Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications

Microelectronics Journal 35 (2004) 291–297 www.elsevier.com/locate/mejo

Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications J. Roig*, D. Flores, S. Hidalgo, J. Rebollo, J. Millan Centro Nacional de Microelectro´nica (CNM-CSIC), Campus UAB, Bellaterra, 08193 Barcelona, Spain

Abstract This work is addressed to the investigation of the electro-thermal performance of RF-LDMOS transistors integrated in TF-SOI, TF-SOS and thinned TF-SOS substrates by means of numerical simulations. Reported experimental trap density, carrier mobility and capture crosssection values have been used together with sapphire datasheet thermal properties, in order to provide accurate simulation results. It is found that subthreshold characteristics are the same for all the analysed substrates while blocking-state, on-state and power dissipation process depends on the substrate type. q 2003 Elsevier Ltd. All rights reserved. Keywords: Silicon-on-sapphire; Silicon-on-insulator; LDMOS; RF; Power amplifier

1. Introduction Recent advances and new requirements on wireless communications have favoured the research on RF circuits integrated on Silicon-On-Sapphire (SOS) substrates using CMOS technology [1], and the development of power amplifiers on Silicon-On-Insulator (SOI) substrates including LDMOS devices to provide voltage capability up to 30 V [2]. These challenges have also been possible due to the improvement of the Thin Film SOI and SOS (TF-SOI and TF-SOS) substrates manufacturing technologies, leading to high quality active silicon layers. Up to now, LDMOS devices for RF applications are not integrated on SOS substrates because of the low carrier mobility, the high leakage current levels caused by the large trap density [3] and the manufacturing cost of high quality substrates. Advantages of SOI technology vs. bulk technology in the RF application field have been largely reported [4]. The difficulty to combine high-frequency power transistors with high Q on-chip inductors lead to bulk RF amplifiers implemented on standard CMOS technologies with a relatively low level of integration. RF power amplifiers integrated on SOI technology have been recently developed in order to improve the high-frequency performance and to eliminate the cross-talk and latch-up phenomena. Moreover, * Corresponding author. Tel.: þ34-93-594-77-00; fax: þ 34-93-58014-96. E-mail address: [email protected] (J. Roig). 0026-2692/$ - see front matter q 2003 Elsevier Ltd. All rights reserved. doi:10.1016/S0026-2692(03)00187-3

on-chip inductors with a relatively high Q factor can be easily achieved on SOI technology with a low P-type substrate doping concentration and a thick buried oxide. Furthermore, the SOI technology provides better immunity to radiation induced ionisation currents, thus reducing the soft errors in CMOS systems and circuits. In order to fit the electrical performances of SOI RF power amplifiers to the requirements of the new telecommunication standards, a significant effort has been recently devoted to the improvement of SOI LDMOS structures [2,5,6]. On the other hand, CMOS ICs integrated on SOS substrates show several advantages with respect to CMOS ICs integrated on SOI technology. † High Q factor inductors, due to the reduction of substrate losses. † Better heat extraction capability from the active silicon layer in dynamic and stationary operation modes since the sapphire thermal conductivity is higher than that of the buried oxide. † Reduction of the parasitic bipolar gain, leading to a smaller current kink magnitude and a higher kink onset voltage. † Reduction of the impact ionisation process, thus increasing the breakdown voltage. The crystallographic quality of the active silicon layer on TF-SOS substrates has been largely improved in the last

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decade [7 –11]. Hence, LDMOS structures for RF power amplifiers seem to be feasible since the leakage current levels can be significantly reduced and carrier mobility enhanced. An LDMOS transistor integrated on SOS substrates was reported on 1997 [12], the linearity required for RF applications being demonstrated. This paper reports for the first time a detailed study of the electro-thermal performance of LDMOS transistors integrated on SOS substrates based on numerical simulations. The reported data on high level trap concentration, low mobility, capture cross-section and sapphire thermal skills have been included in the performed simulations.

Table 1 Physical values for electro-thermal models Symbol

me mh te th NDt NAt

2. Electro-thermal simulations

se

Electro-thermal simulations have been carried out with DESSIS software [13] to compare the electrical performance of SOS and SOI LDMOS equivalent structures. The cross-sectional view of an SOS LDMOS structure is shown in Fig. 1. The geometrical and technological parameters have been chosen according to the fabricated SOI LDMOS transistors [14] for RF applications. The physical values listed in Table 1 have been introduced into the mobility, recombination and trap models used to perform electrothermal simulations. The interface trap distribution considers a unique state for each type of trap, located at EM þ 0:18 eV for acceptor traps (state 1) and EM 2 0:18 eV for donor traps (state 2), EM being the mid gap energy [7]. These values are relevant to determine the interface recombination term ðRTrap Þ [13], expressed as

sh

RTrap ¼ NAt

gn gp ðnp 2 n2i;eff Þ gn ðn þ nt1 Þ þ gp ðp þ pt1 Þ

þ NDt

gn gp ðnp 2 n2i;eff Þ gn ðn þ nt2 Þ þ gp ðp þ pt2 Þ

ð1Þ

where n; p are the free electron and hole concentrations, NDt ; NAt are the donor and acceptor trap concentrations

Description

Units

Electron mobility at low electric field Hole mobility at low electric field Electron lifetime Hole lifetime Interface donor trap density Interface acceptor trap density Electron capture trap cross-section Hole capture trap cross-section

Values SOI

SOS

cm2 V21 s21

700

500 [7]

cm2 V21 s21

250

200 [7]

s s cm22

3 £ 1027 1 £ 1027 –

1 £ 1029 [1] 1 £ 1029 [1] 1 £ 10211 [7]

cm22

–

1 £ 10211 [7]

cm2

–

1 £ 10215 [11]

cm2

–

1 £ 10215 [11]

and ni;eff is the effective intrinsic density. Hole and electron concentrations corresponding to states 1 and 2 ð pt1;2 ; nt1;2 Þ are defined in Eq. (2) whereas gn ; gp factors are given in Eq. (3). p; nt1;2 ¼ ni;eff expð2; þEt1;2 =kTÞ

ð2Þ

gp;n ¼ np;n th sp;n

ð3Þ

The trap energy of states 1 and 2, measured from the middle of the bandgap, is defined by the Et1;2 term of Eq. (2). Electron and hole thermal velocities and capture cross-sections are represented by np;n th and sp;n ; respectively, in Eq. (3). Values for NDt ; NAt and sp;n are summarised in Table 1 whereas other values are the simulator default ones [13]. SRH bulk recombination models have been used with carrier lifetime values (Table 1) lower than those of the SOI substrates, mainly due to the poor crystallographic quality of the active silicon layer. Moreover, the temperature dependence of the thermal resistivity and capacity for silicon, sapphire and oxide materials is summarised in Table 2. A 500 mm thick sapphire substrate has been Table 2 Thermal properties of silicon, sapphire and oxide

Oxide Silicon

Sapphire

Fig. 1. Simulated TF-SOS LDMOS transistor.

Thermal capacity CH (J/K cm3)

Thermal conductivity k (W/cm K)

1.67 [13] 29 £ 10212 T 4 þ3 £ 1028 T 3 24 £ 1025 T 2 þ1:98 £ 1022 T 21:76 [16] 4 £ 1029 T 3 21 £ 1025 T 2 þ1:27 £ 1022 T þ0:19 [18]

0.007 [15] 3354T 21:342 [17]

803T 21:343 [18]

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considered in all the performed simulations, with a relative dielectric constant of 9.5. On the other hand, a 0.4 mm buried oxide (BOX) layer and 500 mm thick silicon substrate has been used to simulate the equivalent SOI structures. Default dielectric constant values have been applied to silicon and oxide. In addition, LDMOS transistors integrated on thinned TF-SOS substrates have been also analysed. Handle sapphire substrates can be thinned down to 30 mm by etch-back, grinding and mechanical polishing [9]. The quality of the active silicon layer and the sapphire/silicon interface are not affected by these processes. As a consequence, the substrate thermal resistance in the steady state mode can be reduced by more than one order of magnitude.

3. Simulation results 3.1. Blocking state mode Variation on the breakdown voltage ðVbr Þ values in TF-SOI and TF-SOS LDMOS have been found in the performed electro-thermal simulations. As inferred from Fig. 2, simulated Vbr values are 18 and 23 V in TF-SOS and TF-SOI LDMOS transistors, respectively. Breakdown in LDMOS transistors is a consequence of the parasitic bipolar activation. Simulated Vbr values of similar TFSOI and TF-SOS diode structures are higher (40 V) than LDMOS counterparts since no parasitic bipolar structure is present and the breakdown is only due to the impact ionisation process. Besides, TF-SOI LDMOS transistors exhibit a higher Vbr value than the TF-SOS case due to the better optimisation of LDMOS SOI structure.

Fig. 3. Electric field distribution at breakdown in TF-SOS (a) and TF-SOI (b) LDMOS transistors.

The most critical electric field peak region in the TFSOS LDMOS transistor has moved from the bottom of the N-Nþ side (see Fig. 3a) to the top of P –N junction (see Fig. 3b). This is a consequence of the different depletion processes of TF-SOI and TF-SOS. Two reasons can explain the different TF-SOS depletion process: † Absence of BOX/Substrate ‘grounded interface’, which provides a field plate effect, as it was pointed out in Ref. [19]. † Similar dielectric constant value, when moving from silicon to sapphire.

Fig. 2. Blocking state curves for LDIODE and LDMOS structures integrated in TF-SOI and TF-SOS substrates.

It is worth to point out that Poisson equation is not modified due to the donor and acceptor trap charge balance. The vertical electric field at the silicon –sapphire offset region interface is lower than the corresponding value at the BOX – silicon interface, as it can be inferred from Fig. 4. Hence, the vertical spread of the depleted region is narrower

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Fig. 4. Interface vertical electric field profiles at breakdown voltage for LDMOS transistors integrated in TF-SOI and TF-SOS substrates.

at a given drain voltage. In addition, the interface electric field in the offset region can be negative near the P –N junction, leading to accumulation charge regions. According to the electric field distribution plotted in Fig. 3, a geometrical and technological optimisation study has to be carried out in order to increase the blocking capability of TF-SOS diode structure. The mean free path reduction inside the active silicon area in TF-SOS structures due to the worst crystallographic quality has not been taken into account in the impact ionisation models. As a consequence, the avalanche process is underestimated yielding a lower voltage capability. Moreover, the different electric field distribution on TF-SOS and TF-SOI substrates also influences the on-state current distribution across the active silicon layer, as discussed in Section 3.3. Finally, TF-SOS LDMOS transistors exhibit a leakage current level more than one order of magnitude higher than that observed in TF-SOI counterpart (Fig. 2). The increase of leakage current level is mainly due to the trap concentration at the silicon– sapphire interface in TF-SOS substrates. Moreover, the leakage current is not affected by thinning the sapphire substrates. 3.2. Subthreshold characteristics Silicon– sapphire interface trap density has no relevant effect on the threshold voltage ðVTH Þ and subthreshold slope ðSS Þ since the analysed LDMOS transistor works in Partially Depleted (PD) regime and, as a consequence, front and back channel region biasing effects are independent. This can be seen in Fig. 5, where VTH and SS values of 1.3 V and 116 mV/dec, respectively, have been extracted in both TFSOI and TF-SOS LDMOS transistors at a drain voltage of 0.1 V. In spite of the identical VTH and SS values, TF-SOS LDMOS transistors exhibit high leakage current levels and

Fig. 5. Subthreshold characteristics of the TF-SOI and TF-SOS LDMOS transistors.

low drain current at a given gate voltage, due to the carrier mobility degradation in the channel region, in comparison with the TF-SOI counterparts. Once again, TF-SOS and thinned TF-SOS substrates show equal features on VTH and SS values. 3.3. Conduction mode Several differences on the thermo-electrical performance of TF-SOS and TF-SOI LDMOS transistors have been found in conduction mode simulations for gate voltage values ranging from 1 to 10 V. Concerning the on-state characteristics of TF-SOI and TF-SOS LDMOS transistors, two relevant aspects have been observed from numerical simulations: † A decrease of the conduction current level and a premature breakdown have been noticed in TF-SOS LDMOS transistors due to the reduction of the carrier mobility and the increase of the self-heating effect (Fig. 7). Therefore, the SOA is reduced as it can be inferred from Fig. 6a and b. † A reduction of the kink effect due to lower carrier lifetime (Fig. 8) in TF-SOS LDMOS transistors. In fact, the kink effect starts with the activation of the parasitic bipolar transistor due to the injection of holes generated by the impact ionisation process. The shorter the lifetime the larger the recombination process and the lower the injected current, thus reducing the bipolar transistor gain. It is worth to point out that simulated structures suffer from kink effect at gate voltages up to 3 V. This problem is usually solved with the aid of body tie techniques [14], grounding the body region. Taking into account these techniques and the resultant kink effect reduction, the body

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295

Fig. 7. LDMOS drain current and max. temp. vs. drain voltage on TF-SOI, TF-SOS and thinned TF-SOS substrates. VG ¼ 4 V:

the on-state electric field distribution are expected, leading to dissimilar on-state current density distribution. Fig. 9 shows a more homogeneous current density distribution across the offset region in the case of a TF-SOS LDMOS transistor. This is mainly due to the interface vertical electric field reduction and to the accumulation effect, described in Section 3.1. However, the better current distribution homogeneity in steady state mode is not relevant from the conduction point of view since the temperature increase in the active silicon layer is higher in TF-SOS LDMOS transistors due to the heat extraction capability reduction as a consequence of the higher substrate thermal resistance.

Fig. 6. Drain current (solid) and max. temp. (dashed) vs. drain voltage in (a) TF-SOI and (b) TF-SOS LDMOS transistors.

contact spacing can be enlarged in TF-SOS LDMOS transistors, or a higher body doping concentration can be used with the same body contact spacing. Thinned TF-SOS substrates have several advantages over conventional TF-SOS ones operating in steady state conduction regime. The more effective heat extraction process in thinned TF-SOS LDMOS transistors provides higher current levels and breakdown voltage values, as it can be seen in Figs. 7 and 8. On the other hand, a partial kink effect suppression is observed in Fig. 8. Comparing the IðVÞ curves of thinned and conventional TF-SOS substrates, it can be inferred that self-heating effects do not significantly influence the parasitic bipolar activation. Different electric field distribution in blocking operation mode has been observed in TF-SOI and TF-SOS LDMOS transistors (Fig. 3). Hence, similar differences concerning

Fig. 8. Parasitic bipolar activation in LDMOS transistors.

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Fig. 9. Current density distribution across SOS and SOI layer in the middle of the offset region. LDMOS transistor working in saturation regime.

4. Power dissipation process Additional thermal one-dimensional simulations have been carried out with DESSIS software to analyse the selfheating process of the active silicon region on TF-SOI, TFSOS and thinned TF-SOS substrates. The heat generation is emulated by a constant superficial power dissipation pulses per unit area ðPÞ and the thermal resistance and capacitance of the active silicon region is neglected in the performed simulations. The thermal effect of this layer has to be taken into account at higher operating frequencies than those considered in our analysis [20]. Hence, the generated power can only be extracted through the substrate. Adiabatic walls, a series thermal resistance of 0.1 K cm2/W connected to the bottom side and a fixed ambient temperature (300 K) have also been considered. Fig. 10a describes the different heating behaviour of TF-SOI, TF-SOS and thinned TF-SOS substrates when a P ¼ 300 W/cm2 is applied [14]. Two self-heating regimes can be clearly distinguished in TF-SOI substrates when a large enough power pulse is applied. In the first regime, the BOX thermal resistance is predominant and temperature increase ðDTÞ is proportional to the BOX thickness ðtbox Þ: DT reaches a first saturation regime at 1 ms. Then, after some hundreds of ms, the silicon substrate selfheating process becomes relevant and a second DT saturation regime takes place at some tens of ms. On the contrary, TF-SOS and thinned TF-SOS substrates show a unique self-heating regime due to sapphire heating. In this case, the saturation occurs at hundreds of ms in TF-SOS substrates and at less than 10 ms in thinned TF-SOS ones. The faster reach of the substrate bottom by the heat flow produces the observed reduction of the time constant.

Fig. 10. Temperature increase vs. time for (a) constant power dissipation in TF-SOS, thinned TF-SOS and TF-SOI substrates and (b) detail. P ¼ 300 W/cm2, tBOX ¼ 0:4 mm.

Comparing the heating process of TF-SOI and TF-SOS substrates in the BOX heating regime, TF-SOS substrates always exhibit DT values lower than those of their TF-SOI counterparts. In spite of the TF-SOS substrates higher thermal capacitance, their DT values during the cooling process are lower than those of TF-SOI counterparts if the power pulse is shorter than the DT BOX heating regime saturation time (1 ms), as demonstrated in Ref. [21]. For larger power pulses, low duty cycle values are mandatory in TF-SOS substrates to compensate the high heat capacity of the sapphire. These constraints can also be extended to thinned TF-SOS substrates. At very low operating frequency, or steady state mode, the whole sapphire substrate is heated, leading to higher/lower DT values in TF-SOS and thinned TF-SOS substrates, respectively, as previously discussed in this paper. Although devices integrated on TF-SOI and TF-SOS substrates usually do not operate at low frequencies, high temperatures can be achieved in large operation time regimes, where DT is accumulative.

J. Roig et al. / Microelectronics Journal 35 (2004) 291–297

5. Conclusions Performed simulations have shown that LDMOS transistors integrated in TF-SOS substrates exhibit better electro-thermal performances respect to TF-SOI counterparts. A reduction of floating body effect and an increase of the breakdown voltage by optimising the LDMOS transistor has been observed. Despite these advantages, a reduction of the SOA in TF-SOS LDMOS transistors has been found due to the lower carrier mobility and the larger substrate thermal resistance. This problem can be solved by thinning the SOS substrates, thus reducing the thermal resistance one order of magnitude. Subthreshold characteristics are the same in all the analysed substrate types due to the PD nature of the LDMOS transistors. In transient power dissipation process, the active silicon layer of TF-SOS substrates shows a lower temperature increase than that of TF-SOI counterparts at high operating frequencies. Under steady state conditions, the active silicon layer temperature increase is only lower in the case of thinned TF-SOS substrates.

Acknowledgements This work was supported by the Comisio´n Interministerial de Ciencia y Tecnologı´a (CICYT) (ref. TIC2002-02564).

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