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Three-level NPC Inverter SVM Implementation on Delfino DSC
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ScienceDirect PapersOnLine 52-27 (2019) 252–256 Three-level NPC IFAC Inverter SVM Implementation on Delfino DSC Three-level NPC Inverter SVM Implementation on Delfino DSC Three-level Inverter SVM Implementation on Three-level NPC NPCKrzysztof Inverter SVMKrzysztof Implementation on Delfino Delfino DSC DSC Górecki*. Rogowski** Three-level NPCKrzysztof Inverter SVM Implementation on Delfino DSC Górecki*. Krzysztof Rogowski**
Ryszard Krzysztof Beniak***Rogowski** Krzysztof Krzysztof Górecki*. Górecki*. Krzysztof Rogowski** Ryszard Beniak*** Ryszard Beniak*** Krzysztof Górecki*. Krzysztof Rogowski** Ryszard Beniak*** Faculty of Electrical Engineering, Automatic Control and Informatics, Opole University of Technology, Ryszard Beniak*** Faculty Electrical Engineering, Automatic Control and Informatics, Opole University of Technology, Opole,of Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) Faculty of Electrical Engineering, Automatic Control and Opole Faculty of Electrical Engineering, Automatic Control and Informatics, Informatics, Opole University University of of Technology, Technology, Opole, Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) *** (e-mail: [email protected])} Opole, Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) Faculty Electrical Engineering, Automatic Control and Informatics, Opole University of Technology, Opole,of Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) *** (e-mail: [email protected])} *** Opole, Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) *** (e-mail: (e-mail: [email protected])} [email protected])} *** (e-mail: [email protected])} Abstract: The aim of the paper is to present implementation of reduced switch count space vector pulse Abstract: The aimfor of the paper is neutral to present implementation of reduced switchThe count space vector pulse width modulation three-level point clamped inverters (3L-NPC). implementation was Abstract: The aim of the paper to implementation of reduced switch count space vector pulse Abstract: The aimfor of the paper is is neutral to present present implementation of reduced switch(DSC) count space vector pulse widthusing modulation three-level point clamped inverters (3L-NPC). The implementation was done Delfino TMS320F28379D. This dual core digital signal controller is used because of width modulation three-level point clamped inverters (3L-NPC). implementation was Abstract: The aimfor of the paper is neutral to present implementation of reduced switchThe count space vector pulse width modulation for three-level neutral point inverters (3L-NPC). The implementation was done using Delfinonature TMS320F28379D. This dualclamped core In digital signalsolution controller (DSC) is usedpulse because of compute-intensive of implemented modulation. presented the space vector width done using Delfino TMS320F28379D. This dual core digital signal controller (DSC) is used because of width modulation for three-level neutral point clamped inverters (3L-NPC). The implementation was done using Delfino TMS320F28379D. This dual core digital signal controller (DSC) is used because of compute-intensive nature of implemented modulation. In presented solution the space vector pulse width modulation uses prediction algorithm This tomodulation. reduce theIn number of solution individual state in power compute-intensive nature of implemented implemented presented the(DSC) space changes vector pulse width done using Delfino TMS320F28379D. dual core digital signal controller is usedpulse because of compute-intensive nature of modulation. In presented solution the space vector width modulation uses prediction algorithm to reduce the number of individual state changes in power transistors (switch count).ofThis implementation is made becauseoflower number of transistor switching modulation uses prediction prediction algorithm tomodulation. reduce theInnumber number individual state changes in power power compute-intensive nature implemented presented solution the state space vector pulse width modulation uses algorithm to reduce the of individual changes in transistors (switch losses. count).The Thisalgorithm implementation is made becausesets lower number of states transistor switching reduces switching makes use of additional of transistors’ corresponding transistors (switch count). This implementation is because number of transistor switching modulation uses prediction algorithm to reduce the number oflower individual changes in power transistors (switch count). This implementation is made made because lower numberstate of states transistor switching reduces switching losses. The algorithm makes use of additional sets of transistors’ corresponding to voltages at the output of inverter. Measurements of voltage waveforms and execution time of reduces switching losses. The algorithm makes use of additional sets of transistors’ states corresponding transistors (switch count). This implementation is made because lower number of transistor switching reduces switching losses. The algorithm makes use of additional sets of transistors’ states corresponding to voltagescontrol at thealgorithm output ofareinverter. Measurements ofObtained voltage results waveforms andpossibility executionoftime of transistors presented in this paper. indicate further to voltages at the output of inverter. Measurements of voltage and execution time of reduces switching The algorithm makes use of additional setswaveforms of transistors’ states corresponding to voltages at thelosses. output ofare inverter. Measurements ofObtained voltage waveforms andpossibility execution of transistors control algorithm presented inreduction this paper. results indicate oftime further optimization of THD levels and switch count on used DSC. transistors control algorithm are presented in this paper. Obtained results indicate possibility of further to voltages at the output of inverter. Measurements of voltage waveforms and execution time of transistors control algorithm are presented in this paper. Obtained results indicate possibility of further optimization of THD levels and switch count reduction on used DSC. optimization of THD levels and switch count reduction on used DSC. transistors control algorithm are presented in this paper. Obtained results indicate possibility of further © 2019, IFAC Federation ofcount Automatic Control) Hosting by Elsevier Ltd. All rights reserved. optimization of(International THD levels and switchThree-level reduction on used DSC. Keywords: Space Vector Modulation, NPC inverter, Digital Signal Controller (DSC). optimization of THD levels and switchThree-level count reduction used DSC. Keywords: Space Vector Modulation, NPC on inverter, Digital Signal Controller (DSC). Keywords: Keywords: Space Space Vector Vector Modulation, Modulation, Three-level Three-level NPC NPC inverter, inverter, Digital Digital Signal Signal Controller Controller (DSC). (DSC). Keywords: Space Vector Modulation, Three-level NPCswitching inverter, Digital Controller (DSC).for this method of losses. Signal The proof of concept 1. INTRODUCTION switching losses. The proof of concept this method of modulation was presented in (Beniak et al.,for 2017). switching The of for this 1. INTRODUCTION switching losses. losses. The proof proof of concept concept for2017). this method method of of modulation was presented in (Beniak et al., 1. INTRODUCTION 1. INTRODUCTION The Neutral-Point-Clamped PWM Inverter was first switching modulation was presented in (Beniak et al., 2017). losses. The proof of concept for this method of modulation was presented in (Beniak et al., 2017). The above-mentioned method is computationally demanding, 1. Takahashi INTRODUCTION The PWM Inverter was first introduced by Nabae, and Akagi in 1981 modulation presented inoptimization (Beniak et al.,method 2017).demanding, above-mentioned method is computationally The Neutral-Point-Clamped Neutral-Point-Clamped PWM Inverter was(Nabae, first The because of was switch count and many The Neutral-Point-Clamped PWM Inverter was first The above-mentioned method is computationally demanding, introduced by Nabae, Takahashi and Akagi in 1981 (Nabae, 1981). The main reasons to use three-level over two-level The above-mentioned method is computationally demanding, of switch countneeded optimization introduced by Nabae, Nabae, Takahashi TakahashiPWM and Akagi Akagi in 1981 1981 (Nabae, The Neutral-Point-Clamped Inverter was(Nabae, first because method and many trigonometric operations by SVM. Method could be introduced by and in because of count optimization method demanding, and many The above-mentioned method is computationally 1981). The main reasons to use three-level overefficiency, two-level trigonometric topologies are lower harmonic distortion, of switch switch count optimization and many operations needed by tables SVM.method Method could be 1981). The main reasons to use three-level introduced by Nabae, Takahashi and Akagibetter inover 1981two-level (Nabae, because implemented witch pre-computed of switch count 1981). The main reasons to use three-level over two-level trigonometric operations by SVM. Method could be because of switch countneeded optimization and many topologies are lower harmonic distortion, better half of voltage rating of main components and lessefficiency, stress on implemented trigonometric operations needed by tables SVM.method Method could be topologies lower harmonic distortion, better efficiency, witch pre-computed of switch count 1981). Theare main reasons to use three-level over two-level optimal transistors powerful, topologies are lower harmonic distortion, better efficiency, implemented witch switching pre-computed tables of less switch count trigonometric operations neededsequence by tables SVM.onMethod could be half of voltage rating of main components and less stress on motor windings isolation (Kouro et al., 2010, Orfanoudakis implemented witch pre-computed of switch count optimal transistors switching on less powerful, half of voltage rating of main components and less stress on sequence topologies are lower harmonic distortion, better efficiency, single-core Digital Processor (DSC), ifpowerful, thecount realhalf of2010, voltage rating ofetmain components and less stress on optimal transistors switching sequence onofbut less implemented witchSignal pre-computed tables switch motor windings isolation (Kouro et al., 2010, Orfanoudakis et al., Rodríguez al., 2002). On the downside there is optimal transistors switching sequence on less powerful, Digital Signal frequency Processor and (DSC), but if the motor isolation (Kouro et al., 2010, half of windings voltage rating of main components and Orfanoudakis less stress on single-core realcontrol with variable modulation depth is motor windings isolation (Kouro al.,the 2010, Orfanoudakis single-core Digital Signal Processor (DSC), the realal., 2010, Rodríguez et al., 2002). On downside is time optimal transistors switching sequence on but lessif powerful, aet more complex topology (Fig. 1)et and difficulty to there do real single-core Digital Signal Processor (DSC), but ifoption. the realtime with variable frequency and modulation depth is et al., 2010, Rodríguez et al., 2002). On the downside there is motor windings isolation (Kouro et al., 2010, Orfanoudakis control needed, then this kind of solution is not an In et more al., 2010, Rodríguez al., 2002). On the downside is time control with variable modulation depth is apower complex topology (Fig. 1) and difficulty to there do single-core Digital Signal frequency Processor and (DSC), but if the realflow control foret individual inverter (Lai et real al., time control with variable frequency and modulation depth is then of solution isgoal not is an to option. In more complex topology (Fig. 1) and and difficulty to there do real et more al., 2010, Rodríguez et the al., 2002). On the downside is needed, this kind presented DSC implementation the control aapower complex topology (Fig. 1) difficulty to do real needed, then this kind of solution is not an option. In time control with variable frequency and modulation depth is flow control for the individual inverter (Lai et al., 1996). Nevertheless multilevel topologies are increasingly needed, then this kind of solution is not an option. In DSCmodulation implementation goal is to control flow control for the the(Fig. individual inverter (Lai et real al., presented apower more flow complex topology 1) and inverter difficulty(Lai to do frequency and depth, asthe well as reducing switch power control for individual et al., presented DSC implementation the goal is to control needed, then this kind of solution is not an option. In 1996). Nevertheless multilevel topologies are increasingly studied and used. presented DSC implementation goal is to control and modulation depth,areasthe well as reducing switch 1996). flow Nevertheless multilevel topologies are increasingly increasingly power control for the individual inverter (Lai et al., frequency count in and real-time. There many known FPGA 1996). Nevertheless multilevel topologies are frequency modulation depth, as well as reducing switch presented DSC implementation the goal is to control studied and used. frequency and modulation depth, as well as reducing switch count in real-time. There are many known FPGA studied and used. 1996). Nevertheless multilevel topologies are increasingly implementations of SVM for multi-level inverters, as well as studied and used. count in real-time. There many known FPGA frequency modulation depth,are well as reducing switch count in and real-time. There areas (Fan many known FPGA implementations SVM for multi-level inverters, well as studied and used. of as hybrid DSC-FPGA implementation et al., 2014). The implementations of SVM SVMThere for multi-level multi-level inverters, as well well as count in real-time. are many knownas FPGA implementations of for as hybrid DSC-FPGA implementation (Faninverters, et to al.,authors 2014). The most DSC implementation known was hybridrecent DSC-FPGA implementation (Faninverters, et al., al., 2014). 2014). The implementations of SVM for multi-level as wellThe as hybrid DSC-FPGA implementation (Fan et most recent DSC implementation known to authors was implemented on Arduino DUE board, control most recent DSC implementation known was hybrid DSC-FPGA implementation (Fan generating et to al.,authors 2014). The most recent DSC implementation known to authors was implemented on Arduino DUE generating control signals for DSC three-level NPC board, inverter in implemented on Arduino DUE board, generating control most recent implementation known tosimulated authors was implemented Arduino DUE board, generating control signals for on three-level NPCwith inverter simulated in Matlab/Simulink environment maximum obtainable signals for three-level NPC board, inverter simulated in implemented on Arduino DUE generating control signals for three-level in Matlab/Simulink environment withinverter maximum obtainable sampling frequency of 4kHzNPC (Kherroubi et al.,simulated 2017). There Matlab/Simulink environment with maximum obtainable signals for three-level NPC inverter simulated in Matlab/Simulink environment with maximum obtainable sampling frequency of 4kHz (Kherroubi et al., 2017). There are no dual-core, floating point implementations ofobtainable SVM on sampling frequency of 4kHz (Kherroubi et al., 2017). There Matlab/Simulink environment with maximum sampling frequency 4kHz (Kherroubi et al., 2017). There are no DSC dual-core, point implementations of SVM on 32-bit knownfloating toof are dual-core, floating point implementations of on sampling frequency ofauthors. 4kHz (Kherroubi et al., 2017). There are no no DSC dual-core, point implementations of SVM SVM on 32-bit knownfloating to authors. 32-bit DSC known to authors. are no dual-core, floating point implementations of SVM on 32-bit DSC known to authors. The limiting factors in presented implementation are 32-bit DSC known to authors. The limiting factors in presented implementation are rounding errors factors of switching times (1 µs), transistors deadThe limiting limiting in presented presented implementation are The factors in implementation are rounding errors set of switching times (1 µs), transistors deadtime currently at 4 µs, and resulting from it minimal Fig. 1. The main circuit of prototype 3L-NPC converter rounding errors of switching times (1 µs), transistors deadThe limiting factors in presented implementation are rounding errors of switching times (1 µs), transistors deadtime currently at 10 4 µs. µs, In and resultingimplementation from it minimal switching time set atswitching presented the Fig. 1. The main circuit of prototype 3L-NPC converter time currently set at 4 µs, and resulting from it minimal rounding errors of times (1 µs), transistors deadFig. 1. The main circuit of prototype 3L-NPC converter time currently set at 4 µs, and resulting from it minimal Fig. 1. The main circuit of prototype 3L-NPC converter switching time set at 10 µs. In presented implementation the sampling frequency is set to 2 kHz because of aboveThe method usedcircuit is an implementation of space vector pulse time switching time set presented the currently at 10 4 µs. µs, In and resultingimplementation from it minimal Fig. 1. The main of prototype 3L-NPC converter switching time set at at 10 implementation the sampling frequency is µs. set In to presented 2 kHz because of abovementioned limiting factors. The method used is an implementation of space algorithm vector pulse width modulation (SVM), which uses prediction to sampling frequency is set to 2 kHz because of aboveswitching time set at 10 µs. In presented implementation the The method method used used is is an an implementation implementation of of space space vector vector pulse pulse mentioned sampling frequency is set to 2 kHz because of aboveThe limiting factors. width modulation (SVM), which usesstate prediction algorithm to sampling reduce the number of individual changes in power mentioned limiting factors. frequency is set to 2 kHz because of abovewidthmethod modulation (SVM), which uses uses prediction prediction algorithm to mentioned The used is an implementation of space algorithm vector pulse The aim limiting of the factors. implementation is to control twelve width modulation (SVM), which to reduce the number of individual state changes in power transistors (switch count). Thisuses algorithm makes use of mentioned aim limiting ofoutputs the factors. implementation to control reduce the number of individual state changes in power width modulation (SVM), which prediction algorithm to The independent by one core of theis Delfino Digital twelve Signal reduce the number of individual state changes in power aim of the implementation is to control twelve transistors (switch count). This makes use of The additional sets of transistors’ states algorithm corresponding toinvoltages The aim of the implementation is to control twelve independent outputs by one core of the Delfino Digital Signal transistors (switch count). This algorithm makes use of reduce the number of individual state changes power Processor (DSC), with 1 µs time resolution using n×2 integer transistors (switch count). This algorithm makes use of independent outputs by one one core of of the theisDelfino Delfino Digital twelve Signal additional setsofofinverter transistors’ states corresponding to voltages The aim ofoutputs the implementation to control at the output in aThis way algorithm that reducemakes switch count. independent by Digital Signal Processor (DSC),bywith 1 µs core additional sets of transistors’ states corresponding to voltages transistors (switch count). use of array time resolution using n×2 integer computed the coreof ofthe DSC. The array additional sets ofinverter transistors’ corresponding to to voltages Processor (DSC), with 1one µs core time resolution using n×2contains integer at the output of inswitch astates waycount that reduce switch count. independent outputs byother Delfino Digital Signal Finding ways to decrease is necessary avoid Processor (DSC), with 1 µs time resolution using n×2 integer at in aastates way that reduce switch count. array computed by the other core of DSC. The array contains additional setsofofinverter transistors’ corresponding to voltages at the the output output waycount that reduce switch computed the other core of DSC. The array Finding ways of to inverter decreaseinswitch is necessary to count. avoid array Processor (DSC),by with 1 µs time resolution using n×2contains integer array computed by the other core of DSC. The array contains Finding ways to decrease necessary avoid at the output a waycount that is reduce switchto Finding ways of to inverter decreaseinswitch switch count is necessary to count. avoid array computed by the other core of DSC. The array contains Finding ways to decrease switch count is necessary to 2405-8963 © 2019, IFAC (International Federation of Automaticavoid Control) Hosting by Elsevier Ltd. All rights reserved. Peer review under responsibility of International Federation of Automatic Control. 10.1016/j.ifacol.2019.12.647
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sequence of transistors’ conducting states changes with timing information calculated using SVM method. This kind of setup can also be used for testing of other control methods for Three-level NPC (3L-NPC) inverter. For implementation of switch count reduction method the TMS320F28379D microcontroller was used. It is new 32-bit floating point C2000 Delfino dual core DSC. The series digital signal controllers being developed by Texas Instruments company is worth noticing. Every core has F28x CPU floating point unit (FPU), trigonometric math unit (TMU), and Viterbi complex math unit (VCU-II). Additionally it has the Control Law Accelerator (CLA). It is an independent 32-bit floating point math processor for reading ADC samples “just-in-time”. This unit works parallel and can work as a pre-processing unit for main CPU. Combination of two C28x units and two fast CLA provides 800 MIPS of total system performance. This Delfino series has some important peripherals for power electronics. It has many flexible PWM modules with many modes. Delfino TMS320F2837xD offer four 16-bit analog to digital converters, enabling precision measurement in power control applications. These features in connection with power control peripherals make a powerful tool for power electronic devices. 2. MODULATION METHOD The modulation method used in this research is a modified symmetric space vector modulation for 3L-NPC inverter which uses vector coordinate transposition to reduce calculations of switching times to two-level inverter complexity (Zygmanowski et al., 2006), and prediction algorithm to decrease switch count needed to synthesize desired waveforms at the output of the inverter (Beniak et al., 2017). It was found in previous research that additional sets of transistors’ states, which are not common in use, can be potentially used to synthesize some of the 19 output voltage states of 3L-NPC inverter. By using those additional sets and predictive optimization it is possible to reduce switch count. In current state of research only those of additional transistors’ sets which do not require measurement of the inverter output current flow are used. Using those additional sets in predictive optimization causes the reduction of switch count up to about 20%. The reduction starts from half of modulation depth and frequency (U/f=const.) and is at its maximum at full modulation depth and frequency. Predictive optimization uses table of transistors’ sets that corresponds to output voltages and uses those sets which need less switching to synthesize desired voltage changes for two steps ahead. For example, if the current state of inverter’s transistors is 001111000011 (T1–T12), where 0 denotes OFF, and 1 denotes ON state, and the next voltage in PWM sequence can be synthesized by 4 different sets (011011000110, 001101100011, 001011000010, 001101000011) then the algorithm chooses 001101000011 set, because only one transistor changes its state. This method was presented in detail in (Beniak et al., 2017).
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In the SVM modulation rotating magnetic field is represented as U0 vector rotating in a complex coordinate system. Every inverter has a finite number of switching voltage vectors, which represents the number of combinations of output voltages. This vectors form a regular hexagon in the complex plane. 2-level inverters have 6 active and one zero voltage vector; 3-level inverters have 18 active and one zero voltage vector. If sampling time TC is constant and sufficiently small the U0 vector is considered constant in that time. The U0 is then synthesized as a weighted average combination of three adjacent switching voltage vectors (Fig. 2), from which two are active and one is zero voltage vector. The switching time (t0, t1, t2) of each vector adjacent to U0 is calculated by using (1) and (2) where Uw are active voltage vectors. Thanks to the coordinate transposition method the calculation of switching times for 3-level inverter is analogous to calculation for 2-level inverter.
TC U 0 (ω0t ) = t1U wi + t2 U w(i +1)
(1)
t0 = TC − t1 − t2
(2) Temporal resolution is set to tr=1 µs, which means that every calculated switch time within the TC sampling period is rounded to 1 µs resolution. This SVM implementation uses calculated switching times in a sequence shown in Fig. 3 to obtain more symmetric PWM pulses. This method is known as symmetric space vector modulation and it is used to obtain a better harmonic distortion. As a result of using symmetric SVM there are up to seven changes of the inverter’s output voltages per sampling period TC.
Fig. 2. Rotating vector U0 synthesized as a switched combination of three adjacent vectors Uw0, Uw1, Uw2
Fig. 3. Symmetric PWM switching sequence of switching voltage vectors in sampling time TC 3. IMPLEMENTATION The TMS320F2837xD dual core DSC was used to implement presented method of 3L-NPC inverter modulation. Because of novel approach of the presented method of modulation, and undergoing research to improve it, there was a need to have as much spare computing power as possible. The use of dual core DSC gives the possibility of on-line calculations of
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switching times with switch count reduction method. The Inter-Processor Communication (IPC) of the DSC is used to achieve that. 3.1 Dual-Core Inter-Processor Communications (IPC) This dual core DSC has a few IPC features: message RAMs, IPC command registers, IPC flags and interrupts flash pump semaphore, clock configuration semaphore and free-running counter. The first two of them were used for the implementation of SVM modulation algorithm. The CPU1 calculate the table of switching sequence with timing. This information is transmitted via shared RAM. TMS320F28379D contains two blocks of such RAM. Each block size is 1K words. These blocks are used to transfer messages or data between CPU1 and CPU2. Each of the blocks of memory needs to be initialized as read/write or read-only to the appropriate CPU. Then CPU1 can transmit data to CPU2. It is important to provide information to CPU2 that it can receive data from memory. IPC command registers were used for this purpose. 3.2 SVM implementation using two cores In this implementation one core of the DSC (CPU2) is designated only to set twelve independent outputs, with 1 µs time resolution, using data computed by the other core (CPU1). This was done by using 6 ePWM DSC modules with twelve high resolution outputs. ePWM1 to ePWM6 are synchronized together. PWM output state is forced at the end of each 1 µs PWM period through software control with action qualifier submodule. Every 1 µs epwm1_isr interrupt function is called and sets outputs according to n×2 integer array computed by the other core (CPU1) of the DSC. The array consisting of switching sequence with timing computed by CPU1 is send to shared memory. CPU1 sets flag informing CPU2 that the data is ready for reading. CPU2 loads new data into one of two data arrays, A or B. If CPU2 sets outputs from array A in current TC sampling period, then new data will be loaded to array B. After data loading from shared memory the CPU2 sets appropriate flag to inform CPU1 that the data was loaded. In next TC sampling period CPU2 will be using data from array B to sets outputs and load new data to array A. The alternating data flow is presented in Fig. 4 by dashed line. CPU1 is calculating switching times of voltage vectors according to given U0 vector. Output voltage and frequency of the inverter is set by controlling U0 rotational speed and length in a discrete manner over TC sampling period. With U0 parameters set, the CPU1 calculate position of U0 in complex plane. For over half of the depth of modulation (U0 outside of inner two-level hexagon) the U0 coordinates are transposed to one of six outer two-level hexagons. Calculations of U0 trajectory, as well as U0 transposition, uses transitions between Cartesian and polar coordinates. To speed up these Fig. 4. Block flow diagram of the 3L-NPC modulation algorithm implemented on dual core DSC
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calculations the TMU of the DSC is used. Because every two-level hexagon have different switching vectors sequences the look-up table of those sequences is changed accordingly. Next, the switching times (t0, t1, t2) are calculated. If calculated switching times are too short for practical use (e.g. because of minimal dead-band time) there are spread proportionally to the other switching times. After those calculations switch count reduction algorithm chooses optimized transistor conducting states corresponding to given switching voltage vectors sequence. Then if the ready flag is set by the CPU2 next sequence of transistors’ states witch timing are loaded to shared memory, and the appropriate flag is set to inform the CPU2 that the next data array is ready. The process is shown in Fig. 4.
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contains six IGBT transistors (VCE = 1200 V, ICnom=150 A) and six clamping diodes (VRRM=1200 V, IF=150 A). Motor is a 3-phase induction motor Elektrim Sa71-4A, 380 V, 50 Hz, 0.84 A (wye connection), cos ϕ=0.68. The steady state was measured with the Power Quality Analyser TOPAS 1000 made by LEM NORMA GmbH. Table 2. The execution time (maximum) and cycles of SVM TC calculations Optimization level No optimization
PWM calculations cycles time
Opt. level 0
cycles time
3.3 DSC trigonometric operation acceleration
Opt. level 1
The TMU unit allows for a significant acceleration of trigonometric operations. In case of the SVM modulation algorithm, these are the operations in question: sin(b*2π), cos(b*2π), atan(b)/2π, sqrt(b) (square root) and quadrant(x,y) (return the quadrant value (0.0,±0.25, or ±0.5) and the ratio of x and y, which are provided as per unit values). Quadrant operation in conjunction with atan(b)/2π is used in calculating function atan2(y,x) is expected (x, y – Cartesian coordinates). Executing time of these operations are presented in Table 1.
Opt. level 2
cycles time
Table 1. TMU supported instructions which are used in SVM modulation algorithm Operation
Pipeline cycles
a = sqrt(b)
5
a = sin(b*2pi)
4
a = cos(b*2pi)
4
a = atan(b)/2pi
4
quadrant(x,y)
5
cycles time
Opt. level 3
cycles time
Opt. level 4
cycles time
µs µs µs µs µs µs
TMS320 F28379D 9363 46,8 7892 39,5 7626 38,1 6795 34,0 6843 34,2 6843 34,2
The parameters of modulation were set to following values: voltage frequency f=50 Hz, sampling time TC=500 µs, temporal resolution tr=1 µs, transistor dead time td=4 µs. The input phase-phase voltage of the prototype converter was set to 120 V. The calculation time of switching sequence and transfer of these data from CPU1 to CPU2 cannot exceed 500 µs. As can be seen in Table 2. calculation time is considerably less than 500 µs, even without compilation optimization. The lowest calculation time was achieved with level three and four optimization. Although real-time implementation presented in this paper was conducted with 2 kHz sampling frequency, the algorithm execution time suggest that the sampling frequency can be set up to 20kHz, switch count reduction included.
3.4 The measurement of executing time TMS320F28379D was working with the highest stable frequency guaranteed by the producer – 200 MHz. The comparison has been done for compilation without optimization and for five optimization levels: 0 – register optimizations, 1 – local optimizations, 2 – global optimizations, 3 – interprocedure optimizations, 4 – whole program optimizations. The program realizing the SVM modulation algorithm in the main program of first CPU initialized the basic operating parameters of individual peripherals. These results were presented in Table 2. The measurements were made with a prototype converter which was made for testing of the new concepts of modulation for 3L-NPC inverters. IGBT transistors are used as inverter power switches. Transistors are in two FS150R12KE3G modules made by Infineon. Each module
Fig. 5. Voltage waveforms at the output of the prototype converter
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Fig. 6. Current waveforms at the output of the prototype converter The voltage and current waveforms at the output of the prototype converter driven by the DSC with method of modulation presented in this paper can be seen in Fig. 5 and 6. Those measurements were conducted without load on the motor, as a confirmation of correct software implementation and are consistent with previous research of the switch count reduction method. 4. CONCLUSIONS The modified SVM execution time measurements showed that implementations of even more complex real-time control algorithms are possible using dual-core TMS320F28379D microcontroller. This will be used in future to further optimize switching sequence with use of online measurement of the inverter output current flow with two DSC’s CLA units, as well as for drive control and THD optimization. Alternatively the remaining cycles of CPU can be used to shorten sampling time TC. Presented implementation can serve as a hint for others on how to implement computeintensive real-time inverter modulation algorithms on dual core DSCs. REFERENCES Beniak R., and K. Rogowski (2017), A method of reducing switching losses in three-level NPC inverter – Analysis in Steady States, Power Electronics and Drives, Vol. 2 (37), pp. 117–126. Fan B., G. Tan, and S. Fan (2014), Comparison of Three Different 2-D Space Vector PWM Algorithms and Their FPGA Implementations, Journal of Power Technologies, Vol. 94 (3), pp. 176–189. Kherroubi Z.E.A., M. Kermadi, E.M. Berkouk, and Z. Salam (2017), Real Time Implementation of Space Vector Pulse Width Modulation for Three Level Neutral Point Clamped (NPC) inverter using Arduino DUE board, 2017 IEEE Conference on Energy Conversion (CENCON).
Kouro, S., M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodríguez, M. A. Pérez, and J. I. Leon (2010), Recent Advances and Industrial Applications of Multilevel Converters, IEEE Transactions on Industry Electronics, Vol. 57, No. 8, pp. 2553–2580. Lai J.S., and F.Z. Peng (1996), Multilevel Converters – A New Breed of Power Converters, IEEE Transactions on Industry Applications, Vol. 32, Issue: 3, pp. 509–517. Nabae, A., I. Takahashi and A. Hirofumi (1981). A New Neutral-Point-Clamped PWM Inverter, IEEE Transactions on Industry Applications, Vol. IA-17, No. 5, pp. 518–523. Orfanoudakis G. I., S. M. Sharkh, M. A. Yuratich, and M. A.Abusara (2010), Loss Comparison of Two and Threelevel Inverter Topologies, Systems Power Electronics, Machines and Drives, 5th IET International Conference on, pp. 143–148. Rodríguez J., J. S. Lai and F. Z. Peng (2002), Multilevel Inverters: A Survey of Topologies, Controls, and Applications, IEEE Transactions on Industry Electronics, Vol. 49, No. 4, pp. 724–738. Zygmanowski, M., B. Grzesik (2006). Space Vector Modulation for 3-level neutral-point clamped inverter using DSP TMS320F2812, Zeszyty Naukowe. ELEKTRYKA, Politechnika Śląska, Vol. z. 198, pp. 155166.
ScienceDirect PapersOnLine 52-27 (2019) 252–256 Three-level NPC IFAC Inverter SVM Implementation on Delfino DSC Three-level NPC Inverter SVM Implementation on Delfino DSC Three-level Inverter SVM Implementation on Three-level NPC NPCKrzysztof Inverter SVMKrzysztof Implementation on Delfino Delfino DSC DSC Górecki*. Rogowski** Three-level NPCKrzysztof Inverter SVM Implementation on Delfino DSC Górecki*. Krzysztof Rogowski**
Ryszard Krzysztof Beniak***Rogowski** Krzysztof Krzysztof Górecki*. Górecki*. Krzysztof Rogowski** Ryszard Beniak*** Ryszard Beniak*** Krzysztof Górecki*. Krzysztof Rogowski** Ryszard Beniak*** Faculty of Electrical Engineering, Automatic Control and Informatics, Opole University of Technology, Ryszard Beniak*** Faculty Electrical Engineering, Automatic Control and Informatics, Opole University of Technology, Opole,of Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) Faculty of Electrical Engineering, Automatic Control and Opole Faculty of Electrical Engineering, Automatic Control and Informatics, Informatics, Opole University University of of Technology, Technology, Opole, Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) *** (e-mail: [email protected])} Opole, Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) Faculty Electrical Engineering, Automatic Control and Informatics, Opole University of Technology, Opole,of Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) *** (e-mail: [email protected])} *** Opole, Poland, *(e-mail: [email protected]), **(e-mail: [email protected]) *** (e-mail: (e-mail: [email protected])} [email protected])} *** (e-mail: [email protected])} Abstract: The aim of the paper is to present implementation of reduced switch count space vector pulse Abstract: The aimfor of the paper is neutral to present implementation of reduced switchThe count space vector pulse width modulation three-level point clamped inverters (3L-NPC). implementation was Abstract: The aim of the paper to implementation of reduced switch count space vector pulse Abstract: The aimfor of the paper is is neutral to present present implementation of reduced switch(DSC) count space vector pulse widthusing modulation three-level point clamped inverters (3L-NPC). The implementation was done Delfino TMS320F28379D. This dual core digital signal controller is used because of width modulation three-level point clamped inverters (3L-NPC). implementation was Abstract: The aimfor of the paper is neutral to present implementation of reduced switchThe count space vector pulse width modulation for three-level neutral point inverters (3L-NPC). The implementation was done using Delfinonature TMS320F28379D. This dualclamped core In digital signalsolution controller (DSC) is usedpulse because of compute-intensive of implemented modulation. presented the space vector width done using Delfino TMS320F28379D. This dual core digital signal controller (DSC) is used because of width modulation for three-level neutral point clamped inverters (3L-NPC). The implementation was done using Delfino TMS320F28379D. This dual core digital signal controller (DSC) is used because of compute-intensive nature of implemented modulation. In presented solution the space vector pulse width modulation uses prediction algorithm This tomodulation. reduce theIn number of solution individual state in power compute-intensive nature of implemented implemented presented the(DSC) space changes vector pulse width done using Delfino TMS320F28379D. dual core digital signal controller is usedpulse because of compute-intensive nature of modulation. In presented solution the space vector width modulation uses prediction algorithm to reduce the number of individual state changes in power transistors (switch count).ofThis implementation is made becauseoflower number of transistor switching modulation uses prediction prediction algorithm tomodulation. reduce theInnumber number individual state changes in power power compute-intensive nature implemented presented solution the state space vector pulse width modulation uses algorithm to reduce the of individual changes in transistors (switch losses. count).The Thisalgorithm implementation is made becausesets lower number of states transistor switching reduces switching makes use of additional of transistors’ corresponding transistors (switch count). This implementation is because number of transistor switching modulation uses prediction algorithm to reduce the number oflower individual changes in power transistors (switch count). This implementation is made made because lower numberstate of states transistor switching reduces switching losses. The algorithm makes use of additional sets of transistors’ corresponding to voltages at the output of inverter. Measurements of voltage waveforms and execution time of reduces switching losses. The algorithm makes use of additional sets of transistors’ states corresponding transistors (switch count). This implementation is made because lower number of transistor switching reduces switching losses. The algorithm makes use of additional sets of transistors’ states corresponding to voltagescontrol at thealgorithm output ofareinverter. Measurements ofObtained voltage results waveforms andpossibility executionoftime of transistors presented in this paper. indicate further to voltages at the output of inverter. Measurements of voltage and execution time of reduces switching The algorithm makes use of additional setswaveforms of transistors’ states corresponding to voltages at thelosses. output ofare inverter. Measurements ofObtained voltage waveforms andpossibility execution of transistors control algorithm presented inreduction this paper. results indicate oftime further optimization of THD levels and switch count on used DSC. transistors control algorithm are presented in this paper. Obtained results indicate possibility of further to voltages at the output of inverter. Measurements of voltage waveforms and execution time of transistors control algorithm are presented in this paper. Obtained results indicate possibility of further optimization of THD levels and switch count reduction on used DSC. optimization of THD levels and switch count reduction on used DSC. transistors control algorithm are presented in this paper. Obtained results indicate possibility of further © 2019, IFAC Federation ofcount Automatic Control) Hosting by Elsevier Ltd. All rights reserved. optimization of(International THD levels and switchThree-level reduction on used DSC. Keywords: Space Vector Modulation, NPC inverter, Digital Signal Controller (DSC). optimization of THD levels and switchThree-level count reduction used DSC. Keywords: Space Vector Modulation, NPC on inverter, Digital Signal Controller (DSC). Keywords: Keywords: Space Space Vector Vector Modulation, Modulation, Three-level Three-level NPC NPC inverter, inverter, Digital Digital Signal Signal Controller Controller (DSC). (DSC). Keywords: Space Vector Modulation, Three-level NPCswitching inverter, Digital Controller (DSC).for this method of losses. Signal The proof of concept 1. INTRODUCTION switching losses. The proof of concept this method of modulation was presented in (Beniak et al.,for 2017). switching The of for this 1. INTRODUCTION switching losses. losses. The proof proof of concept concept for2017). this method method of of modulation was presented in (Beniak et al., 1. INTRODUCTION 1. INTRODUCTION The Neutral-Point-Clamped PWM Inverter was first switching modulation was presented in (Beniak et al., 2017). losses. The proof of concept for this method of modulation was presented in (Beniak et al., 2017). The above-mentioned method is computationally demanding, 1. Takahashi INTRODUCTION The PWM Inverter was first introduced by Nabae, and Akagi in 1981 modulation presented inoptimization (Beniak et al.,method 2017).demanding, above-mentioned method is computationally The Neutral-Point-Clamped Neutral-Point-Clamped PWM Inverter was(Nabae, first The because of was switch count and many The Neutral-Point-Clamped PWM Inverter was first The above-mentioned method is computationally demanding, introduced by Nabae, Takahashi and Akagi in 1981 (Nabae, 1981). The main reasons to use three-level over two-level The above-mentioned method is computationally demanding, of switch countneeded optimization introduced by Nabae, Nabae, Takahashi TakahashiPWM and Akagi Akagi in 1981 1981 (Nabae, The Neutral-Point-Clamped Inverter was(Nabae, first because method and many trigonometric operations by SVM. Method could be introduced by and in because of count optimization method demanding, and many The above-mentioned method is computationally 1981). The main reasons to use three-level overefficiency, two-level trigonometric topologies are lower harmonic distortion, of switch switch count optimization and many operations needed by tables SVM.method Method could be 1981). The main reasons to use three-level introduced by Nabae, Takahashi and Akagibetter inover 1981two-level (Nabae, because implemented witch pre-computed of switch count 1981). The main reasons to use three-level over two-level trigonometric operations by SVM. Method could be because of switch countneeded optimization and many topologies are lower harmonic distortion, better half of voltage rating of main components and lessefficiency, stress on implemented trigonometric operations needed by tables SVM.method Method could be topologies lower harmonic distortion, better efficiency, witch pre-computed of switch count 1981). Theare main reasons to use three-level over two-level optimal transistors powerful, topologies are lower harmonic distortion, better efficiency, implemented witch switching pre-computed tables of less switch count trigonometric operations neededsequence by tables SVM.onMethod could be half of voltage rating of main components and less stress on motor windings isolation (Kouro et al., 2010, Orfanoudakis implemented witch pre-computed of switch count optimal transistors switching on less powerful, half of voltage rating of main components and less stress on sequence topologies are lower harmonic distortion, better efficiency, single-core Digital Processor (DSC), ifpowerful, thecount realhalf of2010, voltage rating ofetmain components and less stress on optimal transistors switching sequence onofbut less implemented witchSignal pre-computed tables switch motor windings isolation (Kouro et al., 2010, Orfanoudakis et al., Rodríguez al., 2002). On the downside there is optimal transistors switching sequence on less powerful, Digital Signal frequency Processor and (DSC), but if the motor isolation (Kouro et al., 2010, half of windings voltage rating of main components and Orfanoudakis less stress on single-core realcontrol with variable modulation depth is motor windings isolation (Kouro al.,the 2010, Orfanoudakis single-core Digital Signal Processor (DSC), the realal., 2010, Rodríguez et al., 2002). On downside is time optimal transistors switching sequence on but lessif powerful, aet more complex topology (Fig. 1)et and difficulty to there do real single-core Digital Signal Processor (DSC), but ifoption. the realtime with variable frequency and modulation depth is et al., 2010, Rodríguez et al., 2002). On the downside there is motor windings isolation (Kouro et al., 2010, Orfanoudakis control needed, then this kind of solution is not an In et more al., 2010, Rodríguez al., 2002). On the downside is time control with variable modulation depth is apower complex topology (Fig. 1) and difficulty to there do single-core Digital Signal frequency Processor and (DSC), but if the realflow control foret individual inverter (Lai et real al., time control with variable frequency and modulation depth is then of solution isgoal not is an to option. In more complex topology (Fig. 1) and and difficulty to there do real et more al., 2010, Rodríguez et the al., 2002). On the downside is needed, this kind presented DSC implementation the control aapower complex topology (Fig. 1) difficulty to do real needed, then this kind of solution is not an option. In time control with variable frequency and modulation depth is flow control for the individual inverter (Lai et al., 1996). Nevertheless multilevel topologies are increasingly needed, then this kind of solution is not an option. In DSCmodulation implementation goal is to control flow control for the the(Fig. individual inverter (Lai et real al., presented apower more flow complex topology 1) and inverter difficulty(Lai to do frequency and depth, asthe well as reducing switch power control for individual et al., presented DSC implementation the goal is to control needed, then this kind of solution is not an option. In 1996). Nevertheless multilevel topologies are increasingly studied and used. presented DSC implementation goal is to control and modulation depth,areasthe well as reducing switch 1996). flow Nevertheless multilevel topologies are increasingly increasingly power control for the individual inverter (Lai et al., frequency count in and real-time. There many known FPGA 1996). Nevertheless multilevel topologies are frequency modulation depth, as well as reducing switch presented DSC implementation the goal is to control studied and used. frequency and modulation depth, as well as reducing switch count in real-time. There are many known FPGA studied and used. 1996). Nevertheless multilevel topologies are increasingly implementations of SVM for multi-level inverters, as well as studied and used. count in real-time. There many known FPGA frequency modulation depth,are well as reducing switch count in and real-time. There areas (Fan many known FPGA implementations SVM for multi-level inverters, well as studied and used. of as hybrid DSC-FPGA implementation et al., 2014). The implementations of SVM SVMThere for multi-level multi-level inverters, as well well as count in real-time. are many knownas FPGA implementations of for as hybrid DSC-FPGA implementation (Faninverters, et to al.,authors 2014). The most DSC implementation known was hybridrecent DSC-FPGA implementation (Faninverters, et al., al., 2014). 2014). The implementations of SVM for multi-level as wellThe as hybrid DSC-FPGA implementation (Fan et most recent DSC implementation known to authors was implemented on Arduino DUE board, control most recent DSC implementation known was hybrid DSC-FPGA implementation (Fan generating et to al.,authors 2014). The most recent DSC implementation known to authors was implemented on Arduino DUE generating control signals for DSC three-level NPC board, inverter in implemented on Arduino DUE board, generating control most recent implementation known tosimulated authors was implemented Arduino DUE board, generating control signals for on three-level NPCwith inverter simulated in Matlab/Simulink environment maximum obtainable signals for three-level NPC board, inverter simulated in implemented on Arduino DUE generating control signals for three-level in Matlab/Simulink environment withinverter maximum obtainable sampling frequency of 4kHzNPC (Kherroubi et al.,simulated 2017). There Matlab/Simulink environment with maximum obtainable signals for three-level NPC inverter simulated in Matlab/Simulink environment with maximum obtainable sampling frequency of 4kHz (Kherroubi et al., 2017). There are no dual-core, floating point implementations ofobtainable SVM on sampling frequency of 4kHz (Kherroubi et al., 2017). There Matlab/Simulink environment with maximum sampling frequency 4kHz (Kherroubi et al., 2017). There are no DSC dual-core, point implementations of SVM on 32-bit knownfloating toof are dual-core, floating point implementations of on sampling frequency ofauthors. 4kHz (Kherroubi et al., 2017). There are no no DSC dual-core, point implementations of SVM SVM on 32-bit knownfloating to authors. 32-bit DSC known to authors. are no dual-core, floating point implementations of SVM on 32-bit DSC known to authors. The limiting factors in presented implementation are 32-bit DSC known to authors. The limiting factors in presented implementation are rounding errors factors of switching times (1 µs), transistors deadThe limiting limiting in presented presented implementation are The factors in implementation are rounding errors set of switching times (1 µs), transistors deadtime currently at 4 µs, and resulting from it minimal Fig. 1. The main circuit of prototype 3L-NPC converter rounding errors of switching times (1 µs), transistors deadThe limiting factors in presented implementation are rounding errors of switching times (1 µs), transistors deadtime currently at 10 4 µs. µs, In and resultingimplementation from it minimal switching time set atswitching presented the Fig. 1. The main circuit of prototype 3L-NPC converter time currently set at 4 µs, and resulting from it minimal rounding errors of times (1 µs), transistors deadFig. 1. The main circuit of prototype 3L-NPC converter time currently set at 4 µs, and resulting from it minimal Fig. 1. The main circuit of prototype 3L-NPC converter switching time set at 10 µs. In presented implementation the sampling frequency is set to 2 kHz because of aboveThe method usedcircuit is an implementation of space vector pulse time switching time set presented the currently at 10 4 µs. µs, In and resultingimplementation from it minimal Fig. 1. The main of prototype 3L-NPC converter switching time set at at 10 implementation the sampling frequency is µs. set In to presented 2 kHz because of abovementioned limiting factors. The method used is an implementation of space algorithm vector pulse width modulation (SVM), which uses prediction to sampling frequency is set to 2 kHz because of aboveswitching time set at 10 µs. In presented implementation the The method method used used is is an an implementation implementation of of space space vector vector pulse pulse mentioned sampling frequency is set to 2 kHz because of aboveThe limiting factors. width modulation (SVM), which usesstate prediction algorithm to sampling reduce the number of individual changes in power mentioned limiting factors. frequency is set to 2 kHz because of abovewidthmethod modulation (SVM), which uses uses prediction prediction algorithm to mentioned The used is an implementation of space algorithm vector pulse The aim limiting of the factors. implementation is to control twelve width modulation (SVM), which to reduce the number of individual state changes in power transistors (switch count). Thisuses algorithm makes use of mentioned aim limiting ofoutputs the factors. implementation to control reduce the number of individual state changes in power width modulation (SVM), which prediction algorithm to The independent by one core of theis Delfino Digital twelve Signal reduce the number of individual state changes in power aim of the implementation is to control twelve transistors (switch count). This makes use of The additional sets of transistors’ states algorithm corresponding toinvoltages The aim of the implementation is to control twelve independent outputs by one core of the Delfino Digital Signal transistors (switch count). This algorithm makes use of reduce the number of individual state changes power Processor (DSC), with 1 µs time resolution using n×2 integer transistors (switch count). This algorithm makes use of independent outputs by one one core of of the theisDelfino Delfino Digital twelve Signal additional setsofofinverter transistors’ states corresponding to voltages The aim ofoutputs the implementation to control at the output in aThis way algorithm that reducemakes switch count. independent by Digital Signal Processor (DSC),bywith 1 µs core additional sets of transistors’ states corresponding to voltages transistors (switch count). use of array time resolution using n×2 integer computed the coreof ofthe DSC. The array additional sets ofinverter transistors’ corresponding to to voltages Processor (DSC), with 1one µs core time resolution using n×2contains integer at the output of inswitch astates waycount that reduce switch count. independent outputs byother Delfino Digital Signal Finding ways to decrease is necessary avoid Processor (DSC), with 1 µs time resolution using n×2 integer at in aastates way that reduce switch count. array computed by the other core of DSC. The array contains additional setsofofinverter transistors’ corresponding to voltages at the the output output waycount that reduce switch computed the other core of DSC. The array Finding ways of to inverter decreaseinswitch is necessary to count. avoid array Processor (DSC),by with 1 µs time resolution using n×2contains integer array computed by the other core of DSC. The array contains Finding ways to decrease necessary avoid at the output a waycount that is reduce switchto Finding ways of to inverter decreaseinswitch switch count is necessary to count. avoid array computed by the other core of DSC. The array contains Finding ways to decrease switch count is necessary to 2405-8963 © 2019, IFAC (International Federation of Automaticavoid Control) Hosting by Elsevier Ltd. All rights reserved. Peer review under responsibility of International Federation of Automatic Control. 10.1016/j.ifacol.2019.12.647
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sequence of transistors’ conducting states changes with timing information calculated using SVM method. This kind of setup can also be used for testing of other control methods for Three-level NPC (3L-NPC) inverter. For implementation of switch count reduction method the TMS320F28379D microcontroller was used. It is new 32-bit floating point C2000 Delfino dual core DSC. The series digital signal controllers being developed by Texas Instruments company is worth noticing. Every core has F28x CPU floating point unit (FPU), trigonometric math unit (TMU), and Viterbi complex math unit (VCU-II). Additionally it has the Control Law Accelerator (CLA). It is an independent 32-bit floating point math processor for reading ADC samples “just-in-time”. This unit works parallel and can work as a pre-processing unit for main CPU. Combination of two C28x units and two fast CLA provides 800 MIPS of total system performance. This Delfino series has some important peripherals for power electronics. It has many flexible PWM modules with many modes. Delfino TMS320F2837xD offer four 16-bit analog to digital converters, enabling precision measurement in power control applications. These features in connection with power control peripherals make a powerful tool for power electronic devices. 2. MODULATION METHOD The modulation method used in this research is a modified symmetric space vector modulation for 3L-NPC inverter which uses vector coordinate transposition to reduce calculations of switching times to two-level inverter complexity (Zygmanowski et al., 2006), and prediction algorithm to decrease switch count needed to synthesize desired waveforms at the output of the inverter (Beniak et al., 2017). It was found in previous research that additional sets of transistors’ states, which are not common in use, can be potentially used to synthesize some of the 19 output voltage states of 3L-NPC inverter. By using those additional sets and predictive optimization it is possible to reduce switch count. In current state of research only those of additional transistors’ sets which do not require measurement of the inverter output current flow are used. Using those additional sets in predictive optimization causes the reduction of switch count up to about 20%. The reduction starts from half of modulation depth and frequency (U/f=const.) and is at its maximum at full modulation depth and frequency. Predictive optimization uses table of transistors’ sets that corresponds to output voltages and uses those sets which need less switching to synthesize desired voltage changes for two steps ahead. For example, if the current state of inverter’s transistors is 001111000011 (T1–T12), where 0 denotes OFF, and 1 denotes ON state, and the next voltage in PWM sequence can be synthesized by 4 different sets (011011000110, 001101100011, 001011000010, 001101000011) then the algorithm chooses 001101000011 set, because only one transistor changes its state. This method was presented in detail in (Beniak et al., 2017).
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In the SVM modulation rotating magnetic field is represented as U0 vector rotating in a complex coordinate system. Every inverter has a finite number of switching voltage vectors, which represents the number of combinations of output voltages. This vectors form a regular hexagon in the complex plane. 2-level inverters have 6 active and one zero voltage vector; 3-level inverters have 18 active and one zero voltage vector. If sampling time TC is constant and sufficiently small the U0 vector is considered constant in that time. The U0 is then synthesized as a weighted average combination of three adjacent switching voltage vectors (Fig. 2), from which two are active and one is zero voltage vector. The switching time (t0, t1, t2) of each vector adjacent to U0 is calculated by using (1) and (2) where Uw are active voltage vectors. Thanks to the coordinate transposition method the calculation of switching times for 3-level inverter is analogous to calculation for 2-level inverter.
TC U 0 (ω0t ) = t1U wi + t2 U w(i +1)
(1)
t0 = TC − t1 − t2
(2) Temporal resolution is set to tr=1 µs, which means that every calculated switch time within the TC sampling period is rounded to 1 µs resolution. This SVM implementation uses calculated switching times in a sequence shown in Fig. 3 to obtain more symmetric PWM pulses. This method is known as symmetric space vector modulation and it is used to obtain a better harmonic distortion. As a result of using symmetric SVM there are up to seven changes of the inverter’s output voltages per sampling period TC.
Fig. 2. Rotating vector U0 synthesized as a switched combination of three adjacent vectors Uw0, Uw1, Uw2
Fig. 3. Symmetric PWM switching sequence of switching voltage vectors in sampling time TC 3. IMPLEMENTATION The TMS320F2837xD dual core DSC was used to implement presented method of 3L-NPC inverter modulation. Because of novel approach of the presented method of modulation, and undergoing research to improve it, there was a need to have as much spare computing power as possible. The use of dual core DSC gives the possibility of on-line calculations of
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switching times with switch count reduction method. The Inter-Processor Communication (IPC) of the DSC is used to achieve that. 3.1 Dual-Core Inter-Processor Communications (IPC) This dual core DSC has a few IPC features: message RAMs, IPC command registers, IPC flags and interrupts flash pump semaphore, clock configuration semaphore and free-running counter. The first two of them were used for the implementation of SVM modulation algorithm. The CPU1 calculate the table of switching sequence with timing. This information is transmitted via shared RAM. TMS320F28379D contains two blocks of such RAM. Each block size is 1K words. These blocks are used to transfer messages or data between CPU1 and CPU2. Each of the blocks of memory needs to be initialized as read/write or read-only to the appropriate CPU. Then CPU1 can transmit data to CPU2. It is important to provide information to CPU2 that it can receive data from memory. IPC command registers were used for this purpose. 3.2 SVM implementation using two cores In this implementation one core of the DSC (CPU2) is designated only to set twelve independent outputs, with 1 µs time resolution, using data computed by the other core (CPU1). This was done by using 6 ePWM DSC modules with twelve high resolution outputs. ePWM1 to ePWM6 are synchronized together. PWM output state is forced at the end of each 1 µs PWM period through software control with action qualifier submodule. Every 1 µs epwm1_isr interrupt function is called and sets outputs according to n×2 integer array computed by the other core (CPU1) of the DSC. The array consisting of switching sequence with timing computed by CPU1 is send to shared memory. CPU1 sets flag informing CPU2 that the data is ready for reading. CPU2 loads new data into one of two data arrays, A or B. If CPU2 sets outputs from array A in current TC sampling period, then new data will be loaded to array B. After data loading from shared memory the CPU2 sets appropriate flag to inform CPU1 that the data was loaded. In next TC sampling period CPU2 will be using data from array B to sets outputs and load new data to array A. The alternating data flow is presented in Fig. 4 by dashed line. CPU1 is calculating switching times of voltage vectors according to given U0 vector. Output voltage and frequency of the inverter is set by controlling U0 rotational speed and length in a discrete manner over TC sampling period. With U0 parameters set, the CPU1 calculate position of U0 in complex plane. For over half of the depth of modulation (U0 outside of inner two-level hexagon) the U0 coordinates are transposed to one of six outer two-level hexagons. Calculations of U0 trajectory, as well as U0 transposition, uses transitions between Cartesian and polar coordinates. To speed up these Fig. 4. Block flow diagram of the 3L-NPC modulation algorithm implemented on dual core DSC
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calculations the TMU of the DSC is used. Because every two-level hexagon have different switching vectors sequences the look-up table of those sequences is changed accordingly. Next, the switching times (t0, t1, t2) are calculated. If calculated switching times are too short for practical use (e.g. because of minimal dead-band time) there are spread proportionally to the other switching times. After those calculations switch count reduction algorithm chooses optimized transistor conducting states corresponding to given switching voltage vectors sequence. Then if the ready flag is set by the CPU2 next sequence of transistors’ states witch timing are loaded to shared memory, and the appropriate flag is set to inform the CPU2 that the next data array is ready. The process is shown in Fig. 4.
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contains six IGBT transistors (VCE = 1200 V, ICnom=150 A) and six clamping diodes (VRRM=1200 V, IF=150 A). Motor is a 3-phase induction motor Elektrim Sa71-4A, 380 V, 50 Hz, 0.84 A (wye connection), cos ϕ=0.68. The steady state was measured with the Power Quality Analyser TOPAS 1000 made by LEM NORMA GmbH. Table 2. The execution time (maximum) and cycles of SVM TC calculations Optimization level No optimization
PWM calculations cycles time
Opt. level 0
cycles time
3.3 DSC trigonometric operation acceleration
Opt. level 1
The TMU unit allows for a significant acceleration of trigonometric operations. In case of the SVM modulation algorithm, these are the operations in question: sin(b*2π), cos(b*2π), atan(b)/2π, sqrt(b) (square root) and quadrant(x,y) (return the quadrant value (0.0,±0.25, or ±0.5) and the ratio of x and y, which are provided as per unit values). Quadrant operation in conjunction with atan(b)/2π is used in calculating function atan2(y,x) is expected (x, y – Cartesian coordinates). Executing time of these operations are presented in Table 1.
Opt. level 2
cycles time
Table 1. TMU supported instructions which are used in SVM modulation algorithm Operation
Pipeline cycles
a = sqrt(b)
5
a = sin(b*2pi)
4
a = cos(b*2pi)
4
a = atan(b)/2pi
4
quadrant(x,y)
5
cycles time
Opt. level 3
cycles time
Opt. level 4
cycles time
µs µs µs µs µs µs
TMS320 F28379D 9363 46,8 7892 39,5 7626 38,1 6795 34,0 6843 34,2 6843 34,2
The parameters of modulation were set to following values: voltage frequency f=50 Hz, sampling time TC=500 µs, temporal resolution tr=1 µs, transistor dead time td=4 µs. The input phase-phase voltage of the prototype converter was set to 120 V. The calculation time of switching sequence and transfer of these data from CPU1 to CPU2 cannot exceed 500 µs. As can be seen in Table 2. calculation time is considerably less than 500 µs, even without compilation optimization. The lowest calculation time was achieved with level three and four optimization. Although real-time implementation presented in this paper was conducted with 2 kHz sampling frequency, the algorithm execution time suggest that the sampling frequency can be set up to 20kHz, switch count reduction included.
3.4 The measurement of executing time TMS320F28379D was working with the highest stable frequency guaranteed by the producer – 200 MHz. The comparison has been done for compilation without optimization and for five optimization levels: 0 – register optimizations, 1 – local optimizations, 2 – global optimizations, 3 – interprocedure optimizations, 4 – whole program optimizations. The program realizing the SVM modulation algorithm in the main program of first CPU initialized the basic operating parameters of individual peripherals. These results were presented in Table 2. The measurements were made with a prototype converter which was made for testing of the new concepts of modulation for 3L-NPC inverters. IGBT transistors are used as inverter power switches. Transistors are in two FS150R12KE3G modules made by Infineon. Each module
Fig. 5. Voltage waveforms at the output of the prototype converter
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Fig. 6. Current waveforms at the output of the prototype converter The voltage and current waveforms at the output of the prototype converter driven by the DSC with method of modulation presented in this paper can be seen in Fig. 5 and 6. Those measurements were conducted without load on the motor, as a confirmation of correct software implementation and are consistent with previous research of the switch count reduction method. 4. CONCLUSIONS The modified SVM execution time measurements showed that implementations of even more complex real-time control algorithms are possible using dual-core TMS320F28379D microcontroller. This will be used in future to further optimize switching sequence with use of online measurement of the inverter output current flow with two DSC’s CLA units, as well as for drive control and THD optimization. Alternatively the remaining cycles of CPU can be used to shorten sampling time TC. Presented implementation can serve as a hint for others on how to implement computeintensive real-time inverter modulation algorithms on dual core DSCs. REFERENCES Beniak R., and K. Rogowski (2017), A method of reducing switching losses in three-level NPC inverter – Analysis in Steady States, Power Electronics and Drives, Vol. 2 (37), pp. 117–126. Fan B., G. Tan, and S. Fan (2014), Comparison of Three Different 2-D Space Vector PWM Algorithms and Their FPGA Implementations, Journal of Power Technologies, Vol. 94 (3), pp. 176–189. Kherroubi Z.E.A., M. Kermadi, E.M. Berkouk, and Z. Salam (2017), Real Time Implementation of Space Vector Pulse Width Modulation for Three Level Neutral Point Clamped (NPC) inverter using Arduino DUE board, 2017 IEEE Conference on Energy Conversion (CENCON).
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