Threshold voltage degradation in plasma-damaged CMOS transistors — Role of electron and hole traps related to charging damage

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Microelectron. Reliab., Vol. 36, NO. 1t/12, pp. 1627-1630, 1996 Copyright ~ 1996 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0026 2714/96 $15.00+.00

1Pergamon

Plh S0026--2714(96)00161-8

T H R E S H O L D V O L T A G E D E G R A D A T I O N IN P L A S M A DAMAGED CMOS TRANSISTORS - ROLE OF ELECTRON AND HOLE TRAPS RELATED TO CHARGING DAMAGE T O M A S Z B R O Z E K 1 , Y. D A V I D C H A N 2 and C H A N D R. V I S W A N A T H A N 1 1 Electrical Engineering Dept., University of Calilornia at Los Angeles, CA 90095, USA 2 Rockwell Inl./SEMATECH, Austin, TX 78741, USA Abstract: The paper presents results of study of threshold voltage (VT) degradation in CMOS transistors damaged by higla-field charging. Fowler-Nordheim stress induced VT degradation in devices with latent charging damage due to plasma processing was found to be strongly dependent on device type and diagnostic stress conditions. "Direct" and "reverse" antenna effect for NMOS, and anomalous behavior of PMOS devices are explained with polarity dependent trapping and the model includes generation of hole traps, an effect not considered previously. Copyright © 1996 Elsevier Science Ltd INTRODUCTION Process-induced charging arises due to high-field carrier injection, which results in charge build-up, generation of new traps in the oxide, and interface degradation. The enhanced susceptibility of the interface to degradation and the increase in the oxide trap density persist even after high-temperature annealing steps. Fowler-Nordheim (F-N) stress is usually applied to reveal latent damage. Antenna dependence of stress-induced device parameter change is assumed to be due to process-related damage (charging), while a lack of dependence is generally considered as a lack of charging effect. Analysis of V T shift, although the most obvious and natural approach, may lead, however, to an ambiguous conclusion. Fig. 1 shows stress-induced VT shifts for NMOS and PMOS transistors from a single wafer processed in a damaging plasma environment [1 ]. While NMOS devices show clear antenna dependence, the data for PMOS devices indicate a less consistent behavior, as though PMOS transistors may be less susceptible to charging damage. >

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T. Bro~,ek et al.

In this work we performed a complete analysis of threshold voltage degradation in CMOS devices damaged by high-field charging. "Direct" and "reverse" antenna effect for NMOS and anomalous behavior of PMOS devices are explained with a trap generation model which includes subsequent trapping effects. STRESS-INDUCED L A T E N T D A M A G E IN MOS DEVICES

Experimental Details To investigate the dependence of VT degradation in devices with different amount of latent charging damage, undamaged transistors were subjected to various amount of laboratory F-N stress of either polarity. All devices were from the same wafer and had 0.5 ~tm channel length and 9 nm gate oxide thickness. After the charging damage was introduced, devices were subjected to PMA annealing in N2 (450 oc, 30 min), as in a full process flow. After the anneal, all device parameters relaxed to the initial values. The stressed devices were then subjected to a "diagnostic" F-N injection of either polarity, with V T measurements taken periodically during the stress. Some devices were stressed continuously to monitor "charging curves" during F-N injection. The results given below were qualitatively similar for both polarities of stress used to introduce latent damage. Stress-Generated Electron Traps Fig. 2 shows VT degradation in NMOS devices under positive diagnostic F-N stress. Clear dependence on the amount of latent charging damage can be observed during the whole stress time. This behavior is consistent with a model of filling of electron traps generated previously during high-field oxide charging [2, 3]. Since hole trapping under these conditions is strongly suppressed, interface states and trapped electrons result in net negative oxide charge [4]. Under F-N stress of negative polarity, hole trapping dominates the initial stages of stress, causing negative VT shift [4] and the so-called "reverse" antenna effect (VT shift decreasing with antenna ratio) is observed in damaged NMOS devices (as in Fig. 1). For longer stress times electron trapping takes over and VT shift becomes positive. Enhanced electron trapping (latent damage) causes "hole trapping domination" to be smaller and shorter (Fig. 3). As a result, a "reverse" antenna dependence of negative VT shift is observed for short stress times, while for longer injections VT shift becomes positive and shows a "direct" dependence on the amount of charging damage. For all cases, however, enhanced electron trapping in damaged devices shifts VT toward more positive values (Figs. 2 and 3). The shift is additionally enhanced by negative charge, stored at interface states at VT conditions. Although the model of electron trap generation during process-related charging and corresponding charge buildup during a diagnostic F-N stress may explain VT behavior in NMOS, the model cannot explai a PMOS results. Our measurements on pre-degraded and annealed devices

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Fig. 3. VT shift in NMOS devices under negative F-N stress. Region A corresponds to domination of oxide positive charge. Negative charge dominates in region C. suggest a rather weak antenna (charging damage) dependence of VT shift under diagnostic F-N stress (Fig. 4). Since PMOS devices were subjected to the same charging as NMOS, one could expect similar amounts of additional electron traps in the oxide of both transistor types, increasing with the amount of charging damage. An analysis of "charging curves" measured during diagnostic stress indeed indicates enhanced electron trapping in damaged transistors (Fig. 5). Differences in interface state densities between the devices, which could be a reason for more negative VT shil~ in damaged PMOS devices, were found to be too small to overcompensate the trapped electron charge. A reasonable explanation of this phenomena would involve generation of hole traps, the effect rather unexpected in the gate oxide under high-field stress. Generation of hole trapping centers, however, could have been deduced even from previous studies [5], where an increasing offset of positive charge build-up in charging curves was observed during F-N stress on plasma damaged devices. -12.8

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Stress-Generated Hole Traps A hypothesis of enhanced hole trapping in devices with latent charging damage (in PMOS devices the band-bending during VT test prevents detrapping of holes captured during F-N stress [4]) was checked by subjecting large area PMOS transistors to damaging F-N stress followed by PMA anneal. The results of subsequent substrate hot hole injection (shown in Fig. 6) clearly indicate, that charging stress, which is known to produce large amount of electron traps, also generates hole

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T. Bro2ek et al.

trapping sites. These new hole traps, which lie close to the interface, do not affect "charging curves", but strongly affect net trapped charge and VT degradation [6]. As a consequence, electron trapping, which occurs further from the interface than that of holes, may never dominate the effective oxide charge (the positive effective charge in PMOS also includes charge stored at interface states, which are generated during the diagnostic stress). ">'" 2.5

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Fig. 6. VT changes due to hole trapping during hole injection in PMOS devices pre-damaged with a different amount of F-N injected charge. The damaged devices have as much as 50% more traps. DISCUSSION The above experiments show that transistor response to a diagnostic F-N stress is a complicated combination of the damage created by processing and that introduced during testing. It depends on device type and stress polarity, since they determine conditions for trapping-detrapping phenomena in Si-SiO2 system. Similar to other types of degradation, VT degradation in plasma-damaged devices is device and technology dependent There is no general behavior, which can be expected for AVT. It should be determined for each case separately, since it depends on the initial amount of hole and electron traps and their location in a "virgin" oxide as well as susceptibility of the oxide to electron and hole trap generation under highfield stress. It, of course, will be also affected by interface states, generated by charging and reactivated by a diagnostic stress, as well as those created by the diagnostic stress itself [7]. The contribution and relations between effective charges, related to all these trap types and their occupation during threshold voltage measurements determine the device response to the test. CONCLUSION To summarize, F-N stress induced VT degradation in CMOS devices containing latent charging damage was found to be strongly dependent on device type and diagnostic stress conditions. It is concluded that different VT degradation behavior, observed in damaged CMOS devices can be completely explained by an interaction of latent charging damage with a subsequent diagnostic F-N stress. The effect of previously unreported generation of hole traps allows us to explain the anomalous behavior of PMOS transistors. References

1. X. Li et al., Electronics Lett., 30, 367-8 (1994). 2. J. C. King and C. Hu, IEEE Electron Dev. Lett., 16, 475-7 (1994). 3. D. DiMaria, E. Cartier, D. Arnold, J. Appl. Phys., 73, 3367-84 (1993) 4. T. Bro~.ek, Y. D. Chan, and C. R. Viswanathan, Jpn. J. Appl. Phys., 34, 248-51 (1995). 5. R. Rakkhit, F.P. Heiler, P. Fang, C. Sander, Proc. o f IEEE IRPS, pp. 293-6, 1993. 6. T. Bro~.ek and C. R. Viswanathan, Appl. Phys. Lett., 68, 1826-28 (1996). 7. T. Bro~ek, L. Peng, and C. R. Viswanathan, Proc. 1st Int. Syrup. Plasma Process-Induced Damage, pp. 150-53, 1996.