Threshold voltage extraction in Tunnel FETs

Solid-State Electronics 93 (2014) 49–55

Contents lists available at ScienceDirect

Solid-State Electronics journal homepage: www.elsevier.com/locate/sse

Threshold voltage extraction in Tunnel FETs Adelmo Ortiz-Conde a,⇑, Francisco J. García-Sánchez a, Juan Muci a, Andrea Sucre-González a, João Antonio Martino b, Paula Ghedini Der Agopian b, Cor Claeys c a

Solid State Electronics Laboratory, Simón Bolívar University, Caracas 1080A, Venezuela LSI/PSI/USP, University of São Paulo, Av. Prof. Luciano Gualberto, Trav. 3, No. 158, 05508-010 São Paulo, Brazil c IMEC, Kapeldreef 75, B-3001 Leuven, Belgium b

a r t i c l e

i n f o

Article history: Received 23 September 2013 Received in revised form 21 November 2013 Accepted 20 December 2013 Available online 19 January 2014 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: Tunnel FET (TFET) TFET threshold voltage Threshold voltage extraction Fin TFET

a b s t r a c t This article proposes two possible extrapolation-type methods to extract the threshold voltage of Tunnel Field Effect Transistors (TFETs). The first one, which we call the ‘‘CTR method,’’ makes use of the drain Current-to-Transconductance Ratio function. As this method requires differentiating the drain current with respect to the gate voltage, it is blurred by the amplified effect of measurement noise when applied to real device transfer characteristics. To avoid this effect, a second method is also proposed that uses integration of the drain current with respect to gate voltage instead of differentiation. This second method, which was named ‘‘H1 method’’ when it was originally applied to non-crystalline inversion mode MOSFETs, produces comparable results to those obtained from the CTR method, but it has the advantage of inherently reducing the effect of measurement noise by virtue of the low-pass filtering capacity of integration. Both methods are based on defining threshold voltage as the gate voltage axis intercept of the linearly extrapolated strong conduction behavior of either CRT or H1 functions. This is made possible by approximating the drain current in the strong conduction region of the TFET’s transfer characteristics by a monomial function of the gate voltage. Both methods are illustrated and compared by applying them to measured transfer characteristics of experimental Fin-type TFETs. Ó 2013 Elsevier Ltd. All rights reserved.

1. Introduction As the down scaling of conventional CMOS technology is rapidly approaching fundamental limits [1,2], alternative device structures are constantly proposed to substitute or supplement traditional CMOS type devices. One such device is a gated reverse-biased p– i–n structure, commonly referred to as Tunnel Field-Effect Transistor (TFET). This device is particularly promising for low-power electronics applications [3]. The most prominent feature of TFETs is their capacity for producing an inverse sub-threshold swing (SS) smaller than the 60 mV/decade thermal limit (at 300 K) of conventional inversion mode MOSFETs [1,2,4]. Such a sub-thermal SS is achievable because the drain current in TFETs is produced by carrier injection from source to channel which is predominantly governed by quantum mechanical band-to-band tunneling (BTBT) [5], rather than by diffusion as in MOSFETs. The transconductance (gm) to drain current (ID) ratio (TCR, gm/ID) in the sub-threshold region, also known as device efficiency, is the corresponding impor-

⇑ Corresponding author. Tel.: +58 212 9064010; fax: +58 212 9064025. E-mail addresses: [email protected] (A. Ortiz-Conde), [email protected] (F.J. GarcíaSánchez), [email protected] (J.A. Martino), [email protected] (P.G.D. Agopian), [email protected] (C. Claeys). 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2013.12.010

tant parameter for analog applications, as it portrays the available gain per unit of power dissipation of a FET. Because of their smaller SS, TFETs are capable of TCR values in the sub-threshold region higher than the maximum possible value achievable in conventional inversion mode MOSFETs. Thus, a TFET has the potential for delivering higher gain than a MOSFET for the same power dissipation [6]. Although a variety of TFET models have been proposed [7–13] and continue to be developed, fundamental parameters, such as SS and threshold voltage (VT), are still not as clearly defined for TFETs as they are for conventional inversion mode MOSFETs. For example, the value of SS in TFETs does not remain constant throughout the sub-threshold region but increases with applied gate voltage. SS is therefore usually quoted as an average or overall number evaluated over several decades of ID, from nominally off to nominally on values. In some publications reference is even made to a point-SS in order to reflect the lowest achievable SS value for the performed processing. Likewise, an unequivocal physical mechanism-based definition of threshold voltage does not exist for TFETs, and its extraction remains a challenging task. Therefore it is not uncommon to expediently quote the VT of a TFET as the value of gate voltage (VG) measured at some predefined value of ID. Notwithstanding these ambiguities, being able to determine VT still is a very important task for TFET device assessment and circuit

50

A. Ortiz-Conde et al. / Solid-State Electronics 93 (2014) 49–55

design purposes, as VT affects the ability of reducing the operating voltage demanded by low-power applications. Section 2 discusses the failure of some popular VT extraction methods, used for conventional inversion mode MOSFETs, when they are applied to the measured transfer characteristic of experimental Fin type TFETs. Section 3 then discusses and compares two methods presently proposed to extract the VT of Tunnel Field Effect Transistors (TFETs) from the extrapolation of the drain current behavior in the strong conduction region.

2. Threshold voltage extraction There exist more than ten different extraction methods that can be used to determine the VT of conventional inversion mode MOSFETs [14–16], but it is not immediately evident which of them, if any, could be directly used for TFETs. Because the conduction mechanisms of TFETs are so radically different from those of conventional inversion mode MOSFETs, and since there is a lack of accurate compact models for TFETs, the methodology to extract the value of VT in TFETs has become a subject of some controversy in recent years. As mentioned before, the simplest method that can be used to extract a VT value of any kind of FET is the Constant Current (CC) method. This method determines VT as the value of VG that corresponds to a pre-established, more or less arbitrary, constant value of ID. Because of its simplicity and in spite of its ambiguity, this method is the most widely used by industry to extract the VT of inversion mode MOSFETs. It is also directly applicable to TFETs because of its non-phenomenological nature, and some researchers resort to its use for VT extraction in TFETs [17–19]. On the other hand, others prefer more phenomenological based VT extraction methods, such as the second derivative (SD) method, which has been applied to numerically simulated TFET transfer characteristics [20–23]. We have tested the most promising among the existing VT extraction methods on experimental Fin-type p–i–n TFETs in order to analyze their potential suitability for these devices. The experimental TFETs used were fabricated on (1 0 0) SOI substrates with a 150 nm thick buried oxide using a standard FinFET technology flow described in [24], changing only the source implantation from ptype (for nFET) to n-type (for pTFET). The gate is composed of 5 nm TiN covered by a 100 nm polysilicon layer. The gate dielectric consists of 2 nm HfO2 on 1 nm SiO2. Fin height is 65 nm and the channel doping concentration is the natural unintentional doping of the wafer (Na = 1  1015 cm3). Further characteristics of these devices can be found in [4,25]. Fig. 1 presents typical measured pTFET ambipolar transfer characteristics of one such test device at three values of drain voltage (VD). The device structure is made up of 5 fins with 40 nm width and a channel length of 150 nm. The SD method, originally proposed in 1987 for inversion mode MOSFETs [26], is a transition-type extraction method that determines VT as the VG value at which the second derivative of ID with respect to VG reaches a maximum. Unfortunately the high-pass filter nature of the required double differentiation exacerbates the significant measurement noise that is usually present in experimental transfer characteristics, reducing the effectiveness of the method for many practical TFETs, as can be observed in Fig. 2(a). We wish to mention that, since we are interested in studying the transfer characteristics only for negative gate bias of the present test pTFET device, Fig. 2 and the following figures show only negative values of the gate voltage axis, and thus for convenience this axis has been labeled as VG instead of VG. Three point numerical derivatives with an increment of 10 mV were used to generate Fig. 2. Of course, smoothing techniques could be used to reduce the effect of measurement noise. However, even using smoothed or noise-free simulated characteristics, the SD method still fails

Fig. 1. Measured ambipolar transfer characteristics of an experimental pTFET used for testing, showing linear and semi-logarithmic scales, at three values of drain voltage.

Fig. 2. Illustration of three threshold voltage extraction methods, commonly used for inversion mode MOSFETs, applied to the negative gate bias transfer characteristics of the experimental pTFET device of Fig. 1, at a drain voltage of 0.9 V.

A. Ortiz-Conde et al. / Solid-State Electronics 93 (2014) 49–55

to exhibit a maximum because of the fundamental reasons that will be discussed in following paragraphs. Notwithstanding the inherent noise boosting aspect of differentiation, it does not embody the main problem encountered when applying the SD method to TFETs. The key potential drawback of this method resides in the absence of a clear maximum from the second derivative of the TFET’s transfer characteristics, as is the case for the present experimental Fin-type pTFETs, as clearly revealed in Fig. 2(a). The reason for such absence is that for the second derivative of ID to exhibit a maximum, ID would have to behave at least as a linear-like function of VG once it enters into strong conduction. Or more precisely, it would have to be a monomial-like function of VG of a degree m 6 1. However, the drain current of TFETs in general behaves, to a first approximation, as a convex super-linear function of VG [3,27], i.e., the transconductance increases as VG increases. This suggests that if ID were to be approximated by a polynomial function its order would have to be at least two. Such a polynomial could be further approximated by a monomial function of order larger than one. Such approximate conversions between polynomial and monomial (Power-Law) models have been used before in Thin-Film Transistors [28] and for modeling soft breakdown current in MOS structures [29]. This is the case of the present experimental Fin TFETs’ measured transfer characteristics, as illustrated by the linear scale plot in of Fig. 1 for one of the devices. In fact, the drain current of these TFETs may be satisfactorily approximated in strong conduction by an m-th degree monomial function of the type:

ID ¼ KðV G  V T Þm ;

ð1Þ

where K represents a conductance factor with units of AVm that depends on the device’s physical parameters and on VD, and m is the positive exponent of the approximating monomial with a value >1. For comparison, we wish to recall that the current of a conventional inversion mode MOSFET in saturation is approximately described by a monomial of degree m = 2, and also that monomial Eq. (1) is similar to that frequently used to portray the strong inversion transfer characteristics of non-crystalline inorganic and organic inversion mode MOSFETs [16,30,31]. Successive differentiation can be used as a transition-type extraction method. In general, the location of the transfer function’s transition point from a weak to a strong conduction region can be extracted from the location of the maximum of a successive derivative. Assuming that the strong conduction region can be described by an m-th degree monomial-type function, the maximum corresponding to the transition will show up in the derivative of order Pm + 1. For instance, the first order derivative of a step-like transfer function (m = 0 in the strong conduction region) will present a maximum at the location of the transition. Likewise, the location of the transition of a transfer function that exhibits a linear-like behavior in strong conduction (m = 1) will be given by the maximum in its second order derivative. The justification for the SD extraction method [16], i.e. defining VT at the location of a maximum of the second derivative of ID, may be visualized as follows. Assume a simple level = 1 MOSFET SPICE model, where ID = 0 for VG < VT, and a straight line ID / (VGVT) for VG > VT. The first derivative of this elemental model is a step function that starts at VG = VT, whose derivative (second derivative of ID) is a Dirac Delta function located exactly at VG = VT. Such simple model is not strictly valid for real devices, and thus the second derivative will not be strictly a Dirac Delta function, but it will exhibit a maximum exactly at VG = VT, but only if ID is truly monomial (m = 1). Fig. 3 presents a counterexample that illustrates the uselessness of the SD method when m > 1. Consider a device where ID = I0 for VG < VT, and ID / (VGVT)2 for VG > VT. It is clear that in this case, the SD extraction method will fail because the second derivative of ID does

51

not have a clearly defined maximum. In fact, if we wish to find the location of VT using successive derivatives, we would need to look for a maximum at the third derivative. The transfer characteristics of the present experimental Fintype pTFETs, one of which is shown in Fig. 1, can be satisfactorily described in the strong conduction region by an approximating monomial function of degree m  1 (actually m > 4, as will be shown later). Consequently, differentiating its ID twice with respect to VG cannot, and does not, produce any maximum value, as Fig. 2(a) certainly indicates. Thus, the SD method is completely inadequate for extracting the VT of these devices. Other common VT extraction methods, originally developed for inversion mode MOSFETs, also may fail to extract any meaningful value of VT in TFETs because of similar reasons. For example, the popular Linear Extrapolation (LE) of ID method cannot be used when ID does not become a linear function of VG as the TFET enters into strong conduction, as in the case at hand shown in Fig. 1. The Transconductance-to-Current-Ratio (TCR, gm/ID) method is a more phenomenological transition-based extraction method that relies on defining VT of inversion mode MOSFETs as the value of VG measured at some meaningfully appropriate intermediate point of the TCR curve within its downward excursion from its maximum constant value in the sub-threshold region to its minimum value in the above threshold region [32–36]. The TCR method represents perhaps one of the best methods for inversion mode MOSFETs, but it also turns out to be unsatisfactory for extracting the VT of TFETs. The obstacle here lies on the inability to determine the meaningfully appropriate intermediate point in the TCR curve. In the case of the TFET, the TCR curve is not constant in the subthreshold region, nor does it exhibit a clear inflection point, so that there does not exist a value that can be defined as a reference, as is done with conventional inversion mode MOSFETs. Fig. 2(b) visibly illustrates this difficulty with the transfer characteristics of these experimental TFETs. Another VT extraction method, at times used for inversion mode MOSFETs, is the current-to-square root of the Transconductance Ratio (CsrTR, ID/gm1/2) [37–39], also known as the ‘‘Y-function method.’’ Unfortunately this method is not appropriate either for VT extraction in TFETs. Application of the Y-function is supposed to generate a straight line, from whose extrapolation to zero we may extract a value of VT. Conceptually, it achieves this by dividing the current by the square root of the transconductance in order to cancel the effects of mobility degradation and series resistance, assuming a transfer characteristic that otherwise is a linear function of gate voltage. However, such simplifying assumptions are not normally possible in TFETs, as the present device’s non-linear Y-function, shown in Fig. 2(c), clearly indicates.

3. Extraction methods proposed for TFETs In view of the inability of most VT extraction methods that were originally developed for inversion mode MOSFETs to produce unmistakably meaningful values of the VT in TFETs, we propose here two extrapolation-type methods. Both are centered on the previously mentioned observation that the transfer characteristics of TFETs may be well approximated in the strong conduction region by the monomial function given in (1). The two methods proposed here make use of either the derivative or the integral of the monomial function described in (1), and their application produces the linearization of the behavior of the TFET’s strong conduction transfer characteristics region, where we can assume with sufficient confidence that the dominant conduction mechanism involved is band-to-band tunneling. By virtue of such linearization a consistent threshold voltage value, related to that conduction mechanism, can be extracted by linear extrapolation of that strong

52

A. Ortiz-Conde et al. / Solid-State Electronics 93 (2014) 49–55

Fig. 3. Illustrative plot of ID(VG) and its derivatives for a monomial function with m = 2. For this particular case, the second-derivative (SD) threshold extraction method fails in this case because second-derivative does not have a maximum. However, a third derivative would clearly define the VT at the value of VG where its maximum occurs.

conduction behavior to the gate voltage axis, as will be described in the following subsections. Both methods could possibly offer an alternative vision to enhance the understanding of the meaning of threshold voltage in TFETs. 3.1. Current-to-Transconductance Ratio (CTR) method The first method proposed uses the first derivative of ID to calculate the following function:

CTR ¼

ID ID ¼ dI ¼ D gm dV G

1 d lnðID Þ d VG

:

ð2Þ

which is just inverse of TCR [32–36]. We wish to stress that in general it is not advisable to differentiate originally noisy experimental transfer characteristics. Thus, this CTR method is frequently unreliable for practical situations involving measured transfer characteristics of real TFETs because of the augmented error resulting from the differentiation in (2). Nonetheless, this method is still a useful extraction tool when used on simulated transfer characteristics with little or no noise. Assuming the monomial function approximation to represent the TFET’s transfer characteristics in the strong conduction region, and substituting (1) into (2), yields the following linear function of gate voltage:

CTR ¼

ðV G  V T Þ : m

ð3Þ

The strong conduction region should be understood in the present context as the region where (1) is approximately valid. That means the region where the transfer characteristics approximately behave as a monomial function of gate voltage. Stated in other words, it is the region where the auxiliary functions CTR or H1 exhibit linearlike behavior. The location of the strong conduction region depends on drain bias. As the drain bias increases the onset of strong conduction shifts to ever higher values of gate voltages. This shift has the effect of decreasing the available range width within which (1) may fit the measured transfer characteristics. Fig. 4 shows the implementation of this method on the transfer characteristics of the test TFET measured at three drain voltage values. We wish to remind that this and the remaining figures show only the negative values of gate voltage relevant for the present TFET. Although we can notice in Fig. 4 the amplification of measurement noise caused by the differentiation operation, the strong conduction regions appear to be in general fairly linear as expected. Therefore, the initial assumption that the strong conduction region of the transfer characteristics of TFETs can be adequately approximated by a monomial function of the type described in (1) seems to hold true. More about the validity of this assumption will be discussed later. The CTR can be therefore plausibly fitted at high conduction values by straight lines. Eq. (3) was simultaneously fitted to the three sets of experimental data in

Fig. 4. Current-to-Transconductance Ratio (CTR) as a function of gate voltage for the experimental test pTFET at three drain voltages. Linear extrapolation from the strong conduction region allows extraction of the threshold voltages from the straight lines’ VG axis intercepts and of the monomial exponents from those lines’ slopes.

strong conduction (measured at the three indicated drain biases) assuming DIBL/DIBT = 0 to extract a single value of VT and three values of m. The fitting involves simultaneously adjusting the single value of VT and the three values of m until the total quadratic error is minimized. This condition is imposed because the shift of VT with VD is insignificant in this TFET (DIBL/DIBT  0), as can be inferred also from the observed constancy of the sub-threshold characteristics as drain bias is changed. It is important to be aware of the meaning of the threshold voltage value extracted using these CTR and H1 methods. This VT must be understood as an ‘‘extrapolation’’ type of VT value, in the sense that it represents the extension of a strong conduction behavior, dominant away from threshold, to the transition region, where such behavior is not valid. Therefore, the VT extracted using these two methods is only useful for strong conduction modeling purposes, but it may not be useful to evaluate DIBL/DIBT, which should be modeled by a ‘‘transition’’ type of VT value defined within the weak conduction transition region. It is worth noting that within the sub-threshold region the CTR function directly defines the Sub-threshold Swing, SS, of the transfer characteristics through the relationship: SS = CTR ln (10) = 2.3 CTR. Fig. 4 indicates that the Sub-threshold Swing of the presently studied TFET is SS = 115 mV/dec (CTR = 0.050 V) at VG = 1 V (slightly below VT). This value of SS decreases with decreasing VG reaching the reference value of SS = 60 mV/dec (CTR = 0.026 V) at VG  0.8 V, and continues decreasing thereafter for lower values of VG. This location has been proposed as a figure of merit to evaluate TFET devices [40]. Alternatively, identical information about

A. Ortiz-Conde et al. / Solid-State Electronics 93 (2014) 49–55

SS may be obtained from function H1 instead of CTR. Fig. 5 indicates that the same values of the SS of the presently studied TFET may be directly calculated from H1 through the analogous relationship: SS = H1 ln (10) = 2.3 H1. 3.2. H1 method Considering that the increased measurement noise produced by the CTR method reduces the reliability of the strong conduction region straight line fitting, and that such imprecision causes significant uncertainty in the value of VT extracted by extrapolating these lines, we propose a second extraction method that involves integration of the drain current with respect to VG [41]. The method, called the ‘‘H1 method,’’ has been used already to successfully extract the VT of non-crystalline inversion mode MOSFETs [16,30,42]. As before, we assume that the strong conduction transfer characteristics of TFETs may be adequately approximated by a monomial function. Then, similarly to the CTR method, this second method also produces a linearization of the strong conduction region of the TFET transfer characteristics, but with the added advantage of reducing the effect of measurement noise by virtue of the inherent low-pass filtering action of integration. The H1 function, which was originally introduced to extract the model parameters of pn junctions at very low forward voltages [43], is also a ratio function defined as:

R VG H1 ðV G Þ ¼

I ðV G ÞdV G V Glow D ID

;

ð4Þ

where VGlow is a lower limit of integration that is conveniently selected as the approximate lowest value of VG at which the measured drain current is higher than the observed leakage current. Substitution of (1) into (4), assuming ID ðV G Þ  ID ðV G ¼ V Glow Þ, yields the following linear function of gate voltage:

H1 ðV G Þ ¼

ðV G  V T Þ : mþ1

ð5Þ

Hence, function H1 will behave linearly with gate voltage in the strong conduction region, just as CTR does, but with a slope of 1/ (m + 1) instead of 1/m. Therefore, function H1 can be fitted at high conduction values by straight lines. The values of VT can then be extracted by extrapolating those resulting straight lines to their gate voltage axis intercepts, and the monomial exponent m + 1 can be extracted from the inverse of the straight lines’ slopes. Fig. 5 illustrates the H1 method applied to the same experimental

Fig. 5. H1 function as a function of gate voltage for the experimental test pTFET at three drain voltages. Linear extrapolation from the strong conduction region allows extraction of the threshold voltages from the straight lines’ VG axis intercepts and of the monomial exponents from the lines’ slopes.

53

test pTFET. The values of both parameters extracted by the H1 method, for the three drain voltages considered, are given in the table inset of Fig. 5. They are in general more or less similar to those obtained from the CTR method shown in Fig. 4. However, the absence of noise in the strong conduction region of H1 affords much better reliability when fitting to a straight line. Notice in the table inset of Fig. 5 that using H1 yields almost constant values of m  4.3, whereas the presence of significant noise in the CTR shown in Fig. 4 clearly translates into more erratic resulting values of m. Two decimals are shown for these values of m only for comparison purposes, since using a value of m = 4.3 would suffice for modeling purposes. Thus the uncertainty in the values of VT extracted using H1 is notably reduced with respect to those extracted using the CTR method. In both methods the linear region available to extract data becomes progressively smaller as the drain voltage increases. The main disadvantage of the H1 method with respect to the CTR method resides in that the accumulative effect of integration inherently reduces the VG range over which the function becomes linear. Therefore the H1 method requires that measurement to reach higher VG values than if the CTR method were used. The constancy of the value of K as gate voltage changes for a given value of VD is a good indication to assess the initial assumption of the monomial function suitability to globally represent the behavior of the pTFET’s transfer characteristics in the strong conduction region. The value of K can be calculated introducing the measured data into (1) and using the extracted values of m and VT. The result is shown in Fig. 6 for the three drain voltages considered. We observe in this figure that the value of K remains fairly constant in the respective strong conduction regions, corroborating the appropriateness of the monomial model within that region of the pTFET’s transfer characteristics. Fig. 6 also indicates that the magnitude of VG from which K starts to remain approximately constant increases as the magnitude of VD increases, apparently by an amount close to the VD increment. The magnitude of K is also seen to increase as the magnitude of VD increases, apparently in a superlinear manner. The H1 method procedural effectiveness is confirmed in Fig. 7, which compares the originally measured transfer characteristic to the model, as calculated using (1) with the values of m, VT and K extracted for the experimental test device at three values of VD. We note that within the high conduction region, where Eq. (1) is valid, the model reproduces the original data with good accuracy, as indicated by the calculated corresponding relative errors shown in the lower part of Fig. 7. Measurements from other devices on the

Fig. 6. Conductance factor K as a function of VG for three values of VD, calculated using (1) with the values of m and VT extracted from the test pTFET. The values of K depend non-linearly on VD and become approximately constant with respect to VG for the high conduction region, confirming the adequacy of the monomial model within that region.

54

A. Ortiz-Conde et al. / Solid-State Electronics 93 (2014) 49–55

Fig. 7. Measured transfer characteristics of the test pTFET (solid lines) and strong conduction monomial model playbacks (dashed lines and dots) calculated using the extracted parameters (top part). The corresponding relative errors tend to zero in the strong conduction region (bottom part).

Fig. 8. ATLAS simulated transfer characteristics of the test pTFET (solid lines) and strong conduction monomial model playback (dashed lines and dots) calculated using the indicated extracted parameters. The corresponding relative error (bottom part) is very small in the strong conduction region.

same wafer produce comparable parameter values with good reproducibility, so that the same average values can be used. 4. Model’s validation using ATLAS simulations To demonstrate the adequacy of using the monomial strong conduction model for TFETs, we applied the extraction procedures to ATLAS simulations of the transfer characteristics of a doublegate self-aligned pTFET at room temperature with equivalentoxide thickness (EOT) of 2 nm, a channel length of 150 nm and a fin width of 40 nm. The models used in this simulation were band-to-band tunneling (BTBT), Trap Assisted Tunneling (TAT) and Shockley–Read–Hall (SRH). Simulations are attractive to confirm experimental results, and also because they provide convenient noise-free functions to test procedures. Additional details of these simulations are described in [4]. Fig. 8 shows the simulated transfer characteristics in linear and semi-logarithmic scales together. If we calculate the derivatives of the simulated data we notice that the second derivative does not have a maximum since its magnitude keeps increasing as VG increases. Therefore, the SD extraction method fails even without experimental noise. Fig. 9 illustrates the implementation of the H1 and CTR methods which yielding equal extracted parameter values of VT and m, indicated in the figure. The value of K = 0.142 nA Vm is obtained by introducing the simulated data into (1) and using the extracted values of m and VT. Fig. 8 also presents the strong conduction monomial model playback, as calculated using the indicated extracted parameters. The very small relative error within the strong conduction region, shown in the lower part of the figure, is indicative of the appropriateness of this monomial model to describe the strong conduction of these TFETs.

Fig. 9. H1 function and CTR versus gate voltage for the simulated pTFET, showing very linear behaviors well above threshold, which indicate a monomial-type transfer characteristics in the strong conduction region.

5. Conclusions We have tested several threshold voltage extraction methods, normally used to determine the VT of mono-crystalline inversion mode MOSFETs, and have found that most of these popular methods fail to properly extract trustworthy values of VT when applied to the measured transfer characteristics data of experimental Fintype TFETs. This failure is brought about by the radically different nature of the conduction mechanisms that govern drain current flow in TFETs in general. In fact, the strong conduction transfer

A. Ortiz-Conde et al. / Solid-State Electronics 93 (2014) 49–55

characteristics of TFETs can be satisfactorily approximated by a monomial type function of the gate voltage, reminiscent of the behavior of non-crystalline inversion mode MOSFETs. Consequently we have proposed two possible methods to extract the threshold voltage of Tunnel Field Effect Transistors, the ‘‘CTR method’’ and the ‘‘H1 method,’’ producing comparable results. Both methods have been successfully tested on experimental Fintype TFETs. The CTR method, being based on differentiation, is only suitable for simulated transfer characteristics or when the measurement noise is not very significant. On the other hand, the H1 method, being based on integration, is recommended for experimental transfer characteristics since it offers the advantage of inherently reducing the effect of measurement noise. Acknowledgments The authors want to acknowledge R. Rooyackers from IMEC for supplying the processed TFET devices. References [1] Seabaugh AC, Zhang Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 2010;98:2095–110. http://dx.doi.org/10.1109/JPROC.2010.207047. [2] Claeys C. Trends and challenges in micro- and nanoelectronics for the next decade. Proc 19th Int Conf – Mixed Des Integr Circ Syst (MIXDES) 2012;6226267:37–42. [3] Ionescu AM, Riel H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 2011;479:329–37. http://dx.doi.org/10.1038/nature1067. [4] Agopian PGD, Martino MDV, Filho SGDS, Martino JA, Rooyackers R, Leonelli D, et al. Temperature impact on the tunnel FET off-state current components. Solid-State Electron 2012;78:141–6. http://dx.doi.org/10.1016/ j.sse.2012.05.05. [5] De Michielis L, Lattanzio L, Moselund KE, Riel H, Ionescu AM. Tunneling and occupancy probabilities: how do they affect Tunnel-FET behavior? IEEE Electron Dev Lett 2013;34:726–8. http://dx.doi.org/10.1109/LED.2013.225766. [6] Narang R, Saxena M, Gupta RS, Gupta M. Drain current model for a gate all around (GAA) p–n–p–n tunnel FET. Microelectron J 2013;44:479–88. http:// dx.doi.org/10.1016/j.mejo.2013.04.00. [7] García Bardon M, Neves HP, Puers R, Van Hoof C. Pseudo-two-dimensional model for double-gate tunnel fets considering the junctions depletion regions. IEEE Trans Electron Dev 2010;57:827–34. http://dx.doi.org/10.1109/ TED.2010.204066. [8] Verhulst AS, Leonelli D, Rooyackers R, Groeseneken G. Drain voltage dependent analytical model of tunnel field-effect transistors. J Appl Phys 2011;110. http:// dx.doi.org/10.1063/1.360906. 024510–10. [9] Bhushan B, Nayak K, Rao VR. DC compact model for SOI tunnel field-effect transistors. IEEE Trans Electron Dev 2012;59(10):2635–42. http://dx.doi.org/ 10.1109/TED.2012.220918. [10] Pan A, Chui C-O. A quasi-analytical model for double-gate tunneling fieldeffect transistors. IEEE Electron Dev Lett 2012;33:1468–70. http://dx.doi.org/ 10.1109/LED.2012.220893. [11] Wan J, Le Royer C, Zaslavsky A, Cristoloveanu S. A tunneling field effect transistor model combining interband tunneling with channel transport. J. Appl Phys 2011;110:104503–7. http://dx.doi.org/10.1063/1.365887. [12] Zhang L, He J, Chan M. A compact model for double-gate tunneling field effect transistor and its implications on circuit behaviors. IEEE Int Electron Dev Meeting (IEDM) 2012:6.8.1–4. http://dx.doi.org/10.1109/IEDM.2012.647899. [13] Zhang L, Lin X, He J, Chan M. An analytical charge model for double-gate tunnel FETs. IEEE Trans Electron Dev 2012;59:3217–23. http://dx.doi.org/10.1109/ TED.2012.221714. [14] Liou JJ, Ortiz-Conde A, García-Sánchez FJ. Analysis and design of MOSFETs: modeling, simulation and parameter extraction. New York: Springer; 1998 [ISBN: 978-0-412-14601-5]. [15] Schroeder DK. Semiconductor material and device characterization. 3rd ed. New York: Wiley; 2006. [16] Ortiz-Conde A, García-Sánchez FJ, Muci J, Terán Barrios A, Liou JJ, Ho C-S. Revisiting MOSFET threshold voltage extraction methods. Microelectron Reliab 2013;53:90–104. http://dx.doi.org/10.1016/j.microrel.2012.09.01. [17] Choi KM, Choi WY. Work-function variation effects of tunneling field-effect transistors (TFETs). IEEE Electron Dev Lett 2013;34:942–4. http://dx.doi.org/ 10.1109/LED.2013.226482. [18] Zhang A, Mei J, Zhang L, He H, He J, Chan M. Numerical study on dual material gate nanowire tunnel field-effect transistor. IEEE Int Conf Electron Dev Solid State Circ (EDSSC) 2012;6482880:1–5. http://dx.doi.org/10.1109/ EDSSC.2012.648288. [19] Verhulst AS, Sorée B, Leonelli D, Vandenberghe WG, Groeseneken G. Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor. J Appl Phys 2010;107. http://dx.doi.org/10.1063/1.327704. 024518–8.

55

[20] Boucart K, Ionescu AM. A new definition of threshold voltage in Tunnel FETs. Solid-State Electron 2008;52:1318–23. http://dx.doi.org/10.1016/ j.sse.2008.04.00. [21] Li Y-C, Zhang H-M, Zhang Y-M, Hu H-Y, Wang B, Lou Y-L, et al. Twodimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor. Chin Phys B 2013;22:038501. http:// dx.doi.org/10.1088/1674-1056/22/3/03850. [22] Aswathy M, Biju NM, Komaragiri R. Simulation studies of a tunnel field effect transistor (TFET). Int Conf Adv Comput Commun (ICACC) 2012:138–41. http:// dx.doi.org/10.1109/ICACC.2012.3. [23] Padilla JL, Gamiz F, Godoy A. Impact of quantum confinement on gate threshold voltage and subthreshold swings in double-gate tunnel FETs. IEEE Trans Electron Dev 2012;59:3205–11. http://dx.doi.org/10.1109/ TED.2012.221653. [24] Collaert N, Demand M, Ferain I, Lisoni J, Singanamalla R, Zimmerman P, et al. Tall triple-gate devices with TiN/HfO2 gate stack. Dig Tech Pap Symp VLSI Technol 2005:108–9. http://dx.doi.org/10.1109/.2005.146923. [25] Leonelli D, Vandooren A, Rooyackers R, De Gendt S, Heyns MM, Groeseneken G. Drive current enhancement in p-tunnel FETs by optimization of the process conditions. Solid-State Electron 2011;65–66:28–32. http://dx.doi.org/10.1016/ j.sse.2011.06.03. [26] Wong HS, White MH, Krutsick TJ, Booth RV. Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFETs. SolidState Electron 1987;30:953–68. http://dx.doi.org/10.1016/00381101(87)90132-. [27] Zhang Q, Zhao W, Seabaugh A. Low-subthreshold-swing tunnel transistors. IEEE Electron Dev Lett 2006;27:297–300. http://dx.doi.org/10.1109/ LED.2006.87185. [28] Ortiz-Conde A, García Sánchez FJ, Muci J. Transformation between power-law and polynomial thin-film transistor models. Electrochem Soc Trans 2009;23:405–12. http://dx.doi.org/10.1149/1.318374. [29] Ortiz-Conde A, Miranda E, García-Sánchez FJ, Muci J. Compatibility of cotunneling and power-law models of soft breakdown current in MOS structures. IEEE Int Caribean Conf Circ Dev Syst (Mexico) April 2008:1–4. http://dx.doi.org/10.1109/ICCDCS.2008.454261. [30] Ortiz-Conde A, Cerdeira A, Estrada M, García-Sánchez FJ, Quintero R. A simple procedure to extract the threshold voltage of amorphous thin film MOSFETs in the saturation region. Solid-State Electron 2001;45:663–7. http://dx.doi.org/ 10.1016/S0038-1101(01)00123-X. [31] Kumar Singh V, Mazhari B. Measurement of threshold voltage in organic thin film transistors. Appl Phys Lett 2013;102. http://dx.doi.org/10.1063/1.481219. 253304 – 253304-3. [32] Aoyama K. A method for extracting the threshold voltage of MOSFET based on current components. Simul Semicond Dev Process 1995;6:118–21. http:// dx.doi.org/10.1007/978-3-7091-6619-2_2. [33] Cunha AIA, Schneider MC, Galup-Montoro C, Caetano CDC, Machado MB. Unambiguous extraction of threshold voltage based on the transconductanceto-current ratio. WCM Nanotechnol 2005:139–41. [34] Flandre D, Kilchytska V, Rudenko T. gm/Id method for threshold voltage extraction applicable in advanced MOSFETs with nonlinear behavior above threshold. IEEE Electron Dev Lett 2010;31:930–2. http://dx.doi.org/10.1109/ LED.2010.205582. [35] García-Sánchez FG, Latorre-Rey AD, Liu W, Chen W-C, Lin H-C, Liou JJ, et al. A continuous semi-empiric transfer characteristics model for surrounding gate undoped polysilicon nanowire MOSFETs. Solid-State Electron 2011;63:22–6. http://dx.doi.org/10.1016/j.sse.2011.05.00. [36] Rudenko T, Kilchytska V, Arshad MKM, Raskin J-P, Nazarov A, Flandre D. On the MOSFET threshold voltage extraction by transconductance and transconductance-to-current ratio change methods: Part I – effect of gatevoltage-dependent mobility. IEEE Trans Electron Dev 2011;58:4172–9. http:// dx.doi.org/10.1109/TED.2011.216822. [37] Ghibaudo G. New method for the extraction of MOSFET parameters. Electron Lett 1988;24:543–5. [38] Jain S. Measurement of threshold voltage and channel length of submicron MOSFETs. IEE Proc I: Solid-State Electron Dev 1988;135:162–4. http:// dx.doi.org/10.1049/ip-i-1.1988.002. [39] Tsormpatzoglou A, Papathanasiou K, Fasarakis N, Tassis DH, Ghibaudo G, Dimitriadis CA. A Lambert-function charge-based methodology for extracting electrical parameters of nanoscale FinFETs. IEEE Trans Electron Dev 2012;59:3299–305. http://dx.doi.org/10.1109/TED.2012.222264. [40] Vandenberghe WG, Verhulst AS, Sorée B, Magnus W, Groeseneken G, Smets Q, et al. Figure of merit for and identification of sub-60 mV/decade devices. Appl Phys Lett 2013;102(1). http://dx.doi.org/10.1063/1.477352. Art. No. 013510. [41] Ortiz-Conde A, García-Sánchez FJ, Liou JJ, Ching-Sung Ho. Integration-based approach to evaluate the sub-threshold slope of MOSFETs. Microelectron Reliab 2010;50:312–5. http://dx.doi.org/10.1016/j.microrel.2009.11.00. [42] Ortiz-Conde A, Latorre Rey AD, Liu W, Chen W-C, Lin H-C, Liou JJ, et al. Parameter extraction in polysilicon nanowire MOSFETs using new double integration-based procedure. Solid-State Electron 2010;54:635–41. http:// dx.doi.org/10.1016/j.sse.2010.01.01. [43] Ranuarez JC, García-Sánchez FJ, Ortiz-Conde A. Procedure for the determination of diode model parameters at very low forward voltage. Solid-State Electron 1999;43:2129–33. http://dx.doi.org/10.1016/S00381101(99)00181-1.