Throughout evaluation in digital switching systems with distributed microprocessor control

North-Holland

Microprocessing and Microprogramming 11 (19B3)207-215

Throughput Evaluation in Digital Switching Systems with Distributed Microprocessor Control M. Gruszecki Bell Telephone Mfg. Co., Francis Wellesplein 1, B-2000 Antwerp, Belgium The digital SPC switching systems with distributed/z-processor control discussed in this paper are large #-processor systems providing a variety of telephone and data switching services. Throughput evaluation of such systems usually implies a significant innovation effort as concerns study tools and methods, i.e., simulation and calculation techniques, laboratory and field testing. This paper gives a concise review of these techniques and provides a bibliography.

Keywords: Throughput evaluation, digital switching systems, distributed microprocessor control, simulation techniques, testing.

1. A Large Microprocessor System Modern telecommunication switching systems are stored program controlled (SPC) machines handling voice, data and other kinds of traffic in an environment which tends to be fully digital in switching and transmission. A specific class of these systems, namely digital switching systems with distributed microprocessor control, when compared to other SPC systems, is significantly different in its concept and architecture [1] and may comprise a large number of microprocessors. For example, a system of this type connecting some 20.000 telephone and data lines, may use several hundred microprocessors interconnected via a digital network to control its operation (Fig. 1). The digital switching network itself and various subsystems and modules, in this case consist of a large number of LSI chips, memories, microprocessors etc. The considered system is probably one

of the largest microprocessor systems used at present as concerns the number of microprocessors, the large concentration of LSI components in a single system (e.g. a combined telephone and data switching centre) and the range of product variants.

2. System Throughput The throughput of such a system is determined by the real time capacity of its distributed control i.e. the capacity of its microprocessors to handle a certain amount of messages or call attempts per time unit expressed e.g. in CAPS or BHCA (call attempts per second or busy hour call attempts) and by the traffic capacity of the digital switching network (DSN). The present paper is mainly concerned with the throughput evaluation techniques of the distributed control. The DSN shown in Fig. 2 handles both the speech (and data) traffic and interprocessor messages. It is therefore interesting to mention in this context that the DSN is virtually non-blocking. This high performance is the result of its unique architecture and the use of high availability digital switching elements and efficient selection procedures [2]. Designers must predict the traffic and call or message capacity of the system and check its performance under load conditions. This in turn, has an important impact on system design and architecture. When large microprocessor networks are investigated (which means in practice that complex queuing systems have to be evaluated), throughput evaluation may become very sophisticated and a significant innovation ef-

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fort will be required (tools, methods). The next section gives a brief review of throughput evaluation techniques, concentrating on techniques useful for microprocessor and microprocessor networks in digital switching systems.

3. Throughput

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Techniques

3.1. Simulation Techniques Computer simulation is one of the most commonly used techniques for real time capacity investigation of microprocessors and microprocessor systems [2-4]. The real time capacity simulation models usually consist of the following: -model, image or logical description of the simulated system and its software structure - procedure for generating and offering external stimuli; in the case of switching systems this means traffic, calls, messages - p r o c e d u r e for extracting and recording the desired system characteristics.

Tlae modelling of a distributed control system for traffic simulation and the choice of an appropriate simulation system depend on the stage of development of the system studied (early or advanced design phases, verification on final product, etc.), the objective of the study, the required accuracy of results and the resources available for a given project. We will attempt to point out the different aspects taken into consideration when choosing a simulation model for a distributed control system and classify the simulation models according to the following criteria: - number of simulated processors - modelling accuracy - simulation method Before making a classification of simulation models according to the number of simulated processors, we need an explanation about the structure of the distributed control. Fig. 3 shows in more detail the distributed control already outlined in Fig. 1. In the actual system, the number of equipped control elements (microprocessors) depends on the size of the switching office; there is no limit to

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microprocessor network as a queuing network in which each node is a single server queue with feedback and priorities. In the system considered, the software consists

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of modules known as Finite Message Machine (FMM) distributed between the control elements (nodes). Fig. 4 gives a schematic representation of the different types of messages used in this system and their processing and transmission via the digital switching network. In the example shown, we see the interaction between two FMM's" a) internal message within the same processor (Fig. 4a) b) a message sent from processor A to processor B via a semi-permanent path (Fig. 4b) c) a message sent from A to B via a virtual path i.e. a path established just for this message (Fig. 4c). 3.1.1. N u m b e r o f simulated processors • Single node simulation models. Single micropro-

cessors are isolated and simulated one by one independently or semi-independently of the full microprocessor network. The input offered to these single nodes consists of sequences of

stochastically dependent processes executed by a particular microprocessor. There are several ways of linking the sequences and representing the nodes, which are not simulated, and of increasing in this way the realism of the simulated process representation (please see next section, load and subcall type models). The simplest models of this type i.e. models of a single and isolated microprocessor are useful in investigations of internal software organisations, alternatives, different priority arrangements and interrupt schemes comparisons etc. The more complex single node models can already give certain system characteristics such as the average system delay times, the average queue lengths and in some cases the delay distributions, by making convolutions of distributions obtained in different single nodes. • Multinode models. The entire microprocessor network is simulated and includes all the nodes

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(microprocessors) actually equipped in the system. The traffic model normally used in this type of simulation is the call or subcall-type as explained in

the next section. Obviously, the simulation run times needed for full multinode simulations are much longer than those for single node runs, but

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the results give the full system performance characteristics. Between the two above extreme cases, i.e. the isolated single node and full multinode simulation model, we can have a range of intermediate models. For example, we can simulate part of the distributed microprocessor control having specific characteristics e.g. /z-processors handling the digital and/or analog subscriber lines, a cluster of microprocessors devoted to a specific system function etc. We can also have several intermediate models to represent different strata of software and system architecture details or different ways of linking the nodes, etc. We will now classify traffic simulation models according to the manner in which the simulated process is represented and the exactness of this representation. 3.1.2. Modelling accuracy (in increasing order of

modelling accuracy; this classification is specific to telephone switching systems). • Load-type models. The load at different priority

levels in the processors is precisely simulated; the sequence of action requests to the control is assumed to be a call independent input process. Calls (or complete, message sequences) are not simulated, and therefore the dependencies and feedback effects between different processes are ignored. Steady state conditions are assumed. Process time is statistically generated by probability distributions. This type of simulation is usually used in earlier system development stages. The kinds of results and accuracy which can be obtained with this model are restricted. However, even with this simple model, which can simulate either single node or multinode structures, the accuracy of results can be improved by creating the load with more detailed and realistic elementary sequences. Furthermore, when the system development reaches more advanced stages, the load-type model is usually transformed into more accurate models, viz. subcall-type or call-type models, by linking the elementary sequences and introducing more and more system and their SW details.

• Subcall-type models. Call attempts (or long message sequences) are broken into independent "subcalls" (or "subsequences") like preselection, selection, answer, release, etc. This leads to two basic simplifying assumptions for this model: i) The time correlation between the subcalls of each call is neglected. This means that the input of independent call attempts (or messages) described by a specific input process e.g. Poisson process is replaced by a Poisson input process of independent subcalls. ii) Signalling phases are treated as independent stochastic processes. The advantages of subcall-type simulation, compared to more complex techniques, are: i) Call attempts need not be maintained in the simulator for their real-time duration e.g. 100 seconds. Instead, they appear several times as subcalls, but only for very short periods. ii) Simulation time, storage capacity and cost of simulation runs is reduced. The subcall model can be only used for steady state conditions and in this case can provide many useful results concerning throughput, grade of service, processor occupancy, etc. It can not be used in non-stationary conditions, for eaxmple, in overload control studies or transitory period situations [5]. • Call-type models. All call phases are represented in detail including dialling and signalling phases. The simulation run times and memory requirements are much higher than in more simple models but results are applicable to all traffic conditions including overload and transitory situations. 3.1.3. Simulation methods

We will now very briefly describe the basic modelling principles applied in the simulation of control structures in SPC switching systems. • Discrete-event sequencing. An important property of discrete-event simulations is that events take place without time consumption. The simulated process is divided into instantaneous events and process time, queues etc. are updated at each event. Between events nothing happens in the simulated

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system. This is illustrated in Fig. 5. The discrete-event sequencing is the most commonly used technique for real time capacity investigation of SPC systems.

Load testing of SPC switching systems in the field, although in many cases very attractive, is not easily performed before the cutover of the system. Field testing has also a number of inherent limitations and is mentioned in the present paper on throughput evaluation techniques for the record only. 3.4. Analytical methods

• Time sequencing. Time is advanced at fixed time steps. All model events are updated for each time step. • Quasi-parallel sequencing. The simulation program works partly on one, partly on another process as the simulation progresses. The above-mentioned simulation types (simulations on a general purpose computer) model the SPC control of switching systems by reconstructing in the simulation the structure of the distributed control and the logic of the system software, substituting for elementary statement sequences the processing times needed to execute these sequences. We will now briefly discuss two further tools useful in throughput evaluation of distributed control in SPC switching systems i.e. the simulations using the actual SW and HW and field testing. 3.2. Simulations Using the Actual S W and H W A further step in the direction of a more accurate system representation for simulation of real time capacity, is to use the actual SW and HW. This implies, however', that the system must be built and be available in the laboratory. An appropriate load generator must in this case be used. System characteristics can be observed by external devices e.g. a special processor, logical state analyser(s) or by the system itself. Several other classifications of simulation systems can be made according to e.g. simulation languages used, algorithmic/event/activity or pro-

A review of throughput and performance evaluation methods in SPC switching systems would not be complete without at least mentioning the analytical methods. As concerns probabilistic methods i.e. those based on the queuing theory, hundreds of research papers have appeared in the past few years dealing with many aspects of real time processor capacity studies. Once we come to grips with the formidable mathematics sometimes used in these papers, we may find models and solutions fitting our specific problems [2,6,7]. The papers mentioned in the bibliography [5-23] may be provide a useful introduction. The paper of V. Herzog et al. [Bibl.7] comprises additional bibliography and an excellent review of different analytical models applicable to computer performance evaluation. Papers [Bibl. 9-14] are concerned with queuing networks and tandem queues. Papers [Bibl. 15-17] deal with preemptive priority and feedback queuing systems. Finally, papers [Bibl. 18-21] provide examples of scheduling and processor evaluation studies in SPC systems. References [1] R. Bonami et al.: ITT 1240 Digital exchange architecture. Electrical Communication, vol. 56, hr. 2/3, 1981. [2] J.R. de los Mozos and A. Buchheister: ITT 1240 Traffic handling capacity. Electrical Communication, vol. 56, nr. 2/3, 1981. [3] M. Gruszecki: Entrasim - A real time traffic environment simulator for SPC switching systems. 8th ITC Congress, Nov. 1976, Melbourne.

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[4] J.E. ViUar: Traffic calculations in SPC systems. 8th ITC Congress, Nov, 1976, Melbourne. [5] G. Dietrich and R. Salade: Subcall Type Simulations of SPC switching systems. 8th ITC Congress, Nov. 1976, Melbourne. [6] M. Villen Almiranto, Average Response Times in an M/6/1 Queue with General Feedback and Priorities, 10th Congress, June 1983, Montreal. [7] B. Fontana, Queue with Two Priorities and Feedback, 10th Congress, June 1983, Montreal.

Bibliography A. Digital Switching Systems [1] G. Robin and S. Treves: Progressive Introduction of Digital Switching and Transmission in Existing Networks: Zurich Seminar on Digital Communications. 1978. An expansion of this paper with the title: Pragmatic Introduction of Digital Switching and Transmission in Existing Networks, appeared in Institute of Electrical and Electronics Engineers Transactions on Communications. July 1979. [2] G. Tolusso and S.R. Treves: Application of Distributed Control to Handling Non-Voice Services: Electrical Communication, 1981, vol. 56, nr. 1, pp. 44-56. [3] F. Casali and S.R. Treves: Evolutionary Planning of Digital Switching and Transmission in a Typical Medium Size Town: Telecommunications Networks Planning Conference, October 1980, Paris, paper 111.5.

A. 1. Distributed microprocessor control in digital switching systems [4] Electrical Communication, vol. 56, nr. 2/3, 1981. (Issue devoted to digital switching with distributed #-processor control- S.1240.)

B. Traffic Theory [5] R. Syski: Introduction to congestion theory in telephone systems. Oliver and Boyd - Edinburgh and London, 1960. (A large number of research papers on teletraffic theory can be found in the proceedings of the International Teletraffic Congress I through X, 1955-1983.)

C. Traffic models for common and distributed control processor systems. SPC system performance evaluation. Analytical methods [6] G. Dietrich: Telephone traffic model for common control investigations, Electrical Communication. Vol. 50, 1975. [7] V. Herzog, P. K0hn, A. Zeh: Klassifizierung und Analyse von Verkehrsmodellen fLir das Aflaufgeschehen in Rechnersystemen, Nachrichtentechn. Fachber. Bd. 44, 1972. [8] A.H. Agajanian: A bibliography on system performance evaluation, Computer, Nov. 1975.

[9] K.M. Chandy et ah Approximate analysis of general queuing networks. IBM J. Res. Develop., 19, pp. 43-49 (1975). [10] K.M. Chandy et ah Approximate methods for analyzing queuing network models of computing systems. Computing surveys 10 (3), pp. 281-317 (1978). [11] P.J. Burke: The output of a queuing system. Oper. Res., 4, pp. 699-704 (1956). [12] P.J. Burke: Output processes and tandem queues. Press of Polytechnic Institute of Brooklyn, vol. 22, pp. 419-428 (1972). [13] J.R. Jackson: Networks of waiting lines. Oper. Res., 5, pp. 518-521 (1957). [14] P. KLihn: Analysis of complex queuing networks by decomposition. 8th ITC, p. 236 (1976). [15]W.C. Chan, W.K. Chung, D.Y. Maa: Multiserver computer-controlled queuing system with pre-emptive priorities and feedback, Proc IEEE, vol. 120, nr. 11, Nov. 1973. [16] E. Jensen, M.J. S&nchez Puga and R.B. Haugen: Analytical study of feedback effects on processor traffic in SPC systems, ITC-8, Melbourne, Nov. 10-17, 1976. [17] U. Herzog: Preemption distance priorities in real-time computer systems, Nachrichtentechn. Z. Nr. 25, 1972. [18] U. Herzog: Optimal scheduling strategies for real-time computers. IBM J. Res. 8- Dev. Sept. 1975. [19] Kuchibhotla V. Sastry, R'Y' Kain: On the performance of certain multiprocessor computer organizations, IEEE Trans Computers hr. 11, Nov. 1975. [20] N. Farber: A model for estimating the real time capacity of certain classes of central processors, ITC-6 Munich, Sept. 9-15, 1970. [21] R.J. Jaeger, R.I. Potter: Analysis of processor usage in stored program controlled telephone switching systems, Proc. Int. Conf. Communications, Philadelphia, June 1972.

C. I. Textbooks on queuing theory [22] L. Kleinrock: Queuing systems, vol. 1: Theory (1975), vol. 2: Computer applications (1976), John Wiley 8- Sons, Inc. [23] N.K. Jaiswal: Priority queues, 1968, vol. 50, Academic Press.

D. Simulation techniques References [24] and [25] give a general review and bibliography concerning simulation systems until 1976. [24] L. Kosten: Simulation in traffic theory. 6th ITC, Munich, Sept. 1970. [25] J.E. Villar: Traffic Calculations in SPC systems. 8th ITC, Melbourne, Nov. 1976. Simulation languages [26] through [30]. [26] T. Schribner: Simulation using GPSS. J. Wiley 6" Sons, 1974. [27] P.J. Kiviat, R. Villanueva, H.M. Markowitz: The SIMSCRIPT II programming language. Prentice-Hail, 1968.

M. Gruszecki/ Throughput Evaluation in Digital Switching Systems [28] G. Jonin, J. Sedol: Simulation language PALM. 9th ITC. Torremolinos, Oct. 1979. [29] J. Vaucher: Simulation data structures using SlMULA. Winter Simulation Conference, New York 1971. [30] T. R~geberg and B. Stenseth: TETRASlM - a general purpose program for the simulation of telephone systems. 7th ITC, Stockholm 1973. Textbooks on simulation systems [31] through [34] [31] G. Birtwistle: Discrete Event Modelling. Macmillan 1979, [32] G. Gordon: Systems Simulation. Prentice-Hall 1969. [33] W. Franta: The process view of simulation. North-Holland P.C. 1977. [34] T. R~geberg: Computer Networks and Simulation, edited by S. Schoemaker. North Holland P.C. 1978. Different aspects of processor simulations [35] through [43] [35] G. Dietrich and R. Salade: Subcall Type Simulation of SPC Switching Systems. 8th ITC, Melbourne, Nov. 1976.

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[36] H.L. Powers, G.A. Sellers and K.W. Zweifel: A traffic Simulator for Load Testing ESS. Proceedings of the International Conference on Communications. Philadelphia, June 1972. [37] R. Lehnert: A special processor for fast simulation of queuing networks. 9th ITC, Torremolinos, Oct. 1979. [38] T. Rdgeberg: Computer languages and program systems for traffic simulation purposes. Document of Norwegian Computing Center, Oslo, Nov. 1979. [39] O.G. Soto et al.: An Approach to flexible modelling and simulation for control processor analysis. 9th ITC, Torremolinos, Oct, 1979. i40] R. Addle et al.: A general exchange simulator for capacity studies of telecommunication systems. 9th ITC, Torremolinos, Oct. 1979. [41] F,T. Man, Real-time testing of automatic overload control systems in a laboratory environment, IEEE Trans Communications, Sept. 1973.