TMS 9940 — Single chip microcomputer

Microelectronics and Reliability, Vol 16, pp. 617-626. Pergamon Press,1977. Printed in Great Britain.

TMS

9

9

4

0

-

SINGLE CHIP MICROCOMPUTER*

John D. Bryant and Rick Longiey Texas Instruments Incorporated Houston, Texas

ABSTRACT

-

A brief overview of the 990/9900 computer family is given. The architecture of the newest member of the family, the TMS 9940 microcomputer, is discussed in detail with emphasis on its instruction set, memory organization, and I/O structure. Different methods of prototype development for the TMS 9940 software and hardware are illustrated using other members of the family such as the TMS 9980 microprocessor or the AMPS prototype development system. Typical application examples are given including a low cost data terminal and an intelligent system peripheral.

-

Mask programmable and electrically reprogrammable ROM versions 16 general-purpose registers 4 prioritized interrupts

-

16 user-defined program control flags

-

Timer/event counter on chip

-

-

32 bits general purpose I/O 256 bits I/O expansion

INTRODUCTION

-

Multiprocessor system interface

The continuing evolution of the microcomputer has taken another step forward with the introduction of the TMS 9940 by Texas Instruments Incorporated. The TMS 9940, a 16-bit single-chip microcomputer is the latest addition to the 9900 family of compatible computers ranging up to the 990/10 high performance minicomputer. All family members are based,on the same architecture and instruction set, thus allowing the system designer to choose the proper component while minimizing design costs.

-

Single 5 V power supply

-

Power down mode for low standby power

-

-

TI 990 and TMS 9900 instruction set compatible

-

68 instructions including multiply and divide

-

128 bytes RAM on chip

-

2048 bytes ROM on chip

*Presented

at

5 MHz operation

Abbreviations in this paper include:

The TMS 9940 is truly a single-chip microcomputer containing a 16-bit CPU, memory, and extensive input/ output capability. The memory consists of 128 bytes of read/write random access memory (RAM) and 2048 bytes of either mask programmable read only memory (TMS 9940N) or electrically reprogrammed read only memory (TMS 9940E). The TMS 9940 is directly compatible with all members of the 9900 family of peripherals and is fully supported both by hardware and software development systems. Key features of the TMS 9940 include: -

NMOS silicon gate technology

PC:

Program Counter: A 15 bit hardware register containing the value of the address of the next instruction to be executed.

WP:

Workspace Pointer: An ll bit hardware register containing the value of the address of the beginning of the register file.

CRU: Communication Register Unit. The I/O interface for the TMS 9940 which is software programmable. MPSI: Multiprocessor System Interface. Twowire interface for transferring data in a multiple processor system.

ARCHITECTURE The TMS 9940 (Figure l) is basically a single-chip minicomputer. The CPU sends a memory address to the memory via the A Bus and sends/receives data via the D

t h e SEMINEX 1977 t e c h n i c a l

617

seminar

61~

J.D. Bryant and R. Longley

5 MHz

z

/

~.

A BUS ADDRESS

MEMORY D BUS ~J'--"TROM:2 Kx 8 /q D A i T . ~ T1 J RAM: 128 x 8

PROG

~

1~OLINES

i ,N,.,TI~. ir ! ~ --.---41,

TEST

CONTROL ROM AND LOGIC

CRUIN TD TC

IDLE i rI"OLD ,,-

CRUOUT

J "ROL"I~A

EC

l Fig. 1. TMS 9940 Block Diagram

Bus. T 1, T2, and T3 are 16 bit registers used to store intermediate addresses and operands, PC stores the 15 bit program counter value, and WP stores the 11 bit workspace pointer value. The ALU accepts two independent 8-bit inputs (X and Y) and outputs the 8-bit result to the D Bus with pipelining being used to allow the arithmetic logical unit (ALU) to handle 16-bit data automatically. Operation of the chip is under the direction of the microprogrammed 4000 bit control read-only memory (ROM). Program memory consists of 2K 8-bit bytes of ROM and 128 bytes of RAM and is addressable in bytes with a word being defined as two consecutive bytes. The TMS 9940 employs an advanced memory-to-

memory architecture where blocks of memory, designated as workspace files, replace dedicated hardware registers. A workspace register file contains 16 contiguous memory words (register 0 to 15). Each workspace register may hold data or addresses and function as an operand register, accumulator, address register, or index register. The workspace concept is particularly valuable during operations that require a context switch such as an interrupt or subroutine call. Such an operation, using a conventional multi-register arrangement, requires that at least part of the contents of the register file be stored and reloaded; however, the TMS 9940 can accomplish a complete context switch simply by exchanging the values in the status register, the PC register, and the WP register.

TMS 9940 - Single Microcomputer

619

4

INTERRUPTS

SN74L$251

The TMS 9940 implements four prioritized hardware interrupt levels, with the highest priority being reserved for the RESET function followed by the decrementer and the two user-defined external interrupts. The value of the highest active interrupt level is continuously compared with the interrupt mask contained in the status register. When the level of a pending interrupt is of higher priority than the mask value, the processor recognizes the interrupt and performs a context switch by fetching the next context PC and WP values from the interrupt vector location, storing the previous context PC, WP and status register values into registers 13, 14, and 15 of the new workspace, and loading the interrupt mask with a value that is one less than the interrupt level being serviced to automatically mask out all lower priority interrupts. If a higher priority interrupt becomes active during a service routines, a second context switch occurs to service the higher priority interrupt. When that routine is complete, a return instruction (RTWP) restores the previous service routine parameters to the processor to complete processing of the lower priority interrupt.

IN0

•

,

-

A5

ITIM9905)

8 TO 1

.

OUT0 ~

B

:r ~

8BIT A LATCH C B

C

OOT,,---l,

TMS W40 AICROCOMFI3TER CRUIN

CRUCLK

ltIN

SN74LS259 (T I P/dlgO6) ~

l AI-A8

-

SN74L$00

SN74LS00

C

/ i

Fig. 2. TMS 9940 32-Bit Input/Output Expansion

INPUT/OUTPUT

The 9940 I/O logic consists of three separate interfaces, the general purpose I/O, the 1/O expansion, and the multiprocessor system interface• All I/O data communication with the outside world is through the communications register unit (CRU), a versatile bit-oriented interface. The CRU accesses I/O bits in fields of from I to 16 (specified via CRU instruction) with each bit being uniquely specified by an address present on the A Bus. The processor instructions that drive the CRU interface can set, reset, or test any bit in the array or move data between memory and I/O.

:=,

(A) TMS 9900 Downlloading m TMS 9940

GENERAL PURPOSE I/O - The general purpose l / O consists of 32 lines that can be independently programmed to be input ports or output ports with each port consisting of from I to 16 lines. The lines can be set, reset, tested, read, or written through the CRU interface. Direction programming is accomplished via software and can be changed in real time.

I/O EXPANSION - An 1/O expansion channel allows direct I/O expansion for up to 256 bits (lines) by use of a standard 9900 family CRU interface. Figure 2 illustrates how to implement a 16-bit input and a 16-bit output register using standard TTL components. CRU addresses can be decoded as needed to implemen(up to 16 such 32-bit interface registers. In system application,

(B) Mu|dple TMS 9940 CoM~ umtion

Fig. 3. Multiple Processor Systems Communicating through the MPSI however, only the exact number of interface bits needed to interface specific peripheral devices are implemented. It is not necessary to have a 16-bit interface register to interface an 8-bit device.

620

J.D. Bryant and R. Longley

E...........

CLK 16 BIT SHIFT REGISTER

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< 2 - +

....

.

.

.

.

.

.

.

[I ! l )

I i CRLI CLK

CmnS

CEU OUT

Fig. 4. MPSI Bh)ck I)iagram

A block diagramofthe internal MPSI logtc is nho~n in Figure 4. The protocol of the system is such that all devices are "receivers" except when actually transmitting data (the "sender" mode). The TD input signal feeds a 16hit shift register that is clocked by the TC input to allow 16 bits of data to be shifted into the shift register completely transparent to the rest of the CPU operation. After the data has been sent, the "sender" interrupts the "receiver" (through a normal interrupt input) so that the "receiver" can execute an STCR instruction (store CRU bits in memory) to input its MPSI data. To become a "'sender" the TMS 9940 executes an LDCR (load memory hits on CRU) instruction to the dedicated MPSI CR U addreses. The TD signal automatically switches to the output mode to send data, and the TC signal sends out the CRUCLK strobe. After completion of the instruction, TD and TC again revert to the input mode to switch the device back to "receiver" status.

MULTIPROCESSOR SYSTEM INTERFACE ( M P S I ) - The MPSI is a CRU-compatible two-wire

interface for transferring data in a multiple processor system. Since the TMS 9940 can execute instructions out of its RAM, the MPSI allows the capability of efficiently downloading instruction sequences which can then be executed. Thus, multiple processor systems can reconfigure themselves in system application. The MPSI can also be used to transfer data to be operated on such as, for example, in a master-slave situation with the master distributing tasks to the slaves. The MPSI is compatible with the standard 9900 family CRU interface. Figure 3A illustrates a?I'MS 9900 downloading to a TMS 9940 through the MPSI. For multiple TMS 9940 systems, the MPSI is connected as shown in Figure 3B. Additional CPU's can be connected simply by "wire ORing" to the MPSI signals.

OUT

TC

T M S 9940lNT

I

i

--

TD [~

LOOP 1

lOOP2

JEO SBZ LDC~ S80

CI

0 R12, MPSIAD R10, START LOOP 2 INT LOOP 1

!I

An example illustrating the use of the MPSI is shown in Figures 5. 6, and 7. Two TMS 9940's are connected into the MPSt configuration (Figure 5). The left TMS 9940 is assumed to be the sender and the right TMS 9940 is the receiver.

~ECE~V~R S~QUENCF

RECE+VER SOFTWARE INTERRUPT

I O(}P 1

LOOP 2

U LI JMP TB JEQ SBZ

R 12, MPSIAD R10 START LOOP2 I NT LOOP 1 OUT

STCR 16, "f{10~

OUT

16 "RIO+ OUT

TMS 9940OUT

Fig. 5. Two TMS 9940's Comnmnicaling Through the MPSI

START LIIr~ LI LI JMP TB

INT

I

s~:Nr)~ R S~aU~NCE SENDER SOFTWARE

i~

SBO

OUT

cI

R i o END

R I 0 END

NOOP NOOP 3NE LOOP I

LOOP 1

SBZ OUT RTWP

NOOP

o LI R12 MPS AQ [~ RIO,START JMP LOOP~ ~ -~L~ ~ 2 MPSlAO LOOP2 LDCR16 "Rt0" _ _ t N I ' E F d RUPI~-[I R10, START ~BO OUT ~ - - . jMp [ O O P 2 LOOP 2 $ T C R 16, "RIO* JEQ LOOP I ~ _ $80 E)t) T LOOP 1 r a InT JEO LOOP I 4 SBZ OUT )~ [f'30 ~s ~jE() LOOP ; q [QOP2 LDCR16 "RIO+ LOOP 1 TB SNI £BO O U t - JEO LOOP 1 SBZ Or ~ ~2 , , LOOP2 STCH 16 *RIO* - SBO OUT ~IIIM

/

J

NOOP

JNE SBZ

OUt

Fig. 6. Soft,ware Routines for MPS! Sender and Receiver

Fig. 7. MPSi Sender and Receiver Software Transfer Sequences

TMS 9940 - Single Chip Microcomputer

The software required for each TMS 9940 is shown in Figure 6 and the software sequence during a transfer is shown in Figure 7. The sender starts the transfer by loading the first.word (16 bits) to the MPSI and issuing an output command to interrupt the receiver. The receiver inputs the MPSI data, acknowledges receipt to the sender, checks to see if the transfer is complete, and if not, enters a wait loop to wait for the next word to be sent. Once receipt has been acknowledged, the sender sends the next word, checks for its completion of transfer, and enters a wait loop to wait for the next acknowledgement. When the transfer is finally complete the receiver executes an RTWP to return it to its original program. The transfer rate consists of the sum of the sender and receiver sequences and is 31.2 microseconds per byte as shown in Figure 7.

DECREMENTER (TIMER/EVENT COUNTER) The TMS 9940 contains a 14-bit decrementing register which can function as a programmable interval timer, an event timer, or an external event counter. A block diagram of the decrementer is shown in Figure 8. When programmed as a timer, the decrementer can function as an interval timer simply by using the proper start value. The decrementer will then issue interrupts at the chosen interval. The decrementer can also function as an event timer when in the timer mode by reading the timer values at the start and stop points of the event of interest and comparing the two values. The difference will be a direct measurement of the elapsed time. When programmed as an event counter, the decrementer functions as above except that the EC pin is the clock input instead of the system clock. A positive edge transition on EC will decrement the count. When the count reaches zero, the decrementer is reloaded with the programmed start value and an interrupt is issued. EC can also function as a positive edge triggered interrupt by loading a start value of 1.

FLAG REGISTER The TMS 9940 incorporates a 16-bit flag register internally. Each of the bits is under program control and can be set, reset, and tested.

POWER DOWN Applications which have low duty cycles (e.g., those which are human interactive) a n d / o r require low power dissipation, can make use of the power down capability to lower average power. The TMS 9940 is powered by two separate power supplies:

~

C

K

•

VCCI, which powers the RAM, decrementer and interrupt logic

•

VCC2, which powers the rest of the circuitry.

A diagram showing how to connect power to use the power down feature is shown in Figure 9. When the IDLE instruction is executed, a low value will be output on IDLE to open the power supply switch. Inputting an interrupt into the CPU will force the processor out of IDLE and drive IDLE high, which will close the switch and power up the rest of the circuitry. The HOLD input is a Schmitt trigger input which will keep the CPU stopped until VCC2 has settled. The particular chosen values of R and C are system dependent. Use of this capability can allow average power to be reduced dramatically with little additional overhead.

INSTRUCTION SET The TMS 9940 instruction set is a subset of the TMS 9900 family instruction set and contains 68 instructions. The use of the 16-bit operation code field allows individual i n s t r u c t i o n s to i m p l e m e n t p o w e r f u l operations, such as multiply and divide, with data being specified by multiple add ressing modes. The 16-bit architecture allows the use of unrestricted indexed and indirect addressing while the 8-bit orientation ensures

w

T/C

621

CLOCK

REGISTER

~ l DECREMENTER

t_ j-

]

CRUOUT

-- DECREMENTER

r INTERRUPT

EC

READREGISTER TMS 9 9 4 0

Fig. 8. Decrementer Block Diagram

1

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-~ CRUIN

622

J.D. Bryant and R. Longley

POWER SUPPLY SWITCH

I I I • t__/----!

The instruction set includes 12 conditional jumps which make use of the 6 conditional status register bits. The status register bits include:

VCC 1

A

•

ST0:

LOGICAL GREATER THAN

•

S'II:

A R I T H M E T I C G R E A T E R I-HAN

•

ST2:

EQUAl.

•

ST3:

CARRY

•

ST4:

OVERFLOW

•

ST5:

PARITY

I ~

i

IDLE VCC 2

HLD

T Fig. 9. Power Down Mode for Low Standby Power program efficiency. Included in the instruction set are instructions that perform: •

Arithmetic operations on word, byte, and immediate data

•

Multiply

•

Divide

A s u m m a r y of the instructions included in the T M S 9940 instruction set is shown in Table I, and typical instruction execution times are shown in Table 2, TABLE r TMS 9941) INSTRUCTION SET SUMMARY ARITHMETIC (18) ADD (W. B, IMM). SUB (W. B), COMPARE (W, B, IMM), INCR (1, 2t DECR (I, 2), ABS. NEO, MPY, DIV, DCA. DCS PROGRAM CONTROL (t9) BRANCH (LINK. LOAD WP). JUMP, JUMP CONDITIONAL (12). RETURN. EXECUTE. EXTENDED OPERATION

•

Decimal add and subtract

•

Branches and conditional j u m p s

i

Logical operations

LOGICAL (6) AND L OR I. INV, COC, CZC, XOR

•

Multi-bit (I to 16) shifts

SHIFTS (4) SRA, SRL SRC. SLA

DATA CONTROL (15) MOVE (W. B) LOAD (IMM. WP. ST). STORE (ST. WPk SWAP BYTES. CLR. SETO. SOC (W. B) SZC (W. B)

The instructions contain a variety of available addressing modes for addressing r a n d o m - m e m o r y data (e.g., program parameters and flags), or formatted m e m o r y data (character string, .data list, etc.). The allowed addressing modes are: •

Workspace Register Direct

•

Workspace Register Indirect

•

Workspace Increment

Register Indirect

•

Symbolic (Direct)

•

Indexed

•

Immediate

•

Program Counter Relative

with

Auto

I O (5) LDCR, STCR, TB, SBO, SBZ POWER DOWN ~1) IDLE TABLE 2

TMS 994OTYPICAL INSTRUCTION EXECUTION TIMES

•

BRANCH

2s ~

•

CONDITIONAL JUMP

2 ~i ~

•

ADD WORD REG TO REG INDIRECT TO INDEXED

, I, ~, ' ~ !~

•

ADD BYTE REG TO REG

2 4 ~,

•

MULTIPLY

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•

DIVIDE

4', 2 ~,

•

LOAD CRU (REG TO CRU) 8 BITS 16 BITS

~ ~' ~,~ i~',4 ~,

STORE CRU iCRU TO REG) 8 BITS [6 BITS

!r 2 ~ I~ (I ~,.

SET CRU BIT TO ONE ZERO

?~ .,~

•

•

TMS 9940 - Single Chip Microcomputer

TABLE

3,

BENCHMARK COMPARISONS

MEMORY BYTES I8 BIT)

PROGRAM STEPS

ROUTINE

EXECUTION TIME (MICROSEC)

TMS 9940

18048

M3870

TMS I000

TMS 9940

18048

M3870

TMS 1000

I) INCREMENT/COMPARE 4 DIGIT BCD COUNTER

I0

20

17

25

2()

26

25

25

2) PROCESS I/O D A T A

13

18

19

50

26

23

28

II

24

18

18

15

3) 16 DIGIT BCD AOO

623

TMS 9940

M3870

30.4

60

62

50

44.2

47.5

61

675

27

IS

163.2

177.5

478

2925

185

373

3580

20

6S

NA

21MO

4) S BIT BINARY MULTIPLY

I

14

25

44

2

17

28

44

32.4

5) INTERRUPT CONTEXT SWITCH

I

5

17

NA

2

5

17

NA

I

6) STRING SEARCH TOTAL

20

39

48

92

40

46

58

92"

380.8

815

969

107

150

---

108

132

183

--

662.6

1305

201 I

2.

One criterion often used to compare processors is relative performance on a set of benchmark routines. For a given application, a valid comparison can be made only if the benchmark is reflective of the system requirements. In order to make a general comparison, a set of six unrelated benchmarks has been chosen with the results being added (Table 3) to form comparative sums. The 4 microcomputers compared are: •

T M S 9940

•

Intel 8048

•

Mostek 3870

•

T M S I000

1.6

53

BENCHMARK COMPARISONS

3.

The results are formulated using three measures. The first measure, program steps, reflects the power of the instruction set and relates to the non-recurring software development cost. The second measure, memory bytes, is very important in restricted memory systems such as single-chip microcomputers and relates to job size handling ability. Finally, the third measure is execution speed. The six routines illustrated are:

INCREMENT A FOUR-DIGIT BCD COUNTER, COMPARE TO A LIMIT. Four BCD digits are stored in RAM as a software counter. The counter is incremented and the result is compared to a RAM resident limit.

TMS 1000

18048

855

PROCESS I/O DATA. The manipulations required of this routine are: (A)

Input byte A from Port l

(B)

Input byte B from Port 2

(C)

Compare A to B and act as follows:. (I) A = B; set flag and exit (2) A > B; output A, reset flag, and exit (3) A < B; output B, reset flag, and exit.

16-DIGIT BCD ADD. Sixteen decimal digits are in R A M for each of two numbers, A and B. The s u m A + B is computed in BCD and placed in 16digit location C.

4.

8-BIT BINARY MULTIPLY. Two 8-bit binary quantities are defined in RAM. Their product is computed and stored in 16 bits of RAM.

5.

INTERRUPT CONTEXT SWITCH. This routine reflects the overhead involved in saving a set of working registers before processing an interrupt and restoring them afterwards. Note that the TMS 1000 has no interrupt capability, thus, this routine is not applicable.

6.

STRING SEARCH. A block of 15 bytes is defined in RAM and is searched for a string of three contiguous bytes. Two partial finds occur before a match is found. When the match is found a flag is set and the string's starting address is returned.

The results of these comparisons are shown in Table 3.

624

J.D. Bryant and R. Longley

PROTOTYPE DEVELOPMENT Prototype development can be accomplished via several different methods. Since the TMS 9940 is a compatible member of the 9900 family, other family members (such as the TMS 9900 and TMS 9980) can be used for software development. The 9900 microcomputer board can be directly used for this purpose and makes a good starting point for the new design.The TMS 9940 implements 3 additional instructions (decimal correct add, decimal correct subtract, and load immediate data to interrupt mask) which are not in the TMS 9900/ TMS 9980 instruction set. These instructions are defined by op codes which correspond to the op code for XOP0 to XOP3 (internal software interrupts) of the TMS 9900' TMS 9980 (only XOP4 to XOP15 are implemented as general XOP's on the TMS 9940). Executing one of these op codes in a TMS 9900/TMS 9980 system will force a context switch to allow software emulation of the operation directly performed in the TMS 9940. In this way, the two machines will maintain inline machine code compatibility. Another alternative to prototype development makes use of the Advanced Microprocessor Prototyping Laboratory (AMPL) developed by Texas Instruments to support the 9900 family. The A M P L system provides real time emulators for all family members to allow required prototype development to proceed with minimum hardware development. In addition, A M P L provides trace/analyzer functions to give the system developer the capability of real-time monitoring and debug. Pertinent data and control signals may be sampled and saved in a host R A M until the occurrence of a user specified event, and the target CPU can be single stepped through its program so that internal registers and target memory can be examined and altered. Thus, A M P L can be effectively utilized to accelerate prototype development and debug. As the prototype progresses into hardware, the microcomputer b o a r d / A M P L CPU eventually can be replaced by the TMS 9940E for preproduction checkout. Finally the decision to start production with the TMS 9940E or convert to the TMS 9940N must be based upon system volume and design stability criteria.

APPLICATION EXAMPLES D A T A TERMINAL One area where microprocessors have proven to be very cost effective is in the design of data terminals, such as the Model 745 Portable Terminal, developed and manufactured by Texas Instruments. The 745 uses a

TMS 8080A to achieve its low cost and light weight while offering such features as selectable print speeds (10 and 30 CPS) using a 5x7 dot-matrix thermal printhead, built in acoustic coupler, switch-selectable half or full duplex operation, and an ASCII standard keyboard. The microcomputer portion of the 745 design requires 17 integrated circuits as shown in Figure 10. The memory consists of 2K bytes of ROM program memory (two TMS 4700's) and 64 bytes of RAM (one TMS 4036). The TMS 5501, contains a UART, programmable interval timers. interrupt control, an 8-bit input port, and an 8-bit output port. The remaining circuitry is used for I/O buffering and expansion and system overhead. The TMs 8080A controls all operations of the terminal including scanning, debouncing, and encoding the keyboard, encoding the print data into 5x7 matrix format, timing the thermal reaction of the printhead, controlling the stepping motor which positions the printhead, and even ringing the bell at the end of the line. Data is sent to the printhead over the address bus (using dummy MOV M instructions)and strobed into the printhead latch by the LOAD P R I N T H E A D signal. The schematic diagram shown in Figure 11 illustrates how the design could be implemented using a TMS 9940 microcomputer. The complete function can be emulated using only two components (one TMS 9940 microcomputer and one TMS 9902 Asynchronous Communications Controller). Twelve of the 32 I/O lines on the TMS 9940 are multiplexed as shown between the 9902 interface the keyboard scan, and printhead data output. The remaining 20 1/O lines are used to interface to the rest of the system requirements.

INTELLIGENT PERIPHERAL As the cost of microcomputers continue to decline, the low cost design of intelligent peripherals becomes more feasible. One example of this class of application is an intelligent card reader for reading the IBM standard 12 row, 80 column card. A mechanism for reading cards is shown in Figure 12a. As rollers move the card at a constant rate through the mechanism, the front edge of the card is detected by the edge detector to synchronize the reader to the card. The 12 photo detectors are then sampled at appropriate intervals to determine the 80 column code punched on the card. The TMS 9940 allows a "one chip" solution to this application as shown in Figure 12b. The O N / O F F control is an input bit, which is sampled to determine if the card reader is to be used. When an ON condition is detected, the TMS 9940 outputs a signal to turn on the roller motors and activate the LED's. When the front edge of the card passes the edge detector, an interrupt is generated to allow the

TMS

9940

-

Single Microcomputer

625

CHIP COUNT

R~O•h i m , w N

1

741m

1

741o9 74o8

1 3

74157

2

74174 74175 7432

1 1 I

7404 TOTAL

1 17

R~LDPRROM3-

IID _

.....

,

3

16 --

RI~" --

12 PRINTHEAD

¢

MOTOR CONTROL

PRINTHEAD LINEFEED 8ELL

ST,~

Fig. 10. Model 745 Data Terminal Using TMS 8080A Microprocessor

~f

PRINTHEAD LINE FEED

/

SELL

5

~

MOTORCONTROL SENSOR

I

°°1

TM$ ~ 4 0

TMS 9940 to synchronize itself to the card. The interval timer is then used to measure the appropriate time intervals for inputting the 12 rows of data as each column passes through the photo detector. As each column is read, the TMS 9940 can make the appropriate conversion from the switch specified card code to the specified format (e.g., Hollerith to ASCII). After the card has been completely read, the TMS 9940 can preprocess the data to perform such functions as:

TMS 9902

/'

•

Delete extraneous characters

•

Prescale or normalize numerical data

•

Check for special characters and issue appropriate commands

•

Verify data via use of checksum

12

/

~

PRINTHEAD DATA

CHIP COUNT TMS 11940 1 TMS 9902 I

Fig. I 1. Model 745 Data Terminal Using the TMS 9940 Microcomputer

The data can then be sent to the host processor either through the MPS1 or through an asynchronous interface.

626

J.D. Bryant and R. Longley

~

. 0 C O L . . N S - -

.

STANDARD CARD FORMAT

PHOTO IDETECTOR CONSTANT SPEED ROLLERS 12 ROW PHOTO O E T E C T O R , - , ~ .

CARD ~J~ MOVEMENT

ETECTOR

a. CARD READER MECHANISM

MOTOR C O N T R O L _ 12 ROW DETECTORS - CARE EDGe DETECT

ON/OFF CODE/FORMAT SELECT S M T C H E $ m ERROR

Fig. 12. Intelligent Peripheral Design Using the TMS 9940 Microcomputer