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Top gate pentacene thin film transistor with spin-coated dielectric
Organic Electronics 8 (2007) 615–620 www.elsevier.com/locate/orgel
Letter
Top gate pentacene thin film transistor with spin-coated dielectric Taegeun Kwon, Changhoon Baek, Hong H. Lee
*
School of Chemical and Biological Engineering, Interdisciplinary Program in Nano-Science and Technology, Seoul National University, Seoul 151-742, Republic of Korea Received 27 January 2007; received in revised form 17 March 2007; accepted 19 March 2007 Available online 28 March 2007
Abstract Fabrication of top gate pentacene thin film transistor (TFT) is made possible with spin-coatable dielectrics by the technique presented here. Such fabrication has been impractical because of the ill effects a solvent can have on pentacene. A bilayer of pentacene on insulator that are coated on a mold is transferred to a glass substrate on which source and drain electrodes are defined. In the transfer process, pentacene is automatically patterned. This fabrication method allows for the channel length to be as small as photolithography would permit. 2007 Elsevier B.V. All rights reserved. PACS: 85.30.Tv Keywords: Organic thin film transistor; Top gate; Pentacene; Spin-coated dielectric; Transfer patterning; Grain size
Pentacene thin film transistor (TFT) has come a long way since its introduction in the early 1990s [1,2]. The use of these TFTs for flat panel display [3] and integrated circuits [4] has already been demonstrated. To fabricate the TFT, pentacene has to be patterned. Typically, a shadow mask is used to define the active area. However, the resolution is limited and it is difficult to apply the method over large area. To overcome the shortcomings of the shadow mask method, lamination techniques with [5] and without [6,7] light exposure have been introduced. * Corresponding author. Tel.: +82 2 880 7403; fax: +82 2 878 5043. E-mail address: [email protected] (H.H. Lee).
Recently, a transfer patterning technique [8] has been introduced. In this technique, pentacene is deposited on a patterned ‘‘rigiflex’’ mold [9] and the pentacene on the raised part of the mold that corresponds to the desired active area is directly transferred from the mold to the gate dielectric of the TFT. While the method is simple, the surface on which pentacene is deposited is limited to that of the mold material and thus the freedom to choose a surface for larger pentacene grain size is lost. To remove the restriction, a gate dielectric of choice needs to be coated on the mold and then pentacene is deposited on the coated dielectric. When this bilayer of pentacene on dielectric is transfer-patterned, the usual bottom gate TFT cannot be fabricated since then the transferred bilayer will have
1566-1199/$ - see front matter 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.orgel.2007.03.008
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dielectric on pentacene. Therefore, a top gate TFT results. While we were initially motivated to have the freedom to choose any dielectric for larger grain size, we were also inspired by the prospect that a top gate pentacene TFT can be fabricated with solution-based dielectrics such as polymer dielectrics that can be dip- or spin-coated. Low cost manufacturing is the main driving force for solution-processing. Consequently, polymer dielectrics and sol-derived dielectrics [10] are sought after to replace vapor-deposited gate dielectrics. This push for solution-based gate dielectric is inherently incompatible with top gate pentacene transistor because a solution that is coated on pentacene can lead to damaging the underlying pentacene. It is, therefore, not surprising that there are only a handful of articles [11–13] on top gate pentacene TFT. The performance of the device, however, is poor because of the deleterious effects a solvent can have on pentacene. In this letter, we present a method of fabricating top gate pentacene TFT with solution-based gate dielectric. Pentacene can be deposited on any dielectric of choice such that the grain size can be manipulated. The active area of pentacene is defined automatically when a bilayer of pentacene on dielectric is transferred to a substrate. The procedure involved in fabricating top gate pentacene TFT is schematically illustrated in Fig. 1. A rigiflex mold, which is poly(urethaneacrylate) (PUA) [14] in this case, is prepared in which the raised part of the mold corresponds to the active area. The UV-curable, PUA mold material is obtained from Minuta Tech in Korea and used as received. The PUA mold material consists of a functionalized prepolymer with acrylate group, a photoinitiator, and a radiation-curable releasing agent for the surface activity. The liquid mixture was dropdispensed onto a master pattern. A flexible and transparent polyethyleneterephthalate (PET) film was brought into contact with the liquid mixture. Subsequently, it was exposed to UV (k = 250–400 nm) for a few tens of seconds through the transparent backplane (dose = 100 mJ/cm2). After the UV curing, the mold was peeled away from the master mold. The backplane film for the hard mold is a 188-lm-thick adhesive PET film (PET primed with polyurethane, SKC Co., Korea) that allows a degree of flexibility. The cured mold can be used repeatedly for the patterning without any deformation problem of the mold if there is no con-
Fig. 1. Schematic illustration of the procedure for fabricating top gate pentacene TFT. To prepare a mold for the transfer to follow, FEP is vapor-deposited on the patterned mold, followed by spin coating of polymer dielectric, and then by vapor-deposition of pentacene. This prepared mold is brought into contact with the substrate on which source and drain electrodes are patterned. Slight pressing and heating are applied for the transfer, after which the mold is removed. The gate is then defined by vapor deposition with a shadow mask, completing the fabrication.
tamination from the experimental environment. Onto the mold, fluorinatedethylenepropylene (FEP) is thermally deposited to a thickness of ˚ /s at room tem30 nm at a deposition rate of <1 A perature to form an interface with a low work of adhesion. To overcome the problem of wetting the low energy surface, enough solution drops are dispensed on the substrate to cover the whole surface prior to spin-coating. The dielectric of 10 wt.% poly(methylmethacrylate) (PMMA) (MW 16,000) in toluene is then spin-coated on the FEP deposited surface at 3000 rpm for 30 s, followed by deposition of pentacene by thermal evaporation to a thickness
T. Kwon et al. / Organic Electronics 8 (2007) 615–620
˚ /s at room of 100 nm at a deposition rate of <0.5 A temperature. The spin-coating conditions are such that the dielectric layer is 1 lm thick. A cleaned glass substrate is also prepared on which the gold source and drain electrodes are patterned by thermal evaporation with a shadow mask. The channel width and length are 3000 and 120 lm, respectively. The mold with the coated layers is brought into contact with the glass substrate. Manual alignment was used to ensure that the raised part of the mold is aligned with the gold electrodes. A pressure less than 1 MPa is applied at 80 C for several minutes to transfer the bilayer of pentacene on dielectric to the glass substrate. The bilayer of pentacene and PMMA on the protruding part of the mold is transferred to the substrate where the gold source and drain electrodes are patterned. The mold is then simply removed, resulting in the transfer. The height of the raised part of the mold is much larger than the thickness of spin-coated PMMA. As a consequence, the PMMA coated on the edges of the side walls is very thin, facilitating relatively easy tearing at the edges when the transfer is made. Because the work of adhesion at the FEP-dielectric interface is the lowest, clean separation takes place at the interface. The work of adhesion at an interface can be calculated based on contact angle measurements
617
with two probe liquids [15,16]. The aluminum gate is then defined by thermal evaporation through a shadow mask, completing the fabrication of top gate pentacene TFT. All the metal and organic semiconductor films in both devices were deposited by thermal evaporation at room temperature under a vacuum of 106 Torr. The transfer patterning results of the pentacene/ PMMA bilayer are shown in Fig. 2. A tilted micrograph by scanning electron microscopy (SEM) in Fig. 2a shows the pentacene/PMMA bilayer that was transferred across the channel formed by the source and drain electrodes on a glass substrate. To clearly show that the bilayer bridges the electrodes rather than follows the contour of the electrodes, a bit of space was allowed between the edge of the electrodes and that of the bilayer, the dark horizontal line being the edge of the bilayer (1000 nm thick PMMA + 100 nm thick pentacene). As a result, the lower part of the channel is bare and the upper part in the figure is covered with the bilyer, the darkish slanted vertical strip being the channel. Simple bilayer transfer pattering is demonstrated in Fig. 2b–d. Shown in Fig. 2b is an optical image of the master pattern of 4 lm size square holes made on silicon wafer. A PUA mold was prepared from the master and the mold was
Fig. 2. Results of transfer patterning of bilayer of pentacene on insulator: (a) SEM image of the bilayer that was transferred across the channel between source and drain, (b) optical image of Si master with an array of 4 lm boxes, (c) SEM image of the bilayer transferred using the master in (b) and (d) enlarged image of (c).
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coated with PMMA followed by pentacene. Fig. 2c shows the boxes of the bilayer formed on a glass substrate by the transfer from the mold to the substrate and Fig. 2d is an enlarged image of Fig. 2c. It should be noted here that an advantage of top gate TFT over bottom gate TFT is that the channel length can be defined as small as photolithography allows. In the top gate structure, the source and drain electrodes are made on glass substrate and therefore the conventional photolithography can be used for the patterning. A definitive comparison between top and bottom gate transistors has not been made in the literature. To compare the electrical performance, a reference device was also fabricated by the conventional shadow mask method. Since pentacene would be damaged in the process of coating PMMA solution on pentacene for the top gate TFT, the bottom gate structure was used instead for the reference. The materials and deposition conditions were the same
as for the top gate TFT except that pentacene is patterned using the shadow mask method for the reference device. The current–voltage characteristics of both the top gate device fabricated with the transfer method (black squares) and the bottom gate reference device fabricated with the shadow mask method (gray dots) are shown in Fig. 3a. For the transfer curves, the gate voltage VG was scanned from 10 V to 100 V with a fixed source–drain voltage, VSD, at 100 V. The same transfer curves plot1=2 ted in terms of I D vs VG are shown in Fig. 3b. The output curves for various gate voltages are given in Fig. 3c for the top gate TFT fabricated with the transfer method and in Fig. 3d for the bottom-gate reference device. For the effective mobility, le, the following relationship in the saturation region was used 1 W I D ¼ le C i ðV G V T Þ2 2 L
ð1Þ
Fig. 3. Electrical characteristics of OTFTs: (a) log ID vs VG for the reference device (gray dots) fabricated by conventional thermal evaporation with shadow mask and for the device (black squares) fabricated by the transfer method. The source–drain voltage is 100 V, (b) I 1=2 D vs VG for both OTFTs for a fixed source–drain voltage of 100 V, (c) ID vs VSD for the device fabricated by the transfer method and (d) ID vs VSD for the reference device.
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Fig. 4. AFM images of pentacene morphology and grains: (a) pentacene film thermally evaporated on PMMA film, (b) thermally evaporated on PUA mold and (c) thermally evaporated on PMMA film that was coated on FEP deposited PUA mold. The scale bar in all the images is 1 lm long.
where ID is the drain current density, W and L are the channel width (3000 lm) and channel length (120 lm), respectively, and Ci is the insulator capacitance (5.3 nF/cm2), and VG and VT are the gate and threshold voltage, respectively. The mobility thus determined is 0.18 cm2/V s for the top gate TFT whereas it is 0.21 cm2/V s for the reference. For the top gate TFT, the threshold voltage and onand off-state currents are 13 V, 1.1 · 104 A, and 3.9 · 109 A, respectively, such that the on–off current ratio is 2.8 · 104 whereas those for the reference are 16 V, 1.2 · 104 A, and 7.3 · 1011 A, respectively, with the on–off ratio of 1.6 · 106. The electrical characteristics are essentially similar. However, the leakage current at the off-state is higher by more than one order of magnitude than the reference device and any difference between the two devices are mainly due to the high off-state current of the device that was fabricated with the transfer method. This high off-current is believed due to trapped air/particle at the interface or roughness caused by less than perfect wetting of the PMMA solution on the low energy surface of FEP, the exact cause of which has not yet been resolved. One of the motivations for the top gate TFT was to have the freedom to choose any dielectric or to tailor the surface so that the grain size of pentacene can be manipulated. When the direct pentacene transfer method is used, the surface on which pentacene is deposited is restricted to that of the mold, which is PUA in this case. Shown in Fig. 4 are the images of pentacene grains by atomic force microscopy (AFM). The AFM image in Fig. 4a, which is for the pentacene film deposited on PMMA by thermal evaporation, shows a larger grain size when compared with the grain size in Fig. 4b for the film
deposited on PUA film. As expected, the image in Fig. 4c for the film deposited on PMMA that was coated on FEP deposited PUA mold shows a grain structure similar to that in Fig. 4a. Because of this larger grain size, the mobility of the top-gate pentacene TFT device is higher (0.18 cm2/V s) than that of the device fabricated by the direct transfer method [5] (0.07 cm2/V s). In summary, the fabrication of top gate pentacene TFTs is now made possible with the technique introduced here even when the gate dielectric is solution-based material such as polymeric dielectrics. The top gate TFTs with spin-coatable dielectrics have been impractical to fabricate because of the deleterious effects a solvent can have on pentacene. With this advent of the capability to fabricate top gate pentacene TFTs, the source and drain electrodes can be patterned by photolithography and as such the channel length can be made as small as photolithography would allow. Unlike the direct transfer method presented earlier for pentacene patterning [5], the technique introduced here allows tailoring of dielectric surface so as to maximize the pentacene grain size in the course of patterning pentacene. This capability would open the door to routine fabrication and use of top gate pentacene TFTs, which has so far been impractical because of the solvent effects. Although pentacene and PMMA were used for the semiconductor and insulator of TFT, the same approach should be applicable to other organic semiconductors and insulators. References [1] G. Horowitz, X.-Z. Peng, D. Fichou, F. Garnier, Synthetic Metals 51 (1992) 419.
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[2] C.D. Dimitakopoulos, A.R. Brown, A. Pomp, J. Appl. Phys. 80 (1996) 2501. [3] P. Mach, S.J. Rodirguez, R. Nortrup, P. Wiltzius, J.A. Rogers, Appl. Phys. Lett. 78 (2001) 3592. [4] M. Ahles, R. Schmechel, H. Seggern, Appl. Phys. Lett. 87 (2005) 113505. [5] G.B. Blanchet, Y.-L. Loo, J.A. Rogers, F. Gao, C.R. Fincher, Appl. Phys. Lett. 82 (2003) 463. [6] D.R. Hines, S. Mezhenny, M. Breban, E.D. Williams, Appl. Phys. Lett. 86 (2005) 163101. [7] M. Ofuji, A.J. Lovinger, C. Kloc, T. Siegrist, A.J. Maliakal, H.E. Katz, Chem. Mater. 17 (2005) 5748. [8] S.Y. Park, T. Kwon, H.H. Lee, Adv. Mater. 18 (2006) 1861. [9] S.-J. Choi, P.J. Yoo, S.J. Baek, T.W. Kim, H.H. Lee, J. Am. Chem. Soc. 126 (2004) 7744.
[10] K.K. Han, S.Y. Park, M.J. Kim, H.H. Lee, Appl. Phys. Lett. 87 (2005) 253502. [11] E. Becker, R. Parashkov, G. Ginev, D. Schneider, S. Hartmann, F. Brunetti, T. Dobbertin, D. Metzdorf, T. Riedl, H.-H. Johannes, W. Kowalsky, Appl. Phys. Lett. 83 (2003) 4044. [12] T. Cui, G. Liang, Appl. Phys. Lett. 86 (2005) 064102. [13] M.J. Panzer, C.R. Newman, C.D. Frisbie, Appl. Phys. Lett. 86 (2005) 103503. [14] P.J. Yoo, S.J. Choi, J.H. Kim, D. Suh, S.J. Baek, T.W. Kim, H.H. Lee, Chem. Mater. 16 (2004) 5000. [15] Z. Wang, J. Zhang, R. Xing, J. Yuan, D. Yan, Y. Han, J. Am. Chem. Soc. 125 (2003) 15278. [16] J. Rhee, Ph.D thesis, Cathode Patterning for Organic LightEmitting Diodes, Seoul National University, 2004 (Chapter 3).
Letter
Top gate pentacene thin film transistor with spin-coated dielectric Taegeun Kwon, Changhoon Baek, Hong H. Lee
*
School of Chemical and Biological Engineering, Interdisciplinary Program in Nano-Science and Technology, Seoul National University, Seoul 151-742, Republic of Korea Received 27 January 2007; received in revised form 17 March 2007; accepted 19 March 2007 Available online 28 March 2007
Abstract Fabrication of top gate pentacene thin film transistor (TFT) is made possible with spin-coatable dielectrics by the technique presented here. Such fabrication has been impractical because of the ill effects a solvent can have on pentacene. A bilayer of pentacene on insulator that are coated on a mold is transferred to a glass substrate on which source and drain electrodes are defined. In the transfer process, pentacene is automatically patterned. This fabrication method allows for the channel length to be as small as photolithography would permit. 2007 Elsevier B.V. All rights reserved. PACS: 85.30.Tv Keywords: Organic thin film transistor; Top gate; Pentacene; Spin-coated dielectric; Transfer patterning; Grain size
Pentacene thin film transistor (TFT) has come a long way since its introduction in the early 1990s [1,2]. The use of these TFTs for flat panel display [3] and integrated circuits [4] has already been demonstrated. To fabricate the TFT, pentacene has to be patterned. Typically, a shadow mask is used to define the active area. However, the resolution is limited and it is difficult to apply the method over large area. To overcome the shortcomings of the shadow mask method, lamination techniques with [5] and without [6,7] light exposure have been introduced. * Corresponding author. Tel.: +82 2 880 7403; fax: +82 2 878 5043. E-mail address: [email protected] (H.H. Lee).
Recently, a transfer patterning technique [8] has been introduced. In this technique, pentacene is deposited on a patterned ‘‘rigiflex’’ mold [9] and the pentacene on the raised part of the mold that corresponds to the desired active area is directly transferred from the mold to the gate dielectric of the TFT. While the method is simple, the surface on which pentacene is deposited is limited to that of the mold material and thus the freedom to choose a surface for larger pentacene grain size is lost. To remove the restriction, a gate dielectric of choice needs to be coated on the mold and then pentacene is deposited on the coated dielectric. When this bilayer of pentacene on dielectric is transfer-patterned, the usual bottom gate TFT cannot be fabricated since then the transferred bilayer will have
1566-1199/$ - see front matter 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.orgel.2007.03.008
616
T. Kwon et al. / Organic Electronics 8 (2007) 615–620
dielectric on pentacene. Therefore, a top gate TFT results. While we were initially motivated to have the freedom to choose any dielectric for larger grain size, we were also inspired by the prospect that a top gate pentacene TFT can be fabricated with solution-based dielectrics such as polymer dielectrics that can be dip- or spin-coated. Low cost manufacturing is the main driving force for solution-processing. Consequently, polymer dielectrics and sol-derived dielectrics [10] are sought after to replace vapor-deposited gate dielectrics. This push for solution-based gate dielectric is inherently incompatible with top gate pentacene transistor because a solution that is coated on pentacene can lead to damaging the underlying pentacene. It is, therefore, not surprising that there are only a handful of articles [11–13] on top gate pentacene TFT. The performance of the device, however, is poor because of the deleterious effects a solvent can have on pentacene. In this letter, we present a method of fabricating top gate pentacene TFT with solution-based gate dielectric. Pentacene can be deposited on any dielectric of choice such that the grain size can be manipulated. The active area of pentacene is defined automatically when a bilayer of pentacene on dielectric is transferred to a substrate. The procedure involved in fabricating top gate pentacene TFT is schematically illustrated in Fig. 1. A rigiflex mold, which is poly(urethaneacrylate) (PUA) [14] in this case, is prepared in which the raised part of the mold corresponds to the active area. The UV-curable, PUA mold material is obtained from Minuta Tech in Korea and used as received. The PUA mold material consists of a functionalized prepolymer with acrylate group, a photoinitiator, and a radiation-curable releasing agent for the surface activity. The liquid mixture was dropdispensed onto a master pattern. A flexible and transparent polyethyleneterephthalate (PET) film was brought into contact with the liquid mixture. Subsequently, it was exposed to UV (k = 250–400 nm) for a few tens of seconds through the transparent backplane (dose = 100 mJ/cm2). After the UV curing, the mold was peeled away from the master mold. The backplane film for the hard mold is a 188-lm-thick adhesive PET film (PET primed with polyurethane, SKC Co., Korea) that allows a degree of flexibility. The cured mold can be used repeatedly for the patterning without any deformation problem of the mold if there is no con-
Fig. 1. Schematic illustration of the procedure for fabricating top gate pentacene TFT. To prepare a mold for the transfer to follow, FEP is vapor-deposited on the patterned mold, followed by spin coating of polymer dielectric, and then by vapor-deposition of pentacene. This prepared mold is brought into contact with the substrate on which source and drain electrodes are patterned. Slight pressing and heating are applied for the transfer, after which the mold is removed. The gate is then defined by vapor deposition with a shadow mask, completing the fabrication.
tamination from the experimental environment. Onto the mold, fluorinatedethylenepropylene (FEP) is thermally deposited to a thickness of ˚ /s at room tem30 nm at a deposition rate of <1 A perature to form an interface with a low work of adhesion. To overcome the problem of wetting the low energy surface, enough solution drops are dispensed on the substrate to cover the whole surface prior to spin-coating. The dielectric of 10 wt.% poly(methylmethacrylate) (PMMA) (MW 16,000) in toluene is then spin-coated on the FEP deposited surface at 3000 rpm for 30 s, followed by deposition of pentacene by thermal evaporation to a thickness
T. Kwon et al. / Organic Electronics 8 (2007) 615–620
˚ /s at room of 100 nm at a deposition rate of <0.5 A temperature. The spin-coating conditions are such that the dielectric layer is 1 lm thick. A cleaned glass substrate is also prepared on which the gold source and drain electrodes are patterned by thermal evaporation with a shadow mask. The channel width and length are 3000 and 120 lm, respectively. The mold with the coated layers is brought into contact with the glass substrate. Manual alignment was used to ensure that the raised part of the mold is aligned with the gold electrodes. A pressure less than 1 MPa is applied at 80 C for several minutes to transfer the bilayer of pentacene on dielectric to the glass substrate. The bilayer of pentacene and PMMA on the protruding part of the mold is transferred to the substrate where the gold source and drain electrodes are patterned. The mold is then simply removed, resulting in the transfer. The height of the raised part of the mold is much larger than the thickness of spin-coated PMMA. As a consequence, the PMMA coated on the edges of the side walls is very thin, facilitating relatively easy tearing at the edges when the transfer is made. Because the work of adhesion at the FEP-dielectric interface is the lowest, clean separation takes place at the interface. The work of adhesion at an interface can be calculated based on contact angle measurements
617
with two probe liquids [15,16]. The aluminum gate is then defined by thermal evaporation through a shadow mask, completing the fabrication of top gate pentacene TFT. All the metal and organic semiconductor films in both devices were deposited by thermal evaporation at room temperature under a vacuum of 106 Torr. The transfer patterning results of the pentacene/ PMMA bilayer are shown in Fig. 2. A tilted micrograph by scanning electron microscopy (SEM) in Fig. 2a shows the pentacene/PMMA bilayer that was transferred across the channel formed by the source and drain electrodes on a glass substrate. To clearly show that the bilayer bridges the electrodes rather than follows the contour of the electrodes, a bit of space was allowed between the edge of the electrodes and that of the bilayer, the dark horizontal line being the edge of the bilayer (1000 nm thick PMMA + 100 nm thick pentacene). As a result, the lower part of the channel is bare and the upper part in the figure is covered with the bilyer, the darkish slanted vertical strip being the channel. Simple bilayer transfer pattering is demonstrated in Fig. 2b–d. Shown in Fig. 2b is an optical image of the master pattern of 4 lm size square holes made on silicon wafer. A PUA mold was prepared from the master and the mold was
Fig. 2. Results of transfer patterning of bilayer of pentacene on insulator: (a) SEM image of the bilayer that was transferred across the channel between source and drain, (b) optical image of Si master with an array of 4 lm boxes, (c) SEM image of the bilayer transferred using the master in (b) and (d) enlarged image of (c).
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coated with PMMA followed by pentacene. Fig. 2c shows the boxes of the bilayer formed on a glass substrate by the transfer from the mold to the substrate and Fig. 2d is an enlarged image of Fig. 2c. It should be noted here that an advantage of top gate TFT over bottom gate TFT is that the channel length can be defined as small as photolithography allows. In the top gate structure, the source and drain electrodes are made on glass substrate and therefore the conventional photolithography can be used for the patterning. A definitive comparison between top and bottom gate transistors has not been made in the literature. To compare the electrical performance, a reference device was also fabricated by the conventional shadow mask method. Since pentacene would be damaged in the process of coating PMMA solution on pentacene for the top gate TFT, the bottom gate structure was used instead for the reference. The materials and deposition conditions were the same
as for the top gate TFT except that pentacene is patterned using the shadow mask method for the reference device. The current–voltage characteristics of both the top gate device fabricated with the transfer method (black squares) and the bottom gate reference device fabricated with the shadow mask method (gray dots) are shown in Fig. 3a. For the transfer curves, the gate voltage VG was scanned from 10 V to 100 V with a fixed source–drain voltage, VSD, at 100 V. The same transfer curves plot1=2 ted in terms of I D vs VG are shown in Fig. 3b. The output curves for various gate voltages are given in Fig. 3c for the top gate TFT fabricated with the transfer method and in Fig. 3d for the bottom-gate reference device. For the effective mobility, le, the following relationship in the saturation region was used 1 W I D ¼ le C i ðV G V T Þ2 2 L
ð1Þ
Fig. 3. Electrical characteristics of OTFTs: (a) log ID vs VG for the reference device (gray dots) fabricated by conventional thermal evaporation with shadow mask and for the device (black squares) fabricated by the transfer method. The source–drain voltage is 100 V, (b) I 1=2 D vs VG for both OTFTs for a fixed source–drain voltage of 100 V, (c) ID vs VSD for the device fabricated by the transfer method and (d) ID vs VSD for the reference device.
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Fig. 4. AFM images of pentacene morphology and grains: (a) pentacene film thermally evaporated on PMMA film, (b) thermally evaporated on PUA mold and (c) thermally evaporated on PMMA film that was coated on FEP deposited PUA mold. The scale bar in all the images is 1 lm long.
where ID is the drain current density, W and L are the channel width (3000 lm) and channel length (120 lm), respectively, and Ci is the insulator capacitance (5.3 nF/cm2), and VG and VT are the gate and threshold voltage, respectively. The mobility thus determined is 0.18 cm2/V s for the top gate TFT whereas it is 0.21 cm2/V s for the reference. For the top gate TFT, the threshold voltage and onand off-state currents are 13 V, 1.1 · 104 A, and 3.9 · 109 A, respectively, such that the on–off current ratio is 2.8 · 104 whereas those for the reference are 16 V, 1.2 · 104 A, and 7.3 · 1011 A, respectively, with the on–off ratio of 1.6 · 106. The electrical characteristics are essentially similar. However, the leakage current at the off-state is higher by more than one order of magnitude than the reference device and any difference between the two devices are mainly due to the high off-state current of the device that was fabricated with the transfer method. This high off-current is believed due to trapped air/particle at the interface or roughness caused by less than perfect wetting of the PMMA solution on the low energy surface of FEP, the exact cause of which has not yet been resolved. One of the motivations for the top gate TFT was to have the freedom to choose any dielectric or to tailor the surface so that the grain size of pentacene can be manipulated. When the direct pentacene transfer method is used, the surface on which pentacene is deposited is restricted to that of the mold, which is PUA in this case. Shown in Fig. 4 are the images of pentacene grains by atomic force microscopy (AFM). The AFM image in Fig. 4a, which is for the pentacene film deposited on PMMA by thermal evaporation, shows a larger grain size when compared with the grain size in Fig. 4b for the film
deposited on PUA film. As expected, the image in Fig. 4c for the film deposited on PMMA that was coated on FEP deposited PUA mold shows a grain structure similar to that in Fig. 4a. Because of this larger grain size, the mobility of the top-gate pentacene TFT device is higher (0.18 cm2/V s) than that of the device fabricated by the direct transfer method [5] (0.07 cm2/V s). In summary, the fabrication of top gate pentacene TFTs is now made possible with the technique introduced here even when the gate dielectric is solution-based material such as polymeric dielectrics. The top gate TFTs with spin-coatable dielectrics have been impractical to fabricate because of the deleterious effects a solvent can have on pentacene. With this advent of the capability to fabricate top gate pentacene TFTs, the source and drain electrodes can be patterned by photolithography and as such the channel length can be made as small as photolithography would allow. Unlike the direct transfer method presented earlier for pentacene patterning [5], the technique introduced here allows tailoring of dielectric surface so as to maximize the pentacene grain size in the course of patterning pentacene. This capability would open the door to routine fabrication and use of top gate pentacene TFTs, which has so far been impractical because of the solvent effects. Although pentacene and PMMA were used for the semiconductor and insulator of TFT, the same approach should be applicable to other organic semiconductors and insulators. References [1] G. Horowitz, X.-Z. Peng, D. Fichou, F. Garnier, Synthetic Metals 51 (1992) 419.
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[2] C.D. Dimitakopoulos, A.R. Brown, A. Pomp, J. Appl. Phys. 80 (1996) 2501. [3] P. Mach, S.J. Rodirguez, R. Nortrup, P. Wiltzius, J.A. Rogers, Appl. Phys. Lett. 78 (2001) 3592. [4] M. Ahles, R. Schmechel, H. Seggern, Appl. Phys. Lett. 87 (2005) 113505. [5] G.B. Blanchet, Y.-L. Loo, J.A. Rogers, F. Gao, C.R. Fincher, Appl. Phys. Lett. 82 (2003) 463. [6] D.R. Hines, S. Mezhenny, M. Breban, E.D. Williams, Appl. Phys. Lett. 86 (2005) 163101. [7] M. Ofuji, A.J. Lovinger, C. Kloc, T. Siegrist, A.J. Maliakal, H.E. Katz, Chem. Mater. 17 (2005) 5748. [8] S.Y. Park, T. Kwon, H.H. Lee, Adv. Mater. 18 (2006) 1861. [9] S.-J. Choi, P.J. Yoo, S.J. Baek, T.W. Kim, H.H. Lee, J. Am. Chem. Soc. 126 (2004) 7744.
[10] K.K. Han, S.Y. Park, M.J. Kim, H.H. Lee, Appl. Phys. Lett. 87 (2005) 253502. [11] E. Becker, R. Parashkov, G. Ginev, D. Schneider, S. Hartmann, F. Brunetti, T. Dobbertin, D. Metzdorf, T. Riedl, H.-H. Johannes, W. Kowalsky, Appl. Phys. Lett. 83 (2003) 4044. [12] T. Cui, G. Liang, Appl. Phys. Lett. 86 (2005) 064102. [13] M.J. Panzer, C.R. Newman, C.D. Frisbie, Appl. Phys. Lett. 86 (2005) 103503. [14] P.J. Yoo, S.J. Choi, J.H. Kim, D. Suh, S.J. Baek, T.W. Kim, H.H. Lee, Chem. Mater. 16 (2004) 5000. [15] Z. Wang, J. Zhang, R. Xing, J. Yuan, D. Yan, Y. Han, J. Am. Chem. Soc. 125 (2003) 15278. [16] J. Rhee, Ph.D thesis, Cathode Patterning for Organic LightEmitting Diodes, Seoul National University, 2004 (Chapter 3).