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Transient voltage overshoot in TLP testing – Real or artifact?
Microelectronics Reliability 47 (2007) 1016–1024 www.elsevier.com/locate/microrel
Transient voltage overshoot in TLP testing – Real or artifact? D. Tre´mouilles a,*, S. Thijs a, Ph. Roussel a, M.I. Natarajan a, V. Vassilev a, G. Groeseneken a,b b
a IMEC vzw, 75 Kapeldreef, Leuven B-3001, Belgium Electrical Engineering Department, Katholieke Universiteit, Leuven B-3001, Belgium
Received 30 November 2005; received in revised form 4 May 2006 Available online 17 January 2007
Abstract This paper investigates on the transient pulse response of the device under test, which is becoming a critical aspect in determining the ESD reliability of a variety of technology products. For the first time, the feasibility to calibrate or tune the artifacts arising out of system parasitic to ‘see’ the device transient response is presented in this paper with experimental data and numerical analysis. 2006 Elsevier Ltd. All rights reserved.
1. Introduction Transmission line pulse (TLP) test systems were originally intended to obtain the quasi-static high current device response under ESD-like time periods. According to the original report [1], rectangular pulses of successively higher amplitudes are applied to the device, wherein the voltage across and current through the device under test (DUT) are recorded at the top flat region of the applied pulses. Compiling these I–V point pairs, the TLP I–V curve is obtained. While TLP testing is well known and efforts are ongoing to standardize the test method, extracting the information on the transient device response from the actual TLP pulses is less explored [2]. The information present in both the TLP voltage and current pulses is significant as it can provide in-depth information on the device transient response. This, in turn, yields direct information whether the given ESD protection strategy implemented will meet the ESD design window requirements or not. If the ESD designer uses only the voltage amplitude in the TLP I–V curve, at any given current level, as the guideline, and there exists a voltage overshoot during protection device turn on, obviously the latter would lead to early failure of the node it is *
Corresponding author. Tel.: +32 16 287 584. E-mail address: [email protected] (D. Tre´mouilles).
0026-2714/$ - see front matter 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2006.11.004
protecting in a product. Analysis invariably will show that in those cases the ESD device is not destroyed. On the other hand, TLP testers will have a certain amount of parasitic inductance from probe needles, ground loops, wiring, etc., which cannot be totally removed. These inductances will definitely react to the fast rising pulses of the TLP tester and result in voltage overshoots in the pulse transition period (rising and falling edges). Most common TLP testers, using Time Domain Reflectometry (TDR) methods, do not measure the voltage and current pulses across the DUT at the DUT, instead they are measured at a certain distance from the device [2,3]. However, which part of the observed overshoots in the transient pulse are arising out of the device and which are due to the system parasitics is neither clear nor known. There is no calibration procedure proposed in the literature that could remove the artifacts caused by the system parasitics. All the above discussions lead to the following questions: (1) how accurate is the transient response of the device as captured or presented by the TLP tester, and (2) what is really appearing across the DUT and how is it different from what is observed at the oscilloscope located at a certain distance away from the DUT? It should be highlighted that in order to analyze the transient response of the device, accurate data is required in the first few nanoseconds of the TLP pulses.
D. Tre´mouilles et al. / Microelectronics Reliability 47 (2007) 1016–1024
This paper is the first attempt to investigate this simple but significant problem, as transient device response will play an important role in ESD reliability for the entire spectrum of semiconductor devices – from low voltage deep sub-micron to high voltage technologies. Section 2 presents an overview of the TLP tester architecture, followed by comparison of two parasitic extraction procedures in Section 3. Section 4 explains an efficient calculation approach to obtain the actual voltage and current at the device. Section 5 presents a few case studies where the tester parasitics are removed to reveal and study the ‘real’ transient response of the device. 2. TLP tester TLP tester with its inherent parasitics, as well as the triggering of the device itself can lead to the generation of transient voltage overshoots. It is clear that for obtaining the real and full transient device response information, the contribution from the system should be removed. However, TLP testers are designed for the signal amplitude (current and voltage) ‘domain’ and not for the ‘time domain’. Very fast TLP (vfTLP) systems are better designed with respect to time domain measurement accuracy [2]. What this means is that in a vfTLP tester, the system parasitics are either very low or well controlled whereas in a standard TLP tester this is either unknown or uncontrolled. In any measurement system, the parasitics can be removed, either through a calibration process or through a compensation process. TLP testers are, at present, only calibrated using a short, an open, a load resistor and a Zener diode, and none of these eliminates or compensates the system parasitics (e.g., inductors) which results in possible voltage overshoots. Two previous reports [4,5] also highlighted the transient device response as a major issue in understanding the device response to ESD or ESD like pulses using TLP testers. One of the pre-conditions to apply the procedures described in this paper is that the testers must be capable of recording and storing the individual voltage and current pulses, which may not be true for all TLP testers. Further, it should be pointed out that some of the commercial TLP testers implement waveform smoothing so that the end users will see ideal rectangular pulses, which is unrealistic since all testers have enough and more or less important parasitics that will always affect significantly the transient response. If pulses are recorded, the bandwidth of the voltage and current probes, as well as, that of the oscilloscope is important. A high bandwidth (>1 GHz) scope is essential to get accurate transient information, which may not be the case if the purpose is only to get the quasi-static information during pulses. 3. Tester parasitics extraction In this section, two methodologies are presented to extract the tester parasitics. Method 1 is a simple first
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Measurement plane (MP) A’
Pulse 50 Ω Measurement generator box
50 Ω
A
Device plane (DP) B’
C’
needles DUT
B
C
Fig. 1. Schematic description of the TLP tester, using a pulse generator, as a 50 X chain.
approximation wherein parasitics are extracted through the transient analysis performed on a short-circuit-load waveform. Method 2 makes use of a more sophisticated approach, wherein the parasitics are analyzed and extracted using S-parameters. The TLP tester can be modeled as a chain as shown in Fig. 1. A charged transmission line or a pulse generator is generally used to deliver the incident pulse in a 50 X cable. The pulses traverse through the cable and arrive at the measurement node (measurement box), where both the incident pulse and the reflected pulse from the DUT are measured. Three planes, AA 0 , BB 0 and CC 0 are also defined and indicated in Fig. 1. AA 0 plane corresponds to the location of the measurements performed by the current and the voltage probes. All the parasitic contributions between AA 0 and the DUT are thus included in that measurement. The contribution from the transmission lines and connectors cannot be separated from the contributions from the needle (the needle contribution is indicated as between plane BB 0 and CC 0 ). For the system studied in this paper, the physical length of the coaxial connection from the measurement plane to the needle is 167 cm. The signal needle is directly attached to the coaxial cable and a short 4 cm cable is used to connect the ground to the second needle. The goal of this work is to extract the ‘real’ device response, which corresponds to what is at the device plane CC 0 from the current and voltage measured at the AA 0 plane. 3.1. Method 1 – extraction from transient measurement on a short Figs. 2 and 3 show the electrical equivalent circuits of an ideal and a more realistic TLP tester, respectively. In both cases, the transmission lines between the pulse generator and the measurement node (voltage and current), and between the measurement node and the device under test (DUT) are modeled using simple delay lines. In Fig. 3, series inductance Ls and resistance Rs model the parasitic contributions from the elements in between the DUT and the measurement plane (needles, cables, connectors, etc.). Method 1 presented here extracts these parasitics based on a short-circuit load measurement.
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Voltage Current
rent waveforms on the time scale and using the following formulas:
to Oscilloscope
V þ ðtÞ ¼ ðV meas ðtÞ þ 50 I meas ðtÞÞ=2;
ð1Þ
V ðtÞ ¼ ðV meas ðtÞ 50 I meas ðtÞÞ=2; DUT
Transmission line from the pulser to the measurement node
Transmission line from the measurement node to DUT
Fig. 2. Simplified electrical schematic of an ideal TDR TLP tester using a pulse generator.
Voltage Current
to Oscilloscope B
A
Ls
Rs
DUT
Transmission line from the pulser to the measurement node
A'
Transmission line from the measurement node to DUT
Ls B'
Fig. 3. Electrical Schematic of a realistic TDR TLP tester using pulse generator including the system parasitics. The dashed lines indicate the measurement planes AA 0 and BB 0 .
Fig. 4 shows the typical voltage and current waveforms measured on a short. These data are measured at reference plane AA 0 , shown in Fig. 3. The incident (V+) waveform generated by the pulse generator and the reflected (V) waveforms induced by the DUT are superposed during the measurement. They can be extracted, assuming no losses in the 50 X line, after aligning the voltage and cur-
where Vmeas(t) and Imeas(t) are the measured voltage and current, respectively. V+ and V appear at the same time at the BB 0 plane due to the impedance discontinuity created by the needle and the DUT. Thus, they can be aligned in the time domain to calculate the voltage and current at BB 0 plane using the formulas: V ðtÞ ¼ V þ ðtÞ þ V ðtÞ; V þ ðtÞ V ðtÞ : IðtÞ ¼ 50
When applied to the measurement on a short, this yields the result shown in Fig. 5. The current is a nice rectangular pulse, but the voltage has an overshoot/undershoot at the rising/falling edge of the current pulse. This effect is clearly not related to the DUT as it is short-circuit load, and therefore is a TLP tester artifact. Since the voltage across the short circuit load should be zero, this data can be used to extract the values of an equivalent network representing the parasitics of the TLP tester. A simple lumped model consisting of a series resistance, Rs, and a series inductance, Ls, was chosen. While Rs represents the series losses, Ls represents the inductance contribution, both as seen at the BB 0 plane. Using the TLP calibration procedure, Rs can be extracted and found to be 1.1 X. This resistance value is extracted from the linear fitting of the TLP IV curve of the short measurement. Ls is extracted from the time dependent voltage, V(t), and current, I(t), equations, as explained below. During a short-circuit load measurement, the voltage and current pulse basically follow the simple equation: V ðtÞ ¼ Rs IðtÞ þ 2 Ls
1.2
-5 -15
-0.6
-25
Voltage (V)
0
Current (A)
5
0.6
15 5
0 -5 -15
Current (A)
0.6
15 Voltage (V)
ð3Þ
25
25
-35 1.0E-08
dIðtÞ : dt
35
1.2
35
ð2Þ
-0.6
-25 6.0E-08
1.1E-07
-1.2 1.6E-07
-35 1.0E-08
-1.2 1.6E-07
Time (s)
6.0E-08 1.1E-07 Time (s)
Fig. 4. Voltage (black) and current (gray) pulses measured on a short at reference plane AA 0 marked in Fig. 3.
Fig. 5. Extracted voltage (black) and current (gray) pulses at the device under test for a short circuit load.
D. Tre´mouilles et al. / Microelectronics Reliability 47 (2007) 1016–1024
Thus the total series inductance 2 · Ls can be estimated from the formula (wherein the series resistance has been neglected): 2 Ls ¼
V ðtÞ dIðtÞ dt
:
ð4Þ
Fig. 6 shows the extracted series inductance, wherein the current waveform is differentiated. Since dI/dt is only meaningful during the rising and falling edges, a stable region is seen only at those places, indicated with dashed ovals. Despite the smoothing algorithm used to compensate the noise generated by the differentiation operation only an average value of the inductance can be deduced. Zooming in on the stable region in the top figure, the inductance value can be estimated to be about 150 nH as shown in the bottom figure. In order to obtain a better estimation a more efficient solution was developed. Fitting the parasitic parameters by relating the I(t) and V(t) curves in integrated form works a lot better than in differentiated form due to the smoothening effect of the numerical integration: Z t 1 IðtÞ ¼ ðV ðtÞ Rs IðtÞÞ dt: ð5Þ 2 Ls 0 This approach would allow for fitting of Rs and Ls using the complete I(t) and V(t) curves. However, the presence
Fig. 6. Procedure to extract the probe needle inductance value from the original waveform. V/(dI/dt) is plotted as a function of time using extracted voltage and current shown in Fig. 4 (top) and magnified graph corresponding to the flat regions marked in the upper figure (bottom).
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of I(t)at both sides of the integral equation distorts the least squares fitting criterion too severely in the relatively flat portions of the I(t) curve, where the relative contribution of the resistive voltage drop in V(t) is considerable. A proper way to circumvent this problem is by considering the equation in the Laplace domain: LðV ðtÞ; sÞ ¼ ðRs þ 2 Ls sÞ LðIðtÞ; sÞ:
ð6Þ
In this form, the transformed V(t) and I(t) signals duly appear at each side of the equation to fit. As the Laplace transform involves integration, it preserves the smoothening effect intended. Moreover, both fit parameters appear as linear functions of the variables involved. To properly exploit the information content present in the V(t) and I(t) signals, the numerical equivalent of the Laplace transform was implemented by sampling the Laplace transform function, Z 1 Lðf ðtÞ; sÞ ¼ f ðtÞ est dt ð7Þ 0
with s values equal to the inverses of the measurement timing vector. This explains the non-equidistance of the s values in Fig. 7. Only integration up to a time where both transients have sufficiently vanished is required in practice. The small difference in the experimental and fitted Laplace transform in Fig. 7 can be attributed to an imperfect alignment of the incident and reflected waveforms. For the same curves as shown in Fig. 5, this extraction method leads to an Rs value of 1.1 X and a 2 Æ Ls value of 146 nH. While this rather simple method provides a first approximation, it is not really optimal. Actually, the model used includes all parasitics from the DUT to the measurement oscilloscope, including the needles, cables, connectors and probe contributions. Thus the extracted parameters could be an average of all parasitics of the system as seen at the oscilloscope that could not be modeled accurately by a simple lumped element approach. In order to investigate
Fig. 7. Procedure to extract the probe needle inductance and parasitic resistance values from the numerical Laplace transform of the original waveforms. Measured (gray) and fitted (black) L(V(t), s) curves are plotted.
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this possible limitation of the lumped model, a frequency domain measurement of the TLP tester was carried out. These results are presented in the next section. 3.2. Method 2 – S-parameter based extraction Pulses in a TLP tester can be modified not only by the needles but also by the losses in the 50 X cable and the various connections. Thus in order to calculate the waveforms accurately at the device, all the parasitics in between AA 0 and CC 0 planes (Fig. 1) have to be extracted. This can be achieved by performing measurements at these planes on the TLP tester using a network analyzer with an efficient extraction procedure. The system between the planes AA 0 and CC 0 can be divided in two subsystems described by their own transmission matrix. The 50 X portion (including cable and connectors) is modeled by a transmission line in which the S matrix elements are S11 = S22 = 0 and S 12 ¼ S 21 ¼ eðaþjbÞl ;
ð8Þ
where l is the total length, and b¼
2pf vp
ð9Þ
is the wave number with f the frequency and vp the phase velocity (or the wave propagation velocity) inside the cable. a is given by pffiffiffi a ¼ acond f þ adiel f ; ð10Þ where acond and adiel are the conductor and dielectric losses. Knowing l, which can easily be measured, vp, acond and adiel are extracted by fitting the measured reflection coefficient at the AA 0 plane when measuring an open circuit using the network analyzer (needles not connected to any device). In this case the theoretical reflection coefficient is given by Copen ¼ S 11 þ
S 12 S 21 ; 1 S 22
ð11Þ
where the S-parameters are the theoretical parameters from the transmission line model. Open circuit measurement and theoretical fitting of the one port S11 measurement are shown in Fig. 8, and a good fit is obtained. The transmission matrix in between planes AA 0 and BB 0 , see Fig. 1, is thus fully characterized. Indeed, the contribution from the needle not connected can be neglected and thus the BB 0 to CC 0 contribution. To complete the characterization of the system, it is now only required to characterize the transmission matrix between planes BB 0 and CC 0 , to extract the needle model parameters. A two-step approach is required to achieve this goal: (1) perform measurements using the network analyzer with a short circuit at the end of the needles, which will characterize the transmission matrix between AA 0 and CC 0 ; and (2) de-embed the needle contribution (BB 0 –CC 0 ) from the whole line and needle (AA 0 –CC 0 ) using the
Fig. 8. Measurement and simulation, with the fitted model, results of reflection coefficient at the measurement plane MP of an open circuit at the end of the needle.
AA 0 –BB 0 transmission matrix which is already characterized. This de-embedding can be done by translating the measured reflection coefficient to the BB 0 plane using the following formula: Cneedle ¼ Cmeas
1 ; S 12 S 21
ð12Þ
where S12 and S21 are the S-parameters of the line. The needle model parameters are then fitted to the extracted reflection coefficient given that Cshort ¼ S 11
S 12 S 21 ; 1 þ S 22
ð13Þ
where the S-parameters are related to the needle equivalent circuit. The needle model presented in method 1, consisting of serial inductance and resistance, has to be extended to model the measured behavior. Thus, this model consists of an inductance with a series resistance and an additional resistance in parallel as shown in Fig. 9. Real and imaginary parts of the de-embedded reflection coefficient when compared with that from the model show good agreement (Fig. 10). Actually, the series resistance Rs is tuned manually to fit the low frequency region. The series resistance extracted using the transient on a short (1.1 X) allows an almost perfect fit. The inductance and parallel resistance of the needle 2.Ls
2.Rp
Rs
Fig. 9. Needle equivalent circuit model.
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ment equipment is needed to characterize the system. However it takes into account the frequency dependence of the cable losses and gives the timing information between the measurement and the device by modeling the whole system. After determining the parasitic elements of the system, this information can be used to recalculate the ‘real’ voltage across the DUT. An approach could be to use the formula: V DUT ¼ V ðtÞ Rs IðtÞ 2 Ls
Fig. 10. Real and imaginary plot of the de-embedded reflection coefficient for needle on a short-circuit load is compared with the needle model.
model can be calculated using a non-linear fitting algorithm. The extracted total inductance value (2 Æ Ls) is 142nH, and the total parallel resistance (2 Æ Rp) is 1.45 kX. The methodology allows theoretically characterizing of any TDR-TLP-tester parasitic. However, the method is limited by the complexity of the needle model to sufficiently accurately reproduce the needle behavior. On the one hand, the fitting algorithm could run into convergence problem or converge to unrealistic parasitic element values for too complicated model. On the other hand, a correct complex model would be difficult to provide and justified, which could lead to inaccurate conclusions. Many different experimental setups would have to be characterized to estimate the maximum amount of parasitic one could compensate for. As a rule of thumb, the lower the parasitics of the system, the more accurate the compensation steps will be. A system made with RF-probes providing 50 X up to the contact pads on the wafer would be ideal but with the drawback of a fixed pitch for the needles. However, the authors would like to emphasis that such a system should also use a compensation procedure like described in this paper, in order to obtain accurate real voltage and current waveforms at the device. 4. Parasitic contribution removal procedure The two extraction procedures described in the previous section essentially produced very similar and consistent results. This confirms that the proposed model is a good physical representation of the actual measurement system. Further, the extracted values have a practical physical meaning and are not just fitting parameters. The first method using time domain measurement given by the TLP tester itself actually gives an efficient way to extract the parasitics as soon as a robust extraction methodology is used to overcome the differentiation problem. The second methodology is more precise but additional measure-
dIðtÞ dt
ð14Þ
with the voltage and current waveforms obtained by aligning the incident and reflected waveforms in time as described before. However, due to the intrinsic noise added by the differentiation operation, the quality of the results will be poor, even if any smoothing operation is performed. To overcome this problem a frequency domain approach was chosen. The system parasitics can be described by a two-port. One side is connected to the BB 0 plane (Fig. 3) and the other side to the DUT. Using fast Fourier transform (FFT), the data is converted into the frequency domain. The transmission matrix representation of the parasitics serial inductance and resistance of the needle then provides a straightforward method to get the voltage and current at the DUT knowing the incident and reflected waves, a1 and b1, at the other side (BB 0 plane in Fig. 3). These are calculated using the previously described incident and reflected voltage waveform, aligned in time, by the following formula: Vþ a1 ¼ pffiffiffiffiffi Z0
and
V b1 ¼ pffiffiffiffiffi ; Z0
ð15Þ
where Z0 = 50 X is the reference impedance of the system. At the DUT, incoming and reflected waveforms, a2 and b2, are then calculated by multiplying (a1, b1) with the transmission matrix. The higher frequencies are then filtered out and inverse FFT is applied. Finally, the actual current and voltage at the DUT are given by pffiffiffiffiffi pffiffiffiffiffi V ¼ ða2 þ b2 Þ Z 0 ; I ¼ ða2 b2 Þ= Z 0 : ð16Þ This powerful approach can be used to fully and accurately describe the TLP tester in between the measurement oscilloscope (AA 0 ) and the DUT (CC 0 ). Actually the S-parameter model obtained by the second parameter extraction procedure gives directly the transfer matrix of the whole system (cable and needle model). An important advantage of this approach is that no difficult and critical alignment of the incident and reflected pulses is needed which is directly included in the cable model. Thus it allows direct calculation of the voltage and current at the device plane since the voltage and current at the measurement plane are known. In summary, the calculation is limited to the following five steps:
D. Tre´mouilles et al. / Microelectronics Reliability 47 (2007) 1016–1024
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(1) Calculation of the incident and reflected wave from the measured and aligned voltage and current in the measurement plane (MP) (Fig. 1) using V MP þ 50 I MP pffiffiffiffiffi ; 2 Z0 V MP 50 I MP pffiffiffiffiffi ¼ ; 2 Z0
aMP ¼ bMP
ð17Þ
(2) aMP and bMP transformation to the frequency domain (FFT); (3) Multiplication by the transfer matrix of the system give aDP and bDP at the device plane (DP); (4) aDP and bDP transformation to the time domain (iFFT), and (5) Calculation of the voltage and current at the device using aDP bDP pffiffiffiffiffi ; 50 pffiffiffiffiffi ¼ ðaDP bDP Þ 50:
I DP ¼ V DP
ð18Þ
All these steps were implemented in post-measurement correction software in order to study the transient behavior of already characterized devices. 5. Transient device response: case studies Two case studies are presented, (a) a ggnMOS device processed on a 90 nm CMOS technology and (b) a 0.35 lm HV BiCMOS technology medium voltage (MV) bipolar device. 5.1. ggnMOS from 90 nm CMOS technology This case study presents the analysis on the TLP I/V pulse waveforms using the methodology described above. This device triggers at 8 V, and has a holding voltage of 5 V as determined by a standard TLP measurement. Applying this method to the aligned voltage waveform, the corrected waveform can be extracted, as shown in Fig. 11, where it is overlaid with the uncorrected waveform. It can be seen that prior to implementing the correction, a peak of 18 V appears which is due to the system overshoot. This is because, (1) the ggnMOS is known to trigger in less than 200 ps and (2) the TLP tester voltage probe bandwidth is only 500 MHz. Thus, the TLP tester voltage response is limited by the voltage probe sensitivity (2 ns) and therefore the overshoot seen is an artifact. Fig. 11 shows that after correction of the system parasitics, the voltage across the device is reduced to 5 V, which proves that the device is triggered by dV/dt triggering, which will be discussed later on.
Fig. 11. Measured and corrected voltage waveform for a 90 nm technology ggnMOS device for a 500 mA TLP current pulse.
20 V, and has a holding voltage of 10.9 V as determined by a standard TLP measurement. Applying the method described before, the corrected waveform can be extracted, as shown in Fig. 12, where it is overlaid with the uncorrected waveform. It can be seen that prior to implementing the correction, a peak of 28 V appears and this voltage overshoot is mainly due to the system overshoot. After correction of the system parasitics, the voltage across the device is reduced to only 21 V, which is approximately the same as the trigger voltage. In applying this methodology, some interesting additional observations were also made and are described in the next section. 5.3. Transient triggering behavior While analyzing the transient voltage waveforms of ggnMOS and MV bipolar devices without any correction, it
5.2. Medium voltage transistor turn-on behavior A bipolar device, implemented in a 0.35 lm HV BiCMOS technology was measured. This device triggers at
Fig. 12. Measured and corrected voltage waveform for the medium voltage bipolar device during 1.5 A TLP current pulse.
D. Tre´mouilles et al. / Microelectronics Reliability 47 (2007) 1016–1024
Fig. 13. Corrected (line) and uncorrected (dash) voltage waveforms for the ggnMOS device at different current level. Arrow indicates increasing TLP current levels: 100, 200, 300, 400 mA, respectively (up, for the uncorrected data and down, for the corrected data).
was observed that the transient voltage overshoot increases with increasing TLP stress current levels. This is shown in Fig. 13 as dashed lines (without corr.) for the ggnMOS device. However, after implementing the correction for the tester parasitics described before, an inverse behavior at the device transient voltage response is observed, as shown in Fig. 13 with a continuous line (with corr.). This decreasing maximum voltage is attributed to the transient triggering effect, the so-called dV/dt triggering of the device. As the TLP current increases, the dI/dt value also increases, leading to a lower transient triggering voltage. Thus, the ‘real’ decreasing maximum voltage across the device after it is turned-on, hidden by the voltage overshoot associated to the needles, is now clearly made visible. Conversely, the increasing over voltage seen in the uncorrected data does not represent the real behavior of the device and could lead to a wrong interpretation of the device behavior (e.g., transient over voltage due to this device leading to an unexpected failure at a circuit input). The MV bipolar device behavior for increasing TLP current pulse levels after snapback is presented in Fig. 14. As before, the uncorrected data show an increasing voltage overshoot, as high as 40 V, for increasing TLP current levels. The corrected waveforms show, however, that the maximum transient voltage is actually much lower and more or less constant, 21 V, for all the pulses irrespective of the TLP current levels. Therefore, if the designer uses the uncorrected waveform as the ESD design guideline, then it will lead to inefficient and over-design of the ESD protection. A second interesting device behavior is observed from the corrected voltage waveform shown in Fig. 14. The time-to-trigger the device appears to be a function of the current level. For the lowest current pulse (200 mA), 9 ns
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Fig. 14. Corrected (line) and uncorrected (dash) voltage waveforms for the MV bipolar device at different current level. Arrow indicates increasing TLP current levels: 200, 300, 400, 1000 mA, respectively.
at the breakdown voltage is required before the device snaps back. The time required for snapback decreases for increasing current pulse levels. This behavior is attributed to the physical operation of these devices. In this type of devices, the snapback phenomenon is associated with the displacement of the avalanche generation region from the metallurgical junction to a deeper electrical junction situated at the boundary of the low and high doped regions of the collector [6]. At low ESD stress current levels, the potential across the device is related to the metallurgical junction, which has a relative high breakdown voltage leading to a quite high voltage across the DUT. At higher ESD stress current levels, free carriers flood the low-doped collector region, and thus the electric field is modified. This leads to a dramatic decrease of the voltage across the device. Therefore, as the amplitude of the TLP current pulse increases, the snapback occurs earlier since the required carrier density is achieved earlier. 6. Conclusion Transient response of the device under test in a TLP tester is a key parameter for ESD designers. The tester, as well as the device can contribute to any observed transient overshoots. Two methods to characterize the TLP tester parasitics are presented to obtain a better understanding of the transient response of the device under test. Both lead to similar values for the parasitics extracted. A calculation procedure is proposed to calculate the actual voltage and current at the DUT taking into account the fully characterized system parasitics. The triggering behavior of two different devices is shown and explained, which demonstrates the usefulness of the procedure to extract transient information originally hidden by the TLP tester parasitics contribution.
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Acknowledgements One of the authors (D. Tre´mouilles) would like to thank the support through Marie Curie Intra-European Fellowships. This work was supported by AMI Semiconductor within the IWT project SEBASA. References [1] Maloney T, Khurana N. Transmission line pulse technique for circuit modeling and ESD phenomena. In: EOS/ESD symposium proceedings; 1985. p. 49–54.
[2] Gieser H, Haunschild M. Very fast transmission line pulsing of integrated structures and the charge device model. IEEE Trans Compon Pack Manuf Technol Part C 1998;21(4). [3] ESD Assoc. ESD DSP5.5.1-2004. Electrostatic discharge sensitivity testing transmission line pulse (TLP), component level; 2004. [4] Hyatt H, Harris J, Alanzo A, Bellew P. TLP measurements for verification of ESD protection device response. In: EOS/ESD symposium proceedings; 2000. p. 111–21. [5] Ashton R. Extraction of time dependent data from time domain reflection transmission line pulse measurements. In: ICMTS proceedings; 2005. p. 239–44. [6] Tre´mouilles D, Bertrand G, Lescouzeres L, Bafleur M, Nolhier N. Design guidelines to achieve a very high ESD robustness in a selfbiased NPN. In: EOS/ESD symposium proceedings; 2002. p. 281–8.
Transient voltage overshoot in TLP testing – Real or artifact? D. Tre´mouilles a,*, S. Thijs a, Ph. Roussel a, M.I. Natarajan a, V. Vassilev a, G. Groeseneken a,b b
a IMEC vzw, 75 Kapeldreef, Leuven B-3001, Belgium Electrical Engineering Department, Katholieke Universiteit, Leuven B-3001, Belgium
Received 30 November 2005; received in revised form 4 May 2006 Available online 17 January 2007
Abstract This paper investigates on the transient pulse response of the device under test, which is becoming a critical aspect in determining the ESD reliability of a variety of technology products. For the first time, the feasibility to calibrate or tune the artifacts arising out of system parasitic to ‘see’ the device transient response is presented in this paper with experimental data and numerical analysis. 2006 Elsevier Ltd. All rights reserved.
1. Introduction Transmission line pulse (TLP) test systems were originally intended to obtain the quasi-static high current device response under ESD-like time periods. According to the original report [1], rectangular pulses of successively higher amplitudes are applied to the device, wherein the voltage across and current through the device under test (DUT) are recorded at the top flat region of the applied pulses. Compiling these I–V point pairs, the TLP I–V curve is obtained. While TLP testing is well known and efforts are ongoing to standardize the test method, extracting the information on the transient device response from the actual TLP pulses is less explored [2]. The information present in both the TLP voltage and current pulses is significant as it can provide in-depth information on the device transient response. This, in turn, yields direct information whether the given ESD protection strategy implemented will meet the ESD design window requirements or not. If the ESD designer uses only the voltage amplitude in the TLP I–V curve, at any given current level, as the guideline, and there exists a voltage overshoot during protection device turn on, obviously the latter would lead to early failure of the node it is *
Corresponding author. Tel.: +32 16 287 584. E-mail address: [email protected] (D. Tre´mouilles).
0026-2714/$ - see front matter 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2006.11.004
protecting in a product. Analysis invariably will show that in those cases the ESD device is not destroyed. On the other hand, TLP testers will have a certain amount of parasitic inductance from probe needles, ground loops, wiring, etc., which cannot be totally removed. These inductances will definitely react to the fast rising pulses of the TLP tester and result in voltage overshoots in the pulse transition period (rising and falling edges). Most common TLP testers, using Time Domain Reflectometry (TDR) methods, do not measure the voltage and current pulses across the DUT at the DUT, instead they are measured at a certain distance from the device [2,3]. However, which part of the observed overshoots in the transient pulse are arising out of the device and which are due to the system parasitics is neither clear nor known. There is no calibration procedure proposed in the literature that could remove the artifacts caused by the system parasitics. All the above discussions lead to the following questions: (1) how accurate is the transient response of the device as captured or presented by the TLP tester, and (2) what is really appearing across the DUT and how is it different from what is observed at the oscilloscope located at a certain distance away from the DUT? It should be highlighted that in order to analyze the transient response of the device, accurate data is required in the first few nanoseconds of the TLP pulses.
D. Tre´mouilles et al. / Microelectronics Reliability 47 (2007) 1016–1024
This paper is the first attempt to investigate this simple but significant problem, as transient device response will play an important role in ESD reliability for the entire spectrum of semiconductor devices – from low voltage deep sub-micron to high voltage technologies. Section 2 presents an overview of the TLP tester architecture, followed by comparison of two parasitic extraction procedures in Section 3. Section 4 explains an efficient calculation approach to obtain the actual voltage and current at the device. Section 5 presents a few case studies where the tester parasitics are removed to reveal and study the ‘real’ transient response of the device. 2. TLP tester TLP tester with its inherent parasitics, as well as the triggering of the device itself can lead to the generation of transient voltage overshoots. It is clear that for obtaining the real and full transient device response information, the contribution from the system should be removed. However, TLP testers are designed for the signal amplitude (current and voltage) ‘domain’ and not for the ‘time domain’. Very fast TLP (vfTLP) systems are better designed with respect to time domain measurement accuracy [2]. What this means is that in a vfTLP tester, the system parasitics are either very low or well controlled whereas in a standard TLP tester this is either unknown or uncontrolled. In any measurement system, the parasitics can be removed, either through a calibration process or through a compensation process. TLP testers are, at present, only calibrated using a short, an open, a load resistor and a Zener diode, and none of these eliminates or compensates the system parasitics (e.g., inductors) which results in possible voltage overshoots. Two previous reports [4,5] also highlighted the transient device response as a major issue in understanding the device response to ESD or ESD like pulses using TLP testers. One of the pre-conditions to apply the procedures described in this paper is that the testers must be capable of recording and storing the individual voltage and current pulses, which may not be true for all TLP testers. Further, it should be pointed out that some of the commercial TLP testers implement waveform smoothing so that the end users will see ideal rectangular pulses, which is unrealistic since all testers have enough and more or less important parasitics that will always affect significantly the transient response. If pulses are recorded, the bandwidth of the voltage and current probes, as well as, that of the oscilloscope is important. A high bandwidth (>1 GHz) scope is essential to get accurate transient information, which may not be the case if the purpose is only to get the quasi-static information during pulses. 3. Tester parasitics extraction In this section, two methodologies are presented to extract the tester parasitics. Method 1 is a simple first
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Measurement plane (MP) A’
Pulse 50 Ω Measurement generator box
50 Ω
A
Device plane (DP) B’
C’
needles DUT
B
C
Fig. 1. Schematic description of the TLP tester, using a pulse generator, as a 50 X chain.
approximation wherein parasitics are extracted through the transient analysis performed on a short-circuit-load waveform. Method 2 makes use of a more sophisticated approach, wherein the parasitics are analyzed and extracted using S-parameters. The TLP tester can be modeled as a chain as shown in Fig. 1. A charged transmission line or a pulse generator is generally used to deliver the incident pulse in a 50 X cable. The pulses traverse through the cable and arrive at the measurement node (measurement box), where both the incident pulse and the reflected pulse from the DUT are measured. Three planes, AA 0 , BB 0 and CC 0 are also defined and indicated in Fig. 1. AA 0 plane corresponds to the location of the measurements performed by the current and the voltage probes. All the parasitic contributions between AA 0 and the DUT are thus included in that measurement. The contribution from the transmission lines and connectors cannot be separated from the contributions from the needle (the needle contribution is indicated as between plane BB 0 and CC 0 ). For the system studied in this paper, the physical length of the coaxial connection from the measurement plane to the needle is 167 cm. The signal needle is directly attached to the coaxial cable and a short 4 cm cable is used to connect the ground to the second needle. The goal of this work is to extract the ‘real’ device response, which corresponds to what is at the device plane CC 0 from the current and voltage measured at the AA 0 plane. 3.1. Method 1 – extraction from transient measurement on a short Figs. 2 and 3 show the electrical equivalent circuits of an ideal and a more realistic TLP tester, respectively. In both cases, the transmission lines between the pulse generator and the measurement node (voltage and current), and between the measurement node and the device under test (DUT) are modeled using simple delay lines. In Fig. 3, series inductance Ls and resistance Rs model the parasitic contributions from the elements in between the DUT and the measurement plane (needles, cables, connectors, etc.). Method 1 presented here extracts these parasitics based on a short-circuit load measurement.
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Voltage Current
rent waveforms on the time scale and using the following formulas:
to Oscilloscope
V þ ðtÞ ¼ ðV meas ðtÞ þ 50 I meas ðtÞÞ=2;
ð1Þ
V ðtÞ ¼ ðV meas ðtÞ 50 I meas ðtÞÞ=2; DUT
Transmission line from the pulser to the measurement node
Transmission line from the measurement node to DUT
Fig. 2. Simplified electrical schematic of an ideal TDR TLP tester using a pulse generator.
Voltage Current
to Oscilloscope B
A
Ls
Rs
DUT
Transmission line from the pulser to the measurement node
A'
Transmission line from the measurement node to DUT
Ls B'
Fig. 3. Electrical Schematic of a realistic TDR TLP tester using pulse generator including the system parasitics. The dashed lines indicate the measurement planes AA 0 and BB 0 .
Fig. 4 shows the typical voltage and current waveforms measured on a short. These data are measured at reference plane AA 0 , shown in Fig. 3. The incident (V+) waveform generated by the pulse generator and the reflected (V) waveforms induced by the DUT are superposed during the measurement. They can be extracted, assuming no losses in the 50 X line, after aligning the voltage and cur-
where Vmeas(t) and Imeas(t) are the measured voltage and current, respectively. V+ and V appear at the same time at the BB 0 plane due to the impedance discontinuity created by the needle and the DUT. Thus, they can be aligned in the time domain to calculate the voltage and current at BB 0 plane using the formulas: V ðtÞ ¼ V þ ðtÞ þ V ðtÞ; V þ ðtÞ V ðtÞ : IðtÞ ¼ 50
When applied to the measurement on a short, this yields the result shown in Fig. 5. The current is a nice rectangular pulse, but the voltage has an overshoot/undershoot at the rising/falling edge of the current pulse. This effect is clearly not related to the DUT as it is short-circuit load, and therefore is a TLP tester artifact. Since the voltage across the short circuit load should be zero, this data can be used to extract the values of an equivalent network representing the parasitics of the TLP tester. A simple lumped model consisting of a series resistance, Rs, and a series inductance, Ls, was chosen. While Rs represents the series losses, Ls represents the inductance contribution, both as seen at the BB 0 plane. Using the TLP calibration procedure, Rs can be extracted and found to be 1.1 X. This resistance value is extracted from the linear fitting of the TLP IV curve of the short measurement. Ls is extracted from the time dependent voltage, V(t), and current, I(t), equations, as explained below. During a short-circuit load measurement, the voltage and current pulse basically follow the simple equation: V ðtÞ ¼ Rs IðtÞ þ 2 Ls
1.2
-5 -15
-0.6
-25
Voltage (V)
0
Current (A)
5
0.6
15 5
0 -5 -15
Current (A)
0.6
15 Voltage (V)
ð3Þ
25
25
-35 1.0E-08
dIðtÞ : dt
35
1.2
35
ð2Þ
-0.6
-25 6.0E-08
1.1E-07
-1.2 1.6E-07
-35 1.0E-08
-1.2 1.6E-07
Time (s)
6.0E-08 1.1E-07 Time (s)
Fig. 4. Voltage (black) and current (gray) pulses measured on a short at reference plane AA 0 marked in Fig. 3.
Fig. 5. Extracted voltage (black) and current (gray) pulses at the device under test for a short circuit load.
D. Tre´mouilles et al. / Microelectronics Reliability 47 (2007) 1016–1024
Thus the total series inductance 2 · Ls can be estimated from the formula (wherein the series resistance has been neglected): 2 Ls ¼
V ðtÞ dIðtÞ dt
:
ð4Þ
Fig. 6 shows the extracted series inductance, wherein the current waveform is differentiated. Since dI/dt is only meaningful during the rising and falling edges, a stable region is seen only at those places, indicated with dashed ovals. Despite the smoothing algorithm used to compensate the noise generated by the differentiation operation only an average value of the inductance can be deduced. Zooming in on the stable region in the top figure, the inductance value can be estimated to be about 150 nH as shown in the bottom figure. In order to obtain a better estimation a more efficient solution was developed. Fitting the parasitic parameters by relating the I(t) and V(t) curves in integrated form works a lot better than in differentiated form due to the smoothening effect of the numerical integration: Z t 1 IðtÞ ¼ ðV ðtÞ Rs IðtÞÞ dt: ð5Þ 2 Ls 0 This approach would allow for fitting of Rs and Ls using the complete I(t) and V(t) curves. However, the presence
Fig. 6. Procedure to extract the probe needle inductance value from the original waveform. V/(dI/dt) is plotted as a function of time using extracted voltage and current shown in Fig. 4 (top) and magnified graph corresponding to the flat regions marked in the upper figure (bottom).
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of I(t)at both sides of the integral equation distorts the least squares fitting criterion too severely in the relatively flat portions of the I(t) curve, where the relative contribution of the resistive voltage drop in V(t) is considerable. A proper way to circumvent this problem is by considering the equation in the Laplace domain: LðV ðtÞ; sÞ ¼ ðRs þ 2 Ls sÞ LðIðtÞ; sÞ:
ð6Þ
In this form, the transformed V(t) and I(t) signals duly appear at each side of the equation to fit. As the Laplace transform involves integration, it preserves the smoothening effect intended. Moreover, both fit parameters appear as linear functions of the variables involved. To properly exploit the information content present in the V(t) and I(t) signals, the numerical equivalent of the Laplace transform was implemented by sampling the Laplace transform function, Z 1 Lðf ðtÞ; sÞ ¼ f ðtÞ est dt ð7Þ 0
with s values equal to the inverses of the measurement timing vector. This explains the non-equidistance of the s values in Fig. 7. Only integration up to a time where both transients have sufficiently vanished is required in practice. The small difference in the experimental and fitted Laplace transform in Fig. 7 can be attributed to an imperfect alignment of the incident and reflected waveforms. For the same curves as shown in Fig. 5, this extraction method leads to an Rs value of 1.1 X and a 2 Æ Ls value of 146 nH. While this rather simple method provides a first approximation, it is not really optimal. Actually, the model used includes all parasitics from the DUT to the measurement oscilloscope, including the needles, cables, connectors and probe contributions. Thus the extracted parameters could be an average of all parasitics of the system as seen at the oscilloscope that could not be modeled accurately by a simple lumped element approach. In order to investigate
Fig. 7. Procedure to extract the probe needle inductance and parasitic resistance values from the numerical Laplace transform of the original waveforms. Measured (gray) and fitted (black) L(V(t), s) curves are plotted.
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this possible limitation of the lumped model, a frequency domain measurement of the TLP tester was carried out. These results are presented in the next section. 3.2. Method 2 – S-parameter based extraction Pulses in a TLP tester can be modified not only by the needles but also by the losses in the 50 X cable and the various connections. Thus in order to calculate the waveforms accurately at the device, all the parasitics in between AA 0 and CC 0 planes (Fig. 1) have to be extracted. This can be achieved by performing measurements at these planes on the TLP tester using a network analyzer with an efficient extraction procedure. The system between the planes AA 0 and CC 0 can be divided in two subsystems described by their own transmission matrix. The 50 X portion (including cable and connectors) is modeled by a transmission line in which the S matrix elements are S11 = S22 = 0 and S 12 ¼ S 21 ¼ eðaþjbÞl ;
ð8Þ
where l is the total length, and b¼
2pf vp
ð9Þ
is the wave number with f the frequency and vp the phase velocity (or the wave propagation velocity) inside the cable. a is given by pffiffiffi a ¼ acond f þ adiel f ; ð10Þ where acond and adiel are the conductor and dielectric losses. Knowing l, which can easily be measured, vp, acond and adiel are extracted by fitting the measured reflection coefficient at the AA 0 plane when measuring an open circuit using the network analyzer (needles not connected to any device). In this case the theoretical reflection coefficient is given by Copen ¼ S 11 þ
S 12 S 21 ; 1 S 22
ð11Þ
where the S-parameters are the theoretical parameters from the transmission line model. Open circuit measurement and theoretical fitting of the one port S11 measurement are shown in Fig. 8, and a good fit is obtained. The transmission matrix in between planes AA 0 and BB 0 , see Fig. 1, is thus fully characterized. Indeed, the contribution from the needle not connected can be neglected and thus the BB 0 to CC 0 contribution. To complete the characterization of the system, it is now only required to characterize the transmission matrix between planes BB 0 and CC 0 , to extract the needle model parameters. A two-step approach is required to achieve this goal: (1) perform measurements using the network analyzer with a short circuit at the end of the needles, which will characterize the transmission matrix between AA 0 and CC 0 ; and (2) de-embed the needle contribution (BB 0 –CC 0 ) from the whole line and needle (AA 0 –CC 0 ) using the
Fig. 8. Measurement and simulation, with the fitted model, results of reflection coefficient at the measurement plane MP of an open circuit at the end of the needle.
AA 0 –BB 0 transmission matrix which is already characterized. This de-embedding can be done by translating the measured reflection coefficient to the BB 0 plane using the following formula: Cneedle ¼ Cmeas
1 ; S 12 S 21
ð12Þ
where S12 and S21 are the S-parameters of the line. The needle model parameters are then fitted to the extracted reflection coefficient given that Cshort ¼ S 11
S 12 S 21 ; 1 þ S 22
ð13Þ
where the S-parameters are related to the needle equivalent circuit. The needle model presented in method 1, consisting of serial inductance and resistance, has to be extended to model the measured behavior. Thus, this model consists of an inductance with a series resistance and an additional resistance in parallel as shown in Fig. 9. Real and imaginary parts of the de-embedded reflection coefficient when compared with that from the model show good agreement (Fig. 10). Actually, the series resistance Rs is tuned manually to fit the low frequency region. The series resistance extracted using the transient on a short (1.1 X) allows an almost perfect fit. The inductance and parallel resistance of the needle 2.Ls
2.Rp
Rs
Fig. 9. Needle equivalent circuit model.
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ment equipment is needed to characterize the system. However it takes into account the frequency dependence of the cable losses and gives the timing information between the measurement and the device by modeling the whole system. After determining the parasitic elements of the system, this information can be used to recalculate the ‘real’ voltage across the DUT. An approach could be to use the formula: V DUT ¼ V ðtÞ Rs IðtÞ 2 Ls
Fig. 10. Real and imaginary plot of the de-embedded reflection coefficient for needle on a short-circuit load is compared with the needle model.
model can be calculated using a non-linear fitting algorithm. The extracted total inductance value (2 Æ Ls) is 142nH, and the total parallel resistance (2 Æ Rp) is 1.45 kX. The methodology allows theoretically characterizing of any TDR-TLP-tester parasitic. However, the method is limited by the complexity of the needle model to sufficiently accurately reproduce the needle behavior. On the one hand, the fitting algorithm could run into convergence problem or converge to unrealistic parasitic element values for too complicated model. On the other hand, a correct complex model would be difficult to provide and justified, which could lead to inaccurate conclusions. Many different experimental setups would have to be characterized to estimate the maximum amount of parasitic one could compensate for. As a rule of thumb, the lower the parasitics of the system, the more accurate the compensation steps will be. A system made with RF-probes providing 50 X up to the contact pads on the wafer would be ideal but with the drawback of a fixed pitch for the needles. However, the authors would like to emphasis that such a system should also use a compensation procedure like described in this paper, in order to obtain accurate real voltage and current waveforms at the device. 4. Parasitic contribution removal procedure The two extraction procedures described in the previous section essentially produced very similar and consistent results. This confirms that the proposed model is a good physical representation of the actual measurement system. Further, the extracted values have a practical physical meaning and are not just fitting parameters. The first method using time domain measurement given by the TLP tester itself actually gives an efficient way to extract the parasitics as soon as a robust extraction methodology is used to overcome the differentiation problem. The second methodology is more precise but additional measure-
dIðtÞ dt
ð14Þ
with the voltage and current waveforms obtained by aligning the incident and reflected waveforms in time as described before. However, due to the intrinsic noise added by the differentiation operation, the quality of the results will be poor, even if any smoothing operation is performed. To overcome this problem a frequency domain approach was chosen. The system parasitics can be described by a two-port. One side is connected to the BB 0 plane (Fig. 3) and the other side to the DUT. Using fast Fourier transform (FFT), the data is converted into the frequency domain. The transmission matrix representation of the parasitics serial inductance and resistance of the needle then provides a straightforward method to get the voltage and current at the DUT knowing the incident and reflected waves, a1 and b1, at the other side (BB 0 plane in Fig. 3). These are calculated using the previously described incident and reflected voltage waveform, aligned in time, by the following formula: Vþ a1 ¼ pffiffiffiffiffi Z0
and
V b1 ¼ pffiffiffiffiffi ; Z0
ð15Þ
where Z0 = 50 X is the reference impedance of the system. At the DUT, incoming and reflected waveforms, a2 and b2, are then calculated by multiplying (a1, b1) with the transmission matrix. The higher frequencies are then filtered out and inverse FFT is applied. Finally, the actual current and voltage at the DUT are given by pffiffiffiffiffi pffiffiffiffiffi V ¼ ða2 þ b2 Þ Z 0 ; I ¼ ða2 b2 Þ= Z 0 : ð16Þ This powerful approach can be used to fully and accurately describe the TLP tester in between the measurement oscilloscope (AA 0 ) and the DUT (CC 0 ). Actually the S-parameter model obtained by the second parameter extraction procedure gives directly the transfer matrix of the whole system (cable and needle model). An important advantage of this approach is that no difficult and critical alignment of the incident and reflected pulses is needed which is directly included in the cable model. Thus it allows direct calculation of the voltage and current at the device plane since the voltage and current at the measurement plane are known. In summary, the calculation is limited to the following five steps:
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(1) Calculation of the incident and reflected wave from the measured and aligned voltage and current in the measurement plane (MP) (Fig. 1) using V MP þ 50 I MP pffiffiffiffiffi ; 2 Z0 V MP 50 I MP pffiffiffiffiffi ¼ ; 2 Z0
aMP ¼ bMP
ð17Þ
(2) aMP and bMP transformation to the frequency domain (FFT); (3) Multiplication by the transfer matrix of the system give aDP and bDP at the device plane (DP); (4) aDP and bDP transformation to the time domain (iFFT), and (5) Calculation of the voltage and current at the device using aDP bDP pffiffiffiffiffi ; 50 pffiffiffiffiffi ¼ ðaDP bDP Þ 50:
I DP ¼ V DP
ð18Þ
All these steps were implemented in post-measurement correction software in order to study the transient behavior of already characterized devices. 5. Transient device response: case studies Two case studies are presented, (a) a ggnMOS device processed on a 90 nm CMOS technology and (b) a 0.35 lm HV BiCMOS technology medium voltage (MV) bipolar device. 5.1. ggnMOS from 90 nm CMOS technology This case study presents the analysis on the TLP I/V pulse waveforms using the methodology described above. This device triggers at 8 V, and has a holding voltage of 5 V as determined by a standard TLP measurement. Applying this method to the aligned voltage waveform, the corrected waveform can be extracted, as shown in Fig. 11, where it is overlaid with the uncorrected waveform. It can be seen that prior to implementing the correction, a peak of 18 V appears which is due to the system overshoot. This is because, (1) the ggnMOS is known to trigger in less than 200 ps and (2) the TLP tester voltage probe bandwidth is only 500 MHz. Thus, the TLP tester voltage response is limited by the voltage probe sensitivity (2 ns) and therefore the overshoot seen is an artifact. Fig. 11 shows that after correction of the system parasitics, the voltage across the device is reduced to 5 V, which proves that the device is triggered by dV/dt triggering, which will be discussed later on.
Fig. 11. Measured and corrected voltage waveform for a 90 nm technology ggnMOS device for a 500 mA TLP current pulse.
20 V, and has a holding voltage of 10.9 V as determined by a standard TLP measurement. Applying the method described before, the corrected waveform can be extracted, as shown in Fig. 12, where it is overlaid with the uncorrected waveform. It can be seen that prior to implementing the correction, a peak of 28 V appears and this voltage overshoot is mainly due to the system overshoot. After correction of the system parasitics, the voltage across the device is reduced to only 21 V, which is approximately the same as the trigger voltage. In applying this methodology, some interesting additional observations were also made and are described in the next section. 5.3. Transient triggering behavior While analyzing the transient voltage waveforms of ggnMOS and MV bipolar devices without any correction, it
5.2. Medium voltage transistor turn-on behavior A bipolar device, implemented in a 0.35 lm HV BiCMOS technology was measured. This device triggers at
Fig. 12. Measured and corrected voltage waveform for the medium voltage bipolar device during 1.5 A TLP current pulse.
D. Tre´mouilles et al. / Microelectronics Reliability 47 (2007) 1016–1024
Fig. 13. Corrected (line) and uncorrected (dash) voltage waveforms for the ggnMOS device at different current level. Arrow indicates increasing TLP current levels: 100, 200, 300, 400 mA, respectively (up, for the uncorrected data and down, for the corrected data).
was observed that the transient voltage overshoot increases with increasing TLP stress current levels. This is shown in Fig. 13 as dashed lines (without corr.) for the ggnMOS device. However, after implementing the correction for the tester parasitics described before, an inverse behavior at the device transient voltage response is observed, as shown in Fig. 13 with a continuous line (with corr.). This decreasing maximum voltage is attributed to the transient triggering effect, the so-called dV/dt triggering of the device. As the TLP current increases, the dI/dt value also increases, leading to a lower transient triggering voltage. Thus, the ‘real’ decreasing maximum voltage across the device after it is turned-on, hidden by the voltage overshoot associated to the needles, is now clearly made visible. Conversely, the increasing over voltage seen in the uncorrected data does not represent the real behavior of the device and could lead to a wrong interpretation of the device behavior (e.g., transient over voltage due to this device leading to an unexpected failure at a circuit input). The MV bipolar device behavior for increasing TLP current pulse levels after snapback is presented in Fig. 14. As before, the uncorrected data show an increasing voltage overshoot, as high as 40 V, for increasing TLP current levels. The corrected waveforms show, however, that the maximum transient voltage is actually much lower and more or less constant, 21 V, for all the pulses irrespective of the TLP current levels. Therefore, if the designer uses the uncorrected waveform as the ESD design guideline, then it will lead to inefficient and over-design of the ESD protection. A second interesting device behavior is observed from the corrected voltage waveform shown in Fig. 14. The time-to-trigger the device appears to be a function of the current level. For the lowest current pulse (200 mA), 9 ns
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Fig. 14. Corrected (line) and uncorrected (dash) voltage waveforms for the MV bipolar device at different current level. Arrow indicates increasing TLP current levels: 200, 300, 400, 1000 mA, respectively.
at the breakdown voltage is required before the device snaps back. The time required for snapback decreases for increasing current pulse levels. This behavior is attributed to the physical operation of these devices. In this type of devices, the snapback phenomenon is associated with the displacement of the avalanche generation region from the metallurgical junction to a deeper electrical junction situated at the boundary of the low and high doped regions of the collector [6]. At low ESD stress current levels, the potential across the device is related to the metallurgical junction, which has a relative high breakdown voltage leading to a quite high voltage across the DUT. At higher ESD stress current levels, free carriers flood the low-doped collector region, and thus the electric field is modified. This leads to a dramatic decrease of the voltage across the device. Therefore, as the amplitude of the TLP current pulse increases, the snapback occurs earlier since the required carrier density is achieved earlier. 6. Conclusion Transient response of the device under test in a TLP tester is a key parameter for ESD designers. The tester, as well as the device can contribute to any observed transient overshoots. Two methods to characterize the TLP tester parasitics are presented to obtain a better understanding of the transient response of the device under test. Both lead to similar values for the parasitics extracted. A calculation procedure is proposed to calculate the actual voltage and current at the DUT taking into account the fully characterized system parasitics. The triggering behavior of two different devices is shown and explained, which demonstrates the usefulness of the procedure to extract transient information originally hidden by the TLP tester parasitics contribution.
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Acknowledgements One of the authors (D. Tre´mouilles) would like to thank the support through Marie Curie Intra-European Fellowships. This work was supported by AMI Semiconductor within the IWT project SEBASA. References [1] Maloney T, Khurana N. Transmission line pulse technique for circuit modeling and ESD phenomena. In: EOS/ESD symposium proceedings; 1985. p. 49–54.
[2] Gieser H, Haunschild M. Very fast transmission line pulsing of integrated structures and the charge device model. IEEE Trans Compon Pack Manuf Technol Part C 1998;21(4). [3] ESD Assoc. ESD DSP5.5.1-2004. Electrostatic discharge sensitivity testing transmission line pulse (TLP), component level; 2004. [4] Hyatt H, Harris J, Alanzo A, Bellew P. TLP measurements for verification of ESD protection device response. In: EOS/ESD symposium proceedings; 2000. p. 111–21. [5] Ashton R. Extraction of time dependent data from time domain reflection transmission line pulse measurements. In: ICMTS proceedings; 2005. p. 239–44. [6] Tre´mouilles D, Bertrand G, Lescouzeres L, Bafleur M, Nolhier N. Design guidelines to achieve a very high ESD robustness in a selfbiased NPN. In: EOS/ESD symposium proceedings; 2002. p. 281–8.