Transistor action in polysilicon insulator transistor (SIT)

Solid-State Electronit~ Vol. 29, No. 3, pp. 377-379, 1986 Printed in Great Britain.

0038-1101/86 $3.00+ .00 © 1986 PergamonPress Ltd.

NOTES TRANSISTOR

ACTION IN POLYSILICON

INSULATOR TRANSISTOR

(SIT)

( Received 28 November 1984; in revised form 15 April 1985)

1. INTRODUCTION Transistor action by means of nonequilibrium effects in MIS structures has been previously reported[I-4] employing ultrathin ( < 60 A) tunable silicon dioxide as an insulator layer. Such devices, commonly called surface insulator transistors (SITs), surface oxide transistors (SOTs), MIS tunnel transistors, etc., offer the advantages of lower-temperature processing, fewer fabrication steps and IC technology compatibility. The purpose of this note is to introduce a new version of the device with a thicker polysilicon layer (1000-2500 .A) instead of the ultrathin silicon dioxide layer. This structure with similar performance offers unprecedented simplicity and the possibility of high-speed applications [5]. Fundamental equations based upon the two active device models [6, 7] are presented and discussed in relation to our experimental results with polysilicon and those obtained by other authors with ultrathin silicon dioxide. 2. EXPERIMENTAL RESULTS Devices with a structure similar to that shown in the detail of Fig. 1 were fabricated on n-type, (100)-orientation silicon wafers with a resistivity of 4-6 o h m - c m . After wafers were subject to conventional wet-cleaning processes, a thermal oxide was grown at 1100°C for 30 rain. This thermal oxide was removed with an H F etch solution prior to the deposition of the polysilicon layer. The wafer was quickly transferred to the chemical deposition chamber and polysilicon was deposited by the pyrolitic decomposition of silane gas at 650°C using argon as the carrier gas and a deposition time of 4 rain; afterwards the semi-insulating layer was annealed in a forming gas atmosphere for 15 rain at 900°C [8]. Alumiuium was evaporated onto the wafer, after which pattern definition was carried out by usual

photolithographic techniques. Finally the silicon chips were bonded to T-O headers. Typical polysilicon layer thickness was 2000 h, measured by interferometric techniques. The areas of the devices were in the range 10-3-10 -4 cm 2 with different separations between contacts, ranging from 10 to 20/~m. Current gains of the fabricated devices for common base (hFB) and common emitter (hrE) configurations were investigated using a curve tracer. In Fig. 1, the I - V characteristics of device No. 8 in CB configuration are shown. Typical values for the current gains in the CB and CE configurations were found to be in the range 0.6 ~
Fig. 1. 377

Table 1. Experimental values of hva and hFE for different values of separation (s) between collector and emitter Separation between contacts (s) in/~m

hFB

hFE

10 15 20

0.95 0.90 0.60

20 10 1.5

Notes

378

These values for both current gains are similar to those reported by J. Schewchun et al. and J. Ruzyllo[2,3] as will be discussed. 3. DISCUSSION The surface transistor can be considered as coupling of two devices [6, 7] consisting of forward- and reversed-biased MIS diodes (Fig. 2). For the metal/polysilicon/semiconductor structure 4'A = 0 and Egi = E.. The structure can act in both polanUes as an amphfymg mechamsm[10,11]. Considering an n-type substrate and the emitter junction forward biased [Fig. 2(a)], electrons are injected from the conduction band and from the valence band of the semiconductor to the metal (the latter can be considered a hole-injection current from the metal). The hole injection is enhanced by using a metal with high work function. We denote a I the ratio of hole injection to total current at the emitter MIS junction. At the same time, the collector is reversed biased [Fig. 2(b)], which results in the formation of the depletion region beneath the collector electrode. Due to the effects established previously for the polysilicon diode [7] the collector current tends to saturate without an excess supply of minority carriers (holes). A deep depletion layer develops at the insulator-semiconductor interface of the collector contact because the polysilicon is leaky and the hole current injected from the emitter can go through. However, the level of the collector current can be increased by the supply of additional holes to the collector depletion region from the emitter MIS junction. Increasing the supply of holes by injection the hole current arriving at the polysilicon-semiconductor interface wi!l be higher than the hole current flowing across the polysilicon layer. This results in the formation of a hole inversion layer at the interface, which in turn increases the field strength and the voltage drop in the insulator. Therefore the metal Fermi level rises over the conduction band edge, resulting in the electron current ( I N c in Fig. 2 represents conventional current) from the metal to the semiconductor increasing greatly. This increase in the electron current can be much higher than the input hole current (/PC in Fig. 2); thus current amplification occurs. We denote a 2 the ratio of electron injection to the total current at the collector. Electron injection is enhanced by using a metal with low work function such as aluminium on n-type Si. In order to characterize the interaction between emitter, collector and base currents we must consider a transport factor a T, associated with the ratio of hole current from emitter that reaches the collector, and a generation current lg due to the collector space-charge generation mechanism.

The fundamental equations for the currents in this firstorder model can be written as = a l a T / E 4 1+,

Ip(,

INC = a 2 l ( .

lE = IB + Ic .

C o m b i n i n g these four equations we obtain Gla T

oqa T 1c

=

1 - - GIO~ T - - G 2

"6, LU

Ig IB + 1 - a l a T - a 2 "

According to the definition of hFB and hvE, l GT

(1)

hvB

1

hFE

<~I~T 1 "- C~2 - Gla T '

a+ "

(2)

These formulas explain our experimental results as well as those obtained by other authors[2, 3] as follows: • The h v B and hFE values obtained for the polysilicon surface transistor are similar to those reported for the SOT[2] with an oxide thickness ranging between 35 and 105 A; this means the current amplification a 1 and a 2 for polysilicon behaves in a similar way+ as for thin SiO z . However, for ultrathin SiO z ( < 30 A) Schewchun et al.[2] report h v B > 1+ This experimental evidence supports the multiplication mechanism in the polysilicon collector junction being weaker than in the ultrathin SiO 2 collector junction, according to expressions (1) and (2). • The h v E values are larger than hFB due to the effect of a I and a T, as is shown in these expressions. • A n effective way to increase the current gain of the device is to decrease the collector emitter distance which improves the transport factor a T . T h e scaling down of the device is feasible and the mask alignment simple because the electrodes of the emitter and collector are formed in one mask and therefore do not have to be aligned with respect to each other.

FN

DEPLETION

INC

FM

1

~,- = ~ _ - ~ ,'E+ i+:-G '+'

E

IN E

E

lc = Ipc + IN<',

~ ACCUMULATION

EFW

~

LAYER

....

I

-<

o)

b) Fig. 2

--

Notes • The collector gain a 2 is enhanced for n-type substrate and aluminium metallization; however, to increase the emitter gain % a high work function such as for gold is preferred. • Certain instabilities have been observed for high-current operation of the device; this can be explained on account of the increasing values of a I and et2 with current which could make the loop gain unity, according to expressions (1) and (2). 4. CONCLUSIONS Transistor action is reported by means of a metal-polysilicon-semiconductor structure with similar behaviour to the MIS tunnel transistor but offering unprecedented simplicity in processing. Fundamental equations which describe the device performance have been derived. There are several options available for improving the device characteristics, which might show the suitability for low cost, high speed and large-integration-circuit applications.

Acknowledgements--The authors would like to thank Drs. K. Tarnay and I. Z61omy from the Technical University of Budapest, Hungary, for useful discussions.

379

Central Microelectronics Laboratory J. A. Echeverria Polytechnical Institute Havana, Cuba

REFERENCE,S 1. H. Kisaki, Proc. IEEE. 61, 1053 (1973). 2. J. Schewchun and P. A. Clarke, Solid-St. Electron. 16, 213 (1973). 3. J. Ruzyllo, I E E E Electron Dev. Lett. EDL-I, 197 (1980). 4. C. L. Shich and S. Wagner, I E E E Electron Dev. Lett. EDL-4 (1983). 5. A. Adan and K. Dobos, Solid-St. Electron. 23, 17 (1980). 6. I. Z61omy, 4 th Sci. Conf. ISPJAE, Havana, Cuba (1984). 7. A. Adan and I. Z61omy, Solid-St. Electron. 23, 449 (1980). 8. F. Rodriguez, Ph.D. thesis, J.A.E. Polytech. Inst., Havana, Cuba (1979). 9. A. Sarmiento, Ph.D. thesis, Tecta. Univ. Budapest, Hungary (1983). 10. J. Martinez and J. Piqueras, to be published. 11. A. Adan, A. Sarmiento and R. Herrera, Solid-St. Electron. 23, 515 (1980).

Solid-State Electromcs Vol. 29. No. 3, pp. 3 7 9 - 3 8 0 . 1986

0 0 3 8 - 1 1 0 1 / 8 6 $3.00 + .00 z'~ 1986 Pergamon Press Ltd.

Printed in G r e a t Britain.

INDUCED-GATE

U. CASTILLO

A. SARMIEI~O A. ADAN

1 ~jr N O I S E I N M O D F E T S

IN THE LOW GHz RANGEr

(Received 20 April 1985; in revised form 29 June 1985)

INTRODUCTION In some M O D F E T s the 1 / f noise extends into the low G H z range. We discuss here how this affects the minimum noise figure of the device in that frequency range. DISCUSSION In some M O D F E T s the 1 / f noise extends into the low GHz range. In that case there is not only drain 1 / f noise but also "induced gate" 1 / f noise at those frequencies. It is then necessary to reformulate the noise approach to solid state devices so that it holds for both thermal noise and 1 / f noise. We show here how this can be done. It is common practice to represent the h.f. noise of MESFETs, M O D F E T s and PBTs by a short-circuit drain current i d and a short-circuit gate current i s [1]. Here ig and i d are partially correlated and

c

igi~ [~.~.~1/2

(1)

where Icl 2 is relatively small. In the case of thermal noise M 2 = 0.15 for long devices and even smaller for very short devices. It is now common practice [1] to introduce an equivalent noise resistance R,, by the definition m

i2= 4kToR,IYml 2 A f

(3)

where A f is a small frequency interval and Ym the complex transconductance of the device. In addition one c a n introduce an equivalent noise input conductance g',; by the definition •,,2 -. . '4K~0g,, . . . . Zg

Af.

(4)

The noise is described by an emf AV~o in the section Ax 0 in the channel at x0; between x o and x 0 + Axo; then this gives rise to currents Aig and Ai d in the gate and drain lead that are fully correlated with AVx0. We may thus write

~'g'g "d'd]

aig = C( x )(jOaCo/gdo )i j is called the correlation coefficient; it is generally complex. It is now possible to split i s into a part i~ that is fully .it that is uncorrelated with correlated with i a and a part tg i a. A simple calculation shows that ,.~.,,2__,gti.2¢-_ icl2)

(2)

where Co and gdo are the input capacitance and output conductance at zero drain bias and C(x) is a dimensionless function of x o that changes sign when going from source to drain [1]. Consequently i~'2 will be proportional to w2Co2/gdo 2, or

•,2 lg tSupported by NSF Grant.

= 4kTog,,nAf= p(JCo2/gdo2) ~

where P is a dimensionless proportionality factor.

(5)