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Translation of VHDL for logic synthesis
Translation of VHDL for logic synthesis M S Abrahams and A Rushton
Logic synthesis can be achieved from the majority of VHDL, but some constructs have to be restricted. The techniques used in the TransGATE system to synthesize VHDL are explained. These ideas will be useful for those who wish to understand the process of designing hardware from VHDL models. It should be noted that the semantic completeness of VHDL extends only to constrain simulation tools and not to synthesis. Thus, techniques for hardware implementation described here will not necessarily be the same as other synthesis tools use. The main consideration for users of synthesis tools is to develop the design using a synchronous design methodology since there is no capability as yet for asynchronous circuit synthesis. With this restriction, synthesis can be used in the design of combinational logic processes, registered logic processes or finite state machines.
Keywords: VHDL, synthesis,translation
The preface to the IEEE standard 1076-1987 Language Reference Manual 1 makes bold claims about the importance of VHDL as a design language: 'The VHSIC hardware description language (VHDL) is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis and testing of hardware design data and the maintenance, modification and procurement of hardware.' In this paper, it will be shown that synthesis from VHDL is possible, although the hardware meaning of VHDL is not defined by the IEEE language standard. VHDL is said to have semantic completeness by virtue of the language reference manual 1 defining the language so precisely that any VHDL simulator is guaranteed to give the same result as any other. This is in contrast to hardware description languages which are not completely defined, where the behaviour of the simulation model can only be determined by experimentation. TransEDALtd, Pilgrims Close, Chandlers Ford, Eastleigh, Hampshire, SO5 3ST, UK Paper received: 29 September 1992
However, VHDL is defined only with regard to the behaviour of logic simulation tools; synthesis tools are free to determine a hardware meaning for VHDL constructs. The lack of a hardware interpretation in the VHDL standard means synthesis tools can interpret VHDL as the tool developer so desires, with the consequence of different hardware implementations being possible with different synthesis tools. Synthesis from VHDL is under debate by the VHDL analysis and standards group (VASG). In this paper, the interpretation of VHDL used by TransGATE is described. TransGATE is the logic synthesis system developed by TransEDA Limited. TransGATE accepts VHDL input as a register transfer level description or a component netlist. In a register transfer level description, the user puts in VHDL constructs which imply registers and the synthesis tool maps the implied registers and logic in between to a technology cell netlist. Only a few VHDL constructs are positively disallowed, but there are restrictions on the way constructs may be used. TransGATE requires that the user designs a synchronous circuit; feedback must be through registers. The large range of VHDL constructs preclude this paper from being a complete description of the subset of VHDL which can be transformed onto TransGATE, but the translation of the more frequently used constructs in VHDL will be described. Similarly, the paper does not attempt to be a VHDL language tutorial; familiarity with the basic language constructs and their meaning in simulation is assumed, and alternative reading for a VHDL introduction can be found in References 2 and 3.
SOFTWARE ORGANIZATION VHDL is translated onto the TransGATE synthesis system using the following strategy. VHDL text is analysed using the analyser from the CLSI VHDL tool integration platform (VTIP)4. A set of transformations is applied to reduce VHDL text to a small subset of the language. The new VHDL description is translated from this small subset onto the target data structures for logic synthesis. The process of VHDL translation in TransGATE is shown in Figure 1.
0141-9331/94/08/0459-09 ~/ 1994 Butterworth-Heinemann Ltd Microprocessors and Microsystems Volume 18 Number 8 October 1994
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Translation of VHDL for logic synthesis: M S Abrahams and A Rushton
VHDLText
phase ~I synthesis is t{> ,~'xthl~I a VIII)I rwtli'q ~. l l)ll '-,~hemati( text which ~an bt, h a n d e d ,:m t~ lay~:}Lllh:,~4~,, a gate level simulator or a schematic viewu~. With tills target data structure in minrI, the next section describes how a synthesis subset <>f VHDL converts direclly onto TransGATE. After that, the earlier transformation phase will be describecl to show that a much wider subset of VHDL can be translormed into the synthesis subset.
F
I Analysis
CLSI format I
CONVERSION OF THE SYNTHESIS SUBSET
Transformations I Conversion Internal Format Figure 1 Organizationof the TransGATEVHDL translator The CLSI analyser is incorporated into TransGATE to give a seamless interface. It performs syntax checks and semantic checks to ensure that the text read conforms to the VHDL standard. At this stage, the entire language is supported by the analyser. However, a last pass through the analyser is used to perform additional checks for conformity to a synthesis subset. During the extra pass through the analyser, the CLSI data structures are transformed to convert a number of VHDL constructs into a small subset of the language. For example, the transformations perform procedure inlining and loop unrolling. Errors will be raised if structures are encountered which do not belong to the small subset for synthesis or cannot be transformed onto the synthesis subset. After analysis and transformation, the CLSI data structure representing the circuit contains structures which have a direct representation in the TransGATE synthesis view. The last phase, conversion, generates the TransGATE representation. Conversion is described in the following section. TransGATE represents the circuit as a directed graph, called a circuit graph. The arcs represent boolean signals and the nodes are either technology cell instances, boolean equations or are instances of circuit graphs from the next level down in the design hierarchy. Each graph has two special nodes, an input node representing the circuit inputs and an output node representing the circuit outputs. Since the data structure also supports cell instances and hierarchy, it is quite possible to mix high level design with hand crafting of critical modules. Tools in TransGATE perform multi-level synthesis and technology mapping. These tools read and write the circuit graph data structure. Multi-level synthesis collapses boolean equations which represent bad factors and extracts good common factors from the boolean network of the design to reduce the final circuit area. Technology mapping binds the boolean equation network to instances of gates from the selected implementation technology. The final
460
The synthesis subset is kept to a minimum on the understanding that this subset has a direct mapping onto the TransGATE (-ircuit graph data structure and hence a mapping to hardware. The transformation phase can convert a broader language subset into this smaller subset.
Design unit A design unit in VHDL consists of an entity declaration and an architecture body. An entity declaration is used in TransGATE to define the port's specification to a circuit graph, i.e. the input and output nodes. An architecture body defines the internals of the circuit graph.
Entity declaration A VHDL entity declaration is translated onto a TransGATE port specification by mapping types onto their bit maps and generating a set of names for the resulting bits. Type mapping will be described later. Only input and output ports are possible in TransGATE, which correspond to modes [N and OUT respectively. However, VHDL also supports INOUT mode. This represents a bidirectional signal which has no interpretation in TransGATE and therefore is flagged as non-compliant with the synthesis subset.
Architecture body An architecture body contains a set of processes and components. All other statements allowed in VHDL at this level are transformed into processes. Each process (:an be interpreted as a subgraph. Because processes have no interface of their own, the port specification of the subgraph is not obvious. The inputs of the subgraph are the set of signals read within the process. The outputs are the set of signals assigned to within the process. Since each statement in an architecture body is concurrent, it has a direct implementation in hardware, since clearly hardware is concurrent. Connections are made fronl the outputs of the subgraph driving a signal to all the inputs of subgraphs reading a signal. This is all that is required to wire up the graph representing an architecture body. A simple example illustrates the point. Figure 2a shows a simple entity declaration and architecture body, and Figure 2b shows the corresponding subgraphs generated for each process.
Microprocessors and Microsystems Volume 18 Number 8 October 1994
Translation of VHDL for logic synthesis: M S Abrahams and A Rushton e n t i t y e x a m p l e is p o r t (a: in natural; end example; architecture behaviour s i g n a l s : natural; begin p r o c e s s (a) begin s <= a; end process; p r o c e s s (s) begin z <= (s = 0); end process; end behaviour;
e n t i t y e x a m p l e 2 is p o r t (a, b : in r e s o l v e d _ b i t ; end example2;
z : Out b o o l e a n ) ;
of e x a m p l e
is
architecture behaviour begin p r o c e s s (a) begin z <= a; end process; p r o c e s s (b) begin z <= b; e n d process; end behaviour;
z : out
of e x a m p l e 2
resolved_bit);
is
a
a
a h~
b Figure 3 a, Multiple signal drivers; b, TransGATE interpretation or resolved multiple drivers
b Figure2 a, VHDL entity declaration and architecturebody; b, TransGATE
Process
interpretation of entity declaration and architecturebody
Resolution functions The problem with the VHDL model of concurrency in the architecture body is that it is quite legal to have a number of concurrent statements assigning to a signal (called 'drivers' in VHDL-speak). It is necessary to resolve multiple drivers. The VHDL language supports the concept of resolution functions associated with a type. If a signal of a particular type is driven more than once, the resolution function for that type is called to work out the value of the signal. This method is especially useful for modelling tristate buses (where all but one driver will be driving a 'Z' value). The use of multi-value logic types, such as the proposed IEEE standard STDULOGIC:
The general form of a process is a block of sequential statements whi~:h are executed every time a set of sensitization conditions are reached. The transformation into TransGATE format requires the interpretation of the sequential statements into a hardware representation effectively a sequential to concurrent statement transformation. The result is a graph which becomes a subgraph in the transformed architecture body. There are three basic types of process: combinational logic, registered combinational logic and finite state machine. A combinational logic block is represented by a process which is sensitive to any event on any of its inputs (the set of signals which the process reads). An example illustrating a combinational logic process is shown in Figure 4. The process must be sensitive to all of its inputs, none of which may be the clock signal.
type STD ULOGIC ('U ', 'X', '0', '1 ', 'Z', 'W', 'L', 'H', '-'); creates a large number of possible permutations and requires an analysis of the state strength system for the type being resolved. As the majority of type values represent modelling values and only two values represent true logic values, analysing the resolution function is extremely difficult. VHDL attributes are used instead to attach the resolution action to the type. Only two resolution functions have a hardware implementation and these are 'wired-and' and 'wired-or'. These are transformed into 'and' and 'or' functions respectively. An example of an architecture body requiring the use of a 'wired-and' resolution function is shown in Figure 3.
process (a, b, begin z <= (a a n d end process;
c) b)
or
c;
a
a
Z
Hierarchy A component instantiation represents a level of hierarchy in the design. This has a direct correspondence with the hierarchy in TransGATE.
b Figure 4 a, Combinational process; b, TransGATE interpretation of combinational process
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Translation of VHDL for logic synthesis: M S Abrahams and A Rushton process (elk, cst) begin if ('0' ;~ rst) then z <- '0': elsif ('0' = clk and clk'event) y <- a; z <= y; end if; end process;
then
a
F
Clka
z
rst
?
b Figure 5
a, Registered process; b, TransGATE interpretation of registered
pr(x ess Clock signals are excluded from the combinational logic process because they are inconsistent with the synchronous design methodology supported by logic synthesis; other tools in the TransGATE system cannot properly support clocks which are gated with data signals. This definition therefore requires TransGATE to know which signal is the clock signal in a VHDL description. Signal assignments in a combinational logic process are implemented as simple connections. A registered logic block is represented by a process which is sensitive to a clock edge and possibly a reset signal. Each registered process must be sensitive to one clock edge. The clock signal must only be used to control the process; it must not be used as part of any expression or
e n t i t y jk is p o r t (elk : in bit; q : out bit); e n d jk;
rst
: in bit;
j : in bit;
k
architecture s t a t e m a c h i n e of jk is t y p e s t a t e _ t y p e - - i s (stateO, s t a t e l ) ; signal state, next state : state_type := s t a t e O ; attribute state_signal of s t a t e : s i g n a l is ""; begin process (clk, rst) begin if (rst = '0') t h e n s t a t e <= s t a t e O ; elsif (clk'event and clk = s t a t e <= n e x t s t a t e ; e n d if; end prooess;
'i')
process (state, j, k) begin n e x t s t a t e <= s t a t e ; c a s e s t a t e is w h e n s t a t e O => q <= '0'; if j = 'i' t h e n n e x t s t a t e <= s t a t e l ; e n d if; w h e n s t a t e l => q <= 'I'; if k = 'i' t h e n n e x t s t a t e <= s t a t e O ; e n d if; e n d case; end process;
end
state
Figure 6
462
machine;
State machine for a J-K flip-flop
: in bit;
assignment. An example illustrating a registered Iogi( block (specifically a C-R [)lock) is shown in Figure' 7. Nole that all signals are defined at the archite(ture lew~l and lherefore must be exported from the process. Each signal assignment in the process is registered. Thus it is possible to represent a pipeline as a single process, as the example shows. This is the main difference between combinational and registered processes. A finite state machine is a special type of registered block. State machines need to be described by two processes: a registered process to store the state variable and a combinational pro(ess to describe state transitions and output decoding. The split into two processes is required to avoid registering the state machine output signal. If required, it is quite simple to register the output by adding a third process. State machine recognition requires that the state signal has an attribute so that two processes using signals of the state type can be linked together as one state machine during translation. Figure 6 shows an example of a simple state machine.
Feedback Feedback occurs when a process: • • • •
reads a variable before writing to it, assigns a variable in some but not all arms of an if or case statement, has a signal which is both an input and an output to a process, and assigns a signal in some but not all arms of an if or case statement.
In logic synthesis, asynchronous feedback is not allowed; only a purely synchronous design philosophy is supported. Thus it follows that feedback is only allowed in registered logic blocks. Of course, feedback is implicit in a state machine, but C-R blocks may also have registered feedback. Figure 7 illustrates the form of a registered process with feedback. The variable 'state' is read in the process before it is assigned a value..This example also illustrates that signal assignments are registered, in this case 'z' is registered.
then
Sequential statements Inside every process in an architecture body is a series of sequential statements. Each sequential statement maps onto a piece of hardware which in turn forms part of the circuit representing the process. Mapping sequential statements into concurrent hardware requires a number of interpretations which are not self-explanatory. The rest of this section describes these interpretations. Conditional operations - If and Case - translate to multiplexers. However, the conversion is cornplicated by the fact that a particular object may only be assigned in some branches of the conditional statement, and furthermore that a signal assigned in such circumstances will retain its value between process executions. This interaction between
Microprocessors and Microsystems Volume 18 Number 8 October 1994
Translation of VHDL for logic synthesis: M S Abrahams and A Rushton Sequential signal assignments have the property that later signal assignments override earlier signal assignments. The situation is more complex in the presence of conditional statements, because the translator cannot always remove redundant signal assignments, but must feed forward their values. In the example in Figure 9, when cl and c2 are true, the second assignment takes precedence since it is later in the process. If neither cl or c2 is true, no assignment takes place and the previous values of s must be fed back to the inputs.
process v a r i a b l e s t a t e : b i t := '0'; begin w a i t on c l o c k u n t i l c l o c k = 41'; if s t a t e = 'i' t h e n z <= a; s t a t e := ~0'; else z <= b; s t a t e := ~i'; e n d if; end process;
a clock
['~ star I
1
kF
L~
IP-
Z
"I
Dynamic indexing Dynamic indexing occurs when an index expression within an indexed name is not static. Each dynamic index expression translates to a dedicated block of multiplexing logic. In the example of Figure 10, the variable z is being writ-
b Figure 7 a, Feedbackin a registeredprocess;b, TransGATEinterpretation of registeredprocesswith feedback conditional statements and signal assignments allows synchronous feedback paths to be described conveniently. Each conditional statement translates to a multiplexer, with one output for each object that appears as the target of an assignment within the conditional statement. The boolean condition translates to a block of logic which feeds into the select input of each multiplexer, and the data inputs to each multiplexer are fed from the logic for the expression being assigned. If a particular variable is not assigned within one branch of any conditional operation in the process, then the value is fed back from the output of the previous process execution. This highlights the fact that internal signals can feed back from block outputs to inputs, where the values are available if required for the next process execution. Figure 8 shows an if statement without an else clause. Since only registered processes can contain feedback, combinational processes must have completely specified conditional statements.
process begin wait on clock until clock = ~i'; if cl then s <= a; end if; if c2 then s <= b; end if; end process;
a
value
clock
c2 I i c, l l all S
b
Jk~
.T] b
Figure 9 a, VHDL implying the feed forward of a previous value; b, TransGATEinterpretationfeedingforward a previousvalue a(index)
:= z;
a
process begin w a i t on c l o c k u n t i l c l o c k = 'i'; if e n a b l e t h e n f <= a and b; e n d if; end process;
index
/
I
I
a
clock ~ a[O] a[1] a[2]
a[0] a[l]
a[2]
a[3]
a[3]
b
b
Figure 8 a, Incompletely specified if statement; b, feedback resulting from incomplete if statements
Figure 10 a, Assigningto an array element; b, hardwarefor assigningto an array element
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Translation of VHDL for logic synthesis: M S Abrahams and A Rushton ten onto one of the bits of the four bit array a. The remaining three bits of the array retain their old values.
Operators
type
end x
The operators 'and', 'or', 'nand', 'nor', 'xor' and 'not' map directly to the primitive boolean operators. The xnor operator is supported in anticipation of the 1992 update. Operators -t-, and * are implemented using built in architecture for an adder, subtractor and multiplier. Where x is static, the operation 2 ' is equivalent to a left shift of a single bit by x places. Similarly, the operations y * 2',y/2' are equivalent to a left shift or right shift of y by x places. The operation x mod n, where n is a static, positive power of 2, is equivalent to performing the bitwise 'and' of n with a mask having the bottom Iogz(n) bits set. Relational operators on integer and enumeration types are implemented using bitwise xor to test for equality, and by using a special comparator circuit for less than or greater than. The attribute t'pos(x) becomes the identity function. The attribute t'val(x) truncates x to the number of bits in the representation of t'base, t'succ(x) and t'pred(x) become increment and decrement functions o n the position number of x, hut truncated to the range of t'base.
Types The mapping of data types from VHDL to hardware is governed by fixed rules, such that objects of the same data type always map to the same hardware structures. This ensures consistency between components of a design. Enumeration types translate to a bundle of wires, with n wires representing up to 2" states. The position number of the enumeration value is encoded as an unsigned binary integer, which simplifies the handling of relational operators and the attributes t'pos, t'val, t'succ and t'pred. Integer types translate to a bundle of wires, using unsigned or twos complement representation, depending upon whether the lower bound of the range is negative. For example, a type such as 'range 100 to 101' will be represented as 7 bits unsigned. For subtypes of enumeration and integer types, whether introduced explicitly or anonymously, the encoding is the same as the base type, but may be able to take advantage of the restricted range by using fewer wires. Thus, although objects of any type have similar type encodings, two objects of the same type may differ in the number of wires used in their representation. Assignments may require implicit conversion between representations. Type conversions, whether explicit or implicit, may imply widening or narrowing the integer bus, and possibly adding a sign bit or performing a sign extension. However, there is no point in widening the bus except where it is combined with a wider bus in an integer operation. Narrowing a bus may cause bits to be lost through truncation. It is assumed that any range constraints present in the VHDL coding will not be violated by the design, since range checking cannot be performed. Array types translate to a 'bundle of bundles of wire'.
464
recl
:
record
a
: bit;
....
b
: nibble;
--
represented represented
by 1 bit by 4 bits
record;
:
recl ;
a x.a x.b[O] x.b[l] x.b[2] x.b[3]
b Figure 11
a, Variable definition; b, namesgenerated
Names Where possible, name information from the VHDL sour{e is preserved in the TransGATE representation. Entity names are preserved as module names. Formal port names are used to derive input and output port names. Signal and variable names are used to derive the signal name on the node driving a net. Port, signal and variable names may all represent composite objects, and the type of even a scalar object may map onto more than one wire. Names ior composite objects are constructed by concatenating using a dot notation. For a member of a record, the member name is appended to the signal name. For a member of an array, the array index is appended to the signal name. For simple types which are represented by rnore than one bit (such as integers), the bit number is added to the name as an index, not as a suffix using the dot notation. Only one level of indexing is supported by TransGATE.
TRANSFORMING VHDL ONTO THE SYNTHESIS SUBSET A design is converted automatically into the synthesis subset by the transformation phase of translation. Transformation takes place entirely within the VTIP environment; the output is a new VHDL description that is stored in VTIP. It is thus possible for the user to extract and read the transformed description if so desired. This section describes the transformation process.
Non-standard processes The synthesis subset defines the interpretation of VHDL architecture bodies and three forms of processes within them. However, these processes are not the only concurrent statements that can occur in an architecture body. This section shows how most other concurrent statements (:an be transformed into one of the standard processes. There are three forms of sensitization which can be used in a process: the sensitization list, the wait until statement and the wait on statement. Figure 12 illustrates the three forms. The difference between the three forms is that the
Microprocessors and Microsystems Volume 18 Number 8 October 1994
Translation of VHDL for logic synthesis: M S Abrahams and A Rushton process begin
(a, b, c)
process begin statements w a i t ... statements end process;
end process;
a process begin
A
...
B
...
B A
... ...
a
wait until a'event end process;
or b ' e v e n t
or c'event;
b process begin wait on a, b, e n d process;
c;
process begin w a i t ... statements statements end process;
b Figure 14 a, General ~rm of the wait statement; b, trans~rmed general ~rm of the wait statement
C Figure12 a, Sensitizationlist;b, waituntilstatement;c, waitonstatement sensitization list method and the wait on statement can only handle events on a signal, whilst the wait until condition can impose additional tests. However, all of these examples are exactly equivalent. The wait until form (b) is the target form used in the synthesis subset; the other forms should be transformed into this form. Another good example is the way in which a clock edge can be used to activate a process. Figure 13 illustrates this. The different forms of process are equivalent and can be transformed onto one another. The above example shows this equivalence well. This transformation converts the three forms of sensitization into the most general form - the wait until form. However, it places the wait statement at the end of the process. process (clock) begin if c l o c k = ~I'
end
then
e n d if; process;
Concurrent signal assignment The concurrent signal assignment is an assignment which is executed every time one of its inputs changes• Figure 15 shows an example and its interpretation as a combinational logic process.
Block statement
a
There are two types of block statement: a simple block and a guarded block. Both forms simply represent restricted
process begin w a i t on c l o c k end process;
until
clock
=
'i';
b process begin if c l o c k
Another form of process is shown in Figure 14a. This is in fact the most general form of process using a wait statement. It shows that the wait statement may in fact appear anywhere in the process body. In practice, in a simulator, the set of statements A is executed before simulation time begins; it is an initialization sequence. Then, when the wait conditions are met, the set of statements B is executed• On reaching the end of the process, the process is restarted and so the set of statements A is re-executed. Since there is no such thing as initialization code in hardware, this part of the cycle can be dispensed with. This is equivalent to the transformation shown in Figure 14b.
architecture behaviour begin z < = a a n d b; end behaviour;
of
example3
is
a
=
'i'
architecture transformed begin process (a, b) begin z < = a a n d b; end process; end transformed;
then
e n d if; wait on clock; end process;
of
example3
is
C Figure 13 a, Sensitization list for edge triggered register; b, wait until statementfor edgetriggered register;c, wait on statementfor edgetriggered register
b Figure 15 a, Concurrent signaFassignment; b, in~rpretation as a combinational logic process
Microprocessors and Microsystems Volume 18 Number 8 October 1994
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Translation of VHDL for logic synthesis: M S Abrahams and A Rushton -- guarded block block ( e n a b l e : 'i,') begin x = guarded y; end block a
block_example block port (a, b : i n b i t ; port map (a = > Sl, b begin z < = a a n d b; end block blockexample;
z : out bit); = > $2, z = > $ 3 ) ;
a GUARD <= (enable = process ( G U A R D , y) begin if G U A R D t h e n x <= y; e n d if; end process
'I');
b
<=
Sl
and
S2;
b Figure 17 a, Simple block example; b, transformed simple [)lock
for
Figure16 a, Guardedblockexample;b, trans~rmationofguardedblock levels of scope for signals in the description. A simple block is equivalent to a set of concurrent statements, whilst a guarded block is equivalent to a number of conditional concurrent statements. A guarded block example is shown in Figure 16a and its transformation to a conditional process is shown in Figure 16b. The main complication in the transformation of blocks is that a block can have an interface. Actual signals in the architecture body can be bound to formal parameters used inside the block. An example of the transformation by inlining is shown in Figure 17.
Concurrent procedure call A concurrent procedure call is very similar to a concurrent assignment. The difference is that a procedure may contain a wait statement which can make the procedure call equivalent to either a combinational logic process or a registered process. This potential ambiguity can be resolved by inlining the procedure and enclosing it in a process statement. The resultant process can be analysed in the same way as any other process statement. The main difference is that, if there is no wait statement in the procedure, there is an implied wait on all the ~N mode "parameters of the procedure, The inline expansion of procedures is described later.
Loop statements Loop statements get unrolled by the translator, such that the contents of the loop are replicated. This means that loop constraints must be static. Given this condition, any form of loop can be unrolled.
Procedures and functions Each procedure call is expanded inline. The contents of the procedure are first copied into the process which called the procedure. Then the actual parameters are substituted for the formal parameters of the procedure. Finally, constant expressions depending on the parameters are evaluated.
466
$3
i in 1 to 3 loop v := v + a ( i ) ; s <= s + a(i); end loop;
a v := s <= v := s <= v := s <=
v s v s v s
+ a(1); + a(1); + a(2); + a(2); + a(3); + a(3);
b Figure 18
a, Original for ~oop; b, unrolled for loop statement
An important implication of the inlining of procedures is that it allows unconstrained arrays to be used in the procedure's interface. In substituting actual parameters, the unconstrained arrays are replaced by constrained arrays. This makes loop constraints or calculations based on the array dimensions into constant expressions, allowing the unrolling of loops. Declarations of objects in the declarative part of the procedure become declarations of objects in the declarative part of the calling process. The only changes to the declarations are changes made to ensure that all declarations are uniquely named. Figure 19 illustrates the method. Functions are inlined in a similar way to procedures. However, the method is complicated by the fact that functions are called within expressions and it is not possible to inline the function in the expression and retain a valid VHDL description. This problem is resolved by observing that VHDL functions are not allowed to have side effects and that VHDL expressions do not allow assignments within the expression. Therefore it is possible to inline the function immediately before the expression that called it. Then the return statement is replaced by an assignment to a temporary variable and the temporary variable is substituted for the function call within the calling expression. Figure 20 illustrates the idea. Since it is possible to have a function with more than one return statement in VHDL, such functions are transformed into functions with a single return statement. This is done by surrounding code that would be executed under conditions where the function would not have returned with an if statement. An example is shown in Figure 21.
Microprocessors and Microsystems Volume 18 Number 8 October 1994
Translation of VHDL for logic synthesis: M S Abrahams and A Rushton process
(x)
procedure f u n n y (a : in i n t e g e r ; z : out i n t e g e r ; t e m p : i n t e g e r := a; begin for i n d e x in 1 to c o u n t l o o p t e m p :- t e m p + index; end loop; z := temp; e n d funny; begin f u n n y (x, y, 3); end process;
count
: in n a t u r a l )
a function cond_invert (a : natural; e : boolean) return integer is temp : integer; returned : boolea~ := false; begin if e then temp := -a; returned := true; end if; if not returned then temp := a; end if; return temp; end cond_invert;
a p r o c e s s (x) temp : integer; begin t e m p := x; t e m p := t e m p + i; t e m p := t e m p + 2; £ e m p := t e m p + 3; y := temp; end process;
b Figure 21 a, Function with two return statements; b, transformed function with single return statement
b Figure 19
a, Original procedure; b, inlined procedure
p r o c e s s (y) f u n c t i o n invert (a : natural) begin return -a; end invert; begin z := invert (y); end process;
return natural
is
a process temp
(y) : natural;
begin temp
:=
z
temp;
:=
function cond_invert (a : natural; e : boolean) return integer is begin if e then return -a; end if; return a ; end c o n d i n v e r t ;
-y;
e n d process;
b Figure20 a, Original ~nction;b, inlinedfunction
CONCLUSIONS In general, logic synthesis from VHDL is quite possible. There are few constructs in the language which have to be ruled out entirely. The main restrictions are usually that the use of a construct is in some way restricted. For example, a for loop has to be constrained to fixed bounds at compile time. The rule of thumb approach for writing VHDL which can be synthesized it to avoid constructs which have no possible implementation in hardware; these include file, access and floating point types. The operators divide, mod, rem, ** are not usable in their most general forms for logic synthesis. In this paper, a description of the techniques required to synthesize VHDL to hardware has been given. VHDL is a broad language and a paper of this type cannot illustrate synthesis from every language feature. The main language features have been considered. We have left out configurations and packages, because these change none of the hardware implementation. For example, packages consist of types, procedures and functions; synthesis of those constructs has been explained in the techniques described here.
The techniques given here are used in the TransGATE synthesis system and may also be useful for those who wish to hand design hardware from VHDL models. It should be noted that the semantic completeness of VHDL extends only to constrain simulation tools of the language and does not go so far as to state the hardware implementation required by synthesis. The techniques for hardware implementation described here will not necessarily be the same as those used by other synthesis tools. In practice, the differences of language translation are likely to be small. However, multi-level synthesis heuristics used in synthesis tools for area optimization are likely to alter the structure created by the language translators in an effort to save area in the final implementation. This will tend to hide the hardware implementation of individual VHDL constructs. The main point of consideration for users of synthesis tools is that the user must develop the design using a synchronous design methodology since there is no capability as yet for asynchronous circuit synthesis. With this restriction, synthesis can be used in the design of combinational logic processes, registered logic processes or finite state machines.
ACKNOWLEDGEMENTS The authors would like to thank Paul Johnson for his contribution to the development of the TransGATE VHDL translator. This work was partly funded by the UK DTI Information Engineering Advanced Technology Programme by project IED2/1/1509.
REFERENCES 1 IEEEStandard VHDL Language Reference Manual IEEEStandardVHDL
1076-1987, IEEE,New York, USA (March 1988) 2 Lipsett,R, Schaefer,C and Ussary,C VHDL: Hardware Description and Design Kluwer Academic, Norwell, MA, USA (1989) 3 Coelho,D The VHDL Handbook KluwerAcademic, Norwell, MA, USA (1989) 4 More information on the CLSIVHDL Tool Integration Platform can be obtained from CAD LanguageSystemsInc., Suite 310, 15245 Shady Grove Road, Rockville, MD 20850, USA
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Logic synthesis can be achieved from the majority of VHDL, but some constructs have to be restricted. The techniques used in the TransGATE system to synthesize VHDL are explained. These ideas will be useful for those who wish to understand the process of designing hardware from VHDL models. It should be noted that the semantic completeness of VHDL extends only to constrain simulation tools and not to synthesis. Thus, techniques for hardware implementation described here will not necessarily be the same as other synthesis tools use. The main consideration for users of synthesis tools is to develop the design using a synchronous design methodology since there is no capability as yet for asynchronous circuit synthesis. With this restriction, synthesis can be used in the design of combinational logic processes, registered logic processes or finite state machines.
Keywords: VHDL, synthesis,translation
The preface to the IEEE standard 1076-1987 Language Reference Manual 1 makes bold claims about the importance of VHDL as a design language: 'The VHSIC hardware description language (VHDL) is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis and testing of hardware design data and the maintenance, modification and procurement of hardware.' In this paper, it will be shown that synthesis from VHDL is possible, although the hardware meaning of VHDL is not defined by the IEEE language standard. VHDL is said to have semantic completeness by virtue of the language reference manual 1 defining the language so precisely that any VHDL simulator is guaranteed to give the same result as any other. This is in contrast to hardware description languages which are not completely defined, where the behaviour of the simulation model can only be determined by experimentation. TransEDALtd, Pilgrims Close, Chandlers Ford, Eastleigh, Hampshire, SO5 3ST, UK Paper received: 29 September 1992
However, VHDL is defined only with regard to the behaviour of logic simulation tools; synthesis tools are free to determine a hardware meaning for VHDL constructs. The lack of a hardware interpretation in the VHDL standard means synthesis tools can interpret VHDL as the tool developer so desires, with the consequence of different hardware implementations being possible with different synthesis tools. Synthesis from VHDL is under debate by the VHDL analysis and standards group (VASG). In this paper, the interpretation of VHDL used by TransGATE is described. TransGATE is the logic synthesis system developed by TransEDA Limited. TransGATE accepts VHDL input as a register transfer level description or a component netlist. In a register transfer level description, the user puts in VHDL constructs which imply registers and the synthesis tool maps the implied registers and logic in between to a technology cell netlist. Only a few VHDL constructs are positively disallowed, but there are restrictions on the way constructs may be used. TransGATE requires that the user designs a synchronous circuit; feedback must be through registers. The large range of VHDL constructs preclude this paper from being a complete description of the subset of VHDL which can be transformed onto TransGATE, but the translation of the more frequently used constructs in VHDL will be described. Similarly, the paper does not attempt to be a VHDL language tutorial; familiarity with the basic language constructs and their meaning in simulation is assumed, and alternative reading for a VHDL introduction can be found in References 2 and 3.
SOFTWARE ORGANIZATION VHDL is translated onto the TransGATE synthesis system using the following strategy. VHDL text is analysed using the analyser from the CLSI VHDL tool integration platform (VTIP)4. A set of transformations is applied to reduce VHDL text to a small subset of the language. The new VHDL description is translated from this small subset onto the target data structures for logic synthesis. The process of VHDL translation in TransGATE is shown in Figure 1.
0141-9331/94/08/0459-09 ~/ 1994 Butterworth-Heinemann Ltd Microprocessors and Microsystems Volume 18 Number 8 October 1994
459
Translation of VHDL for logic synthesis: M S Abrahams and A Rushton
VHDLText
phase ~I synthesis is t{> ,~'xthl~I a VIII)I rwtli'q ~. l l)ll '-,~hemati( text which ~an bt, h a n d e d ,:m t~ lay~:}Lllh:,~4~,, a gate level simulator or a schematic viewu~. With tills target data structure in minrI, the next section describes how a synthesis subset <>f VHDL converts direclly onto TransGATE. After that, the earlier transformation phase will be describecl to show that a much wider subset of VHDL can be translormed into the synthesis subset.
F
I Analysis
CLSI format I
CONVERSION OF THE SYNTHESIS SUBSET
Transformations I Conversion Internal Format Figure 1 Organizationof the TransGATEVHDL translator The CLSI analyser is incorporated into TransGATE to give a seamless interface. It performs syntax checks and semantic checks to ensure that the text read conforms to the VHDL standard. At this stage, the entire language is supported by the analyser. However, a last pass through the analyser is used to perform additional checks for conformity to a synthesis subset. During the extra pass through the analyser, the CLSI data structures are transformed to convert a number of VHDL constructs into a small subset of the language. For example, the transformations perform procedure inlining and loop unrolling. Errors will be raised if structures are encountered which do not belong to the small subset for synthesis or cannot be transformed onto the synthesis subset. After analysis and transformation, the CLSI data structure representing the circuit contains structures which have a direct representation in the TransGATE synthesis view. The last phase, conversion, generates the TransGATE representation. Conversion is described in the following section. TransGATE represents the circuit as a directed graph, called a circuit graph. The arcs represent boolean signals and the nodes are either technology cell instances, boolean equations or are instances of circuit graphs from the next level down in the design hierarchy. Each graph has two special nodes, an input node representing the circuit inputs and an output node representing the circuit outputs. Since the data structure also supports cell instances and hierarchy, it is quite possible to mix high level design with hand crafting of critical modules. Tools in TransGATE perform multi-level synthesis and technology mapping. These tools read and write the circuit graph data structure. Multi-level synthesis collapses boolean equations which represent bad factors and extracts good common factors from the boolean network of the design to reduce the final circuit area. Technology mapping binds the boolean equation network to instances of gates from the selected implementation technology. The final
460
The synthesis subset is kept to a minimum on the understanding that this subset has a direct mapping onto the TransGATE (-ircuit graph data structure and hence a mapping to hardware. The transformation phase can convert a broader language subset into this smaller subset.
Design unit A design unit in VHDL consists of an entity declaration and an architecture body. An entity declaration is used in TransGATE to define the port's specification to a circuit graph, i.e. the input and output nodes. An architecture body defines the internals of the circuit graph.
Entity declaration A VHDL entity declaration is translated onto a TransGATE port specification by mapping types onto their bit maps and generating a set of names for the resulting bits. Type mapping will be described later. Only input and output ports are possible in TransGATE, which correspond to modes [N and OUT respectively. However, VHDL also supports INOUT mode. This represents a bidirectional signal which has no interpretation in TransGATE and therefore is flagged as non-compliant with the synthesis subset.
Architecture body An architecture body contains a set of processes and components. All other statements allowed in VHDL at this level are transformed into processes. Each process (:an be interpreted as a subgraph. Because processes have no interface of their own, the port specification of the subgraph is not obvious. The inputs of the subgraph are the set of signals read within the process. The outputs are the set of signals assigned to within the process. Since each statement in an architecture body is concurrent, it has a direct implementation in hardware, since clearly hardware is concurrent. Connections are made fronl the outputs of the subgraph driving a signal to all the inputs of subgraphs reading a signal. This is all that is required to wire up the graph representing an architecture body. A simple example illustrates the point. Figure 2a shows a simple entity declaration and architecture body, and Figure 2b shows the corresponding subgraphs generated for each process.
Microprocessors and Microsystems Volume 18 Number 8 October 1994
Translation of VHDL for logic synthesis: M S Abrahams and A Rushton e n t i t y e x a m p l e is p o r t (a: in natural; end example; architecture behaviour s i g n a l s : natural; begin p r o c e s s (a) begin s <= a; end process; p r o c e s s (s) begin z <= (s = 0); end process; end behaviour;
e n t i t y e x a m p l e 2 is p o r t (a, b : in r e s o l v e d _ b i t ; end example2;
z : Out b o o l e a n ) ;
of e x a m p l e
is
architecture behaviour begin p r o c e s s (a) begin z <= a; end process; p r o c e s s (b) begin z <= b; e n d process; end behaviour;
z : out
of e x a m p l e 2
resolved_bit);
is
a
a
a h~
b Figure 3 a, Multiple signal drivers; b, TransGATE interpretation or resolved multiple drivers
b Figure2 a, VHDL entity declaration and architecturebody; b, TransGATE
Process
interpretation of entity declaration and architecturebody
Resolution functions The problem with the VHDL model of concurrency in the architecture body is that it is quite legal to have a number of concurrent statements assigning to a signal (called 'drivers' in VHDL-speak). It is necessary to resolve multiple drivers. The VHDL language supports the concept of resolution functions associated with a type. If a signal of a particular type is driven more than once, the resolution function for that type is called to work out the value of the signal. This method is especially useful for modelling tristate buses (where all but one driver will be driving a 'Z' value). The use of multi-value logic types, such as the proposed IEEE standard STDULOGIC:
The general form of a process is a block of sequential statements whi~:h are executed every time a set of sensitization conditions are reached. The transformation into TransGATE format requires the interpretation of the sequential statements into a hardware representation effectively a sequential to concurrent statement transformation. The result is a graph which becomes a subgraph in the transformed architecture body. There are three basic types of process: combinational logic, registered combinational logic and finite state machine. A combinational logic block is represented by a process which is sensitive to any event on any of its inputs (the set of signals which the process reads). An example illustrating a combinational logic process is shown in Figure 4. The process must be sensitive to all of its inputs, none of which may be the clock signal.
type STD ULOGIC ('U ', 'X', '0', '1 ', 'Z', 'W', 'L', 'H', '-'); creates a large number of possible permutations and requires an analysis of the state strength system for the type being resolved. As the majority of type values represent modelling values and only two values represent true logic values, analysing the resolution function is extremely difficult. VHDL attributes are used instead to attach the resolution action to the type. Only two resolution functions have a hardware implementation and these are 'wired-and' and 'wired-or'. These are transformed into 'and' and 'or' functions respectively. An example of an architecture body requiring the use of a 'wired-and' resolution function is shown in Figure 3.
process (a, b, begin z <= (a a n d end process;
c) b)
or
c;
a
a
Z
Hierarchy A component instantiation represents a level of hierarchy in the design. This has a direct correspondence with the hierarchy in TransGATE.
b Figure 4 a, Combinational process; b, TransGATE interpretation of combinational process
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Translation of VHDL for logic synthesis: M S Abrahams and A Rushton process (elk, cst) begin if ('0' ;~ rst) then z <- '0': elsif ('0' = clk and clk'event) y <- a; z <= y; end if; end process;
then
a
F
Clka
z
rst
?
b Figure 5
a, Registered process; b, TransGATE interpretation of registered
pr(x ess Clock signals are excluded from the combinational logic process because they are inconsistent with the synchronous design methodology supported by logic synthesis; other tools in the TransGATE system cannot properly support clocks which are gated with data signals. This definition therefore requires TransGATE to know which signal is the clock signal in a VHDL description. Signal assignments in a combinational logic process are implemented as simple connections. A registered logic block is represented by a process which is sensitive to a clock edge and possibly a reset signal. Each registered process must be sensitive to one clock edge. The clock signal must only be used to control the process; it must not be used as part of any expression or
e n t i t y jk is p o r t (elk : in bit; q : out bit); e n d jk;
rst
: in bit;
j : in bit;
k
architecture s t a t e m a c h i n e of jk is t y p e s t a t e _ t y p e - - i s (stateO, s t a t e l ) ; signal state, next state : state_type := s t a t e O ; attribute state_signal of s t a t e : s i g n a l is ""; begin process (clk, rst) begin if (rst = '0') t h e n s t a t e <= s t a t e O ; elsif (clk'event and clk = s t a t e <= n e x t s t a t e ; e n d if; end prooess;
'i')
process (state, j, k) begin n e x t s t a t e <= s t a t e ; c a s e s t a t e is w h e n s t a t e O => q <= '0'; if j = 'i' t h e n n e x t s t a t e <= s t a t e l ; e n d if; w h e n s t a t e l => q <= 'I'; if k = 'i' t h e n n e x t s t a t e <= s t a t e O ; e n d if; e n d case; end process;
end
state
Figure 6
462
machine;
State machine for a J-K flip-flop
: in bit;
assignment. An example illustrating a registered Iogi( block (specifically a C-R [)lock) is shown in Figure' 7. Nole that all signals are defined at the archite(ture lew~l and lherefore must be exported from the process. Each signal assignment in the process is registered. Thus it is possible to represent a pipeline as a single process, as the example shows. This is the main difference between combinational and registered processes. A finite state machine is a special type of registered block. State machines need to be described by two processes: a registered process to store the state variable and a combinational pro(ess to describe state transitions and output decoding. The split into two processes is required to avoid registering the state machine output signal. If required, it is quite simple to register the output by adding a third process. State machine recognition requires that the state signal has an attribute so that two processes using signals of the state type can be linked together as one state machine during translation. Figure 6 shows an example of a simple state machine.
Feedback Feedback occurs when a process: • • • •
reads a variable before writing to it, assigns a variable in some but not all arms of an if or case statement, has a signal which is both an input and an output to a process, and assigns a signal in some but not all arms of an if or case statement.
In logic synthesis, asynchronous feedback is not allowed; only a purely synchronous design philosophy is supported. Thus it follows that feedback is only allowed in registered logic blocks. Of course, feedback is implicit in a state machine, but C-R blocks may also have registered feedback. Figure 7 illustrates the form of a registered process with feedback. The variable 'state' is read in the process before it is assigned a value..This example also illustrates that signal assignments are registered, in this case 'z' is registered.
then
Sequential statements Inside every process in an architecture body is a series of sequential statements. Each sequential statement maps onto a piece of hardware which in turn forms part of the circuit representing the process. Mapping sequential statements into concurrent hardware requires a number of interpretations which are not self-explanatory. The rest of this section describes these interpretations. Conditional operations - If and Case - translate to multiplexers. However, the conversion is cornplicated by the fact that a particular object may only be assigned in some branches of the conditional statement, and furthermore that a signal assigned in such circumstances will retain its value between process executions. This interaction between
Microprocessors and Microsystems Volume 18 Number 8 October 1994
Translation of VHDL for logic synthesis: M S Abrahams and A Rushton Sequential signal assignments have the property that later signal assignments override earlier signal assignments. The situation is more complex in the presence of conditional statements, because the translator cannot always remove redundant signal assignments, but must feed forward their values. In the example in Figure 9, when cl and c2 are true, the second assignment takes precedence since it is later in the process. If neither cl or c2 is true, no assignment takes place and the previous values of s must be fed back to the inputs.
process v a r i a b l e s t a t e : b i t := '0'; begin w a i t on c l o c k u n t i l c l o c k = 41'; if s t a t e = 'i' t h e n z <= a; s t a t e := ~0'; else z <= b; s t a t e := ~i'; e n d if; end process;
a clock
['~ star I
1
kF
L~
IP-
Z
"I
Dynamic indexing Dynamic indexing occurs when an index expression within an indexed name is not static. Each dynamic index expression translates to a dedicated block of multiplexing logic. In the example of Figure 10, the variable z is being writ-
b Figure 7 a, Feedbackin a registeredprocess;b, TransGATEinterpretation of registeredprocesswith feedback conditional statements and signal assignments allows synchronous feedback paths to be described conveniently. Each conditional statement translates to a multiplexer, with one output for each object that appears as the target of an assignment within the conditional statement. The boolean condition translates to a block of logic which feeds into the select input of each multiplexer, and the data inputs to each multiplexer are fed from the logic for the expression being assigned. If a particular variable is not assigned within one branch of any conditional operation in the process, then the value is fed back from the output of the previous process execution. This highlights the fact that internal signals can feed back from block outputs to inputs, where the values are available if required for the next process execution. Figure 8 shows an if statement without an else clause. Since only registered processes can contain feedback, combinational processes must have completely specified conditional statements.
process begin wait on clock until clock = ~i'; if cl then s <= a; end if; if c2 then s <= b; end if; end process;
a
value
clock
c2 I i c, l l all S
b
Jk~
.T] b
Figure 9 a, VHDL implying the feed forward of a previous value; b, TransGATEinterpretationfeedingforward a previousvalue a(index)
:= z;
a
process begin w a i t on c l o c k u n t i l c l o c k = 'i'; if e n a b l e t h e n f <= a and b; e n d if; end process;
index
/
I
I
a
clock ~ a[O] a[1] a[2]
a[0] a[l]
a[2]
a[3]
a[3]
b
b
Figure 8 a, Incompletely specified if statement; b, feedback resulting from incomplete if statements
Figure 10 a, Assigningto an array element; b, hardwarefor assigningto an array element
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Translation of VHDL for logic synthesis: M S Abrahams and A Rushton ten onto one of the bits of the four bit array a. The remaining three bits of the array retain their old values.
Operators
type
end x
The operators 'and', 'or', 'nand', 'nor', 'xor' and 'not' map directly to the primitive boolean operators. The xnor operator is supported in anticipation of the 1992 update. Operators -t-, and * are implemented using built in architecture for an adder, subtractor and multiplier. Where x is static, the operation 2 ' is equivalent to a left shift of a single bit by x places. Similarly, the operations y * 2',y/2' are equivalent to a left shift or right shift of y by x places. The operation x mod n, where n is a static, positive power of 2, is equivalent to performing the bitwise 'and' of n with a mask having the bottom Iogz(n) bits set. Relational operators on integer and enumeration types are implemented using bitwise xor to test for equality, and by using a special comparator circuit for less than or greater than. The attribute t'pos(x) becomes the identity function. The attribute t'val(x) truncates x to the number of bits in the representation of t'base, t'succ(x) and t'pred(x) become increment and decrement functions o n the position number of x, hut truncated to the range of t'base.
Types The mapping of data types from VHDL to hardware is governed by fixed rules, such that objects of the same data type always map to the same hardware structures. This ensures consistency between components of a design. Enumeration types translate to a bundle of wires, with n wires representing up to 2" states. The position number of the enumeration value is encoded as an unsigned binary integer, which simplifies the handling of relational operators and the attributes t'pos, t'val, t'succ and t'pred. Integer types translate to a bundle of wires, using unsigned or twos complement representation, depending upon whether the lower bound of the range is negative. For example, a type such as 'range 100 to 101' will be represented as 7 bits unsigned. For subtypes of enumeration and integer types, whether introduced explicitly or anonymously, the encoding is the same as the base type, but may be able to take advantage of the restricted range by using fewer wires. Thus, although objects of any type have similar type encodings, two objects of the same type may differ in the number of wires used in their representation. Assignments may require implicit conversion between representations. Type conversions, whether explicit or implicit, may imply widening or narrowing the integer bus, and possibly adding a sign bit or performing a sign extension. However, there is no point in widening the bus except where it is combined with a wider bus in an integer operation. Narrowing a bus may cause bits to be lost through truncation. It is assumed that any range constraints present in the VHDL coding will not be violated by the design, since range checking cannot be performed. Array types translate to a 'bundle of bundles of wire'.
464
recl
:
record
a
: bit;
....
b
: nibble;
--
represented represented
by 1 bit by 4 bits
record;
:
recl ;
a x.a x.b[O] x.b[l] x.b[2] x.b[3]
b Figure 11
a, Variable definition; b, namesgenerated
Names Where possible, name information from the VHDL sour{e is preserved in the TransGATE representation. Entity names are preserved as module names. Formal port names are used to derive input and output port names. Signal and variable names are used to derive the signal name on the node driving a net. Port, signal and variable names may all represent composite objects, and the type of even a scalar object may map onto more than one wire. Names ior composite objects are constructed by concatenating using a dot notation. For a member of a record, the member name is appended to the signal name. For a member of an array, the array index is appended to the signal name. For simple types which are represented by rnore than one bit (such as integers), the bit number is added to the name as an index, not as a suffix using the dot notation. Only one level of indexing is supported by TransGATE.
TRANSFORMING VHDL ONTO THE SYNTHESIS SUBSET A design is converted automatically into the synthesis subset by the transformation phase of translation. Transformation takes place entirely within the VTIP environment; the output is a new VHDL description that is stored in VTIP. It is thus possible for the user to extract and read the transformed description if so desired. This section describes the transformation process.
Non-standard processes The synthesis subset defines the interpretation of VHDL architecture bodies and three forms of processes within them. However, these processes are not the only concurrent statements that can occur in an architecture body. This section shows how most other concurrent statements (:an be transformed into one of the standard processes. There are three forms of sensitization which can be used in a process: the sensitization list, the wait until statement and the wait on statement. Figure 12 illustrates the three forms. The difference between the three forms is that the
Microprocessors and Microsystems Volume 18 Number 8 October 1994
Translation of VHDL for logic synthesis: M S Abrahams and A Rushton process begin
(a, b, c)
process begin statements w a i t ... statements end process;
end process;
a process begin
A
...
B
...
B A
... ...
a
wait until a'event end process;
or b ' e v e n t
or c'event;
b process begin wait on a, b, e n d process;
c;
process begin w a i t ... statements statements end process;
b Figure 14 a, General ~rm of the wait statement; b, trans~rmed general ~rm of the wait statement
C Figure12 a, Sensitizationlist;b, waituntilstatement;c, waitonstatement sensitization list method and the wait on statement can only handle events on a signal, whilst the wait until condition can impose additional tests. However, all of these examples are exactly equivalent. The wait until form (b) is the target form used in the synthesis subset; the other forms should be transformed into this form. Another good example is the way in which a clock edge can be used to activate a process. Figure 13 illustrates this. The different forms of process are equivalent and can be transformed onto one another. The above example shows this equivalence well. This transformation converts the three forms of sensitization into the most general form - the wait until form. However, it places the wait statement at the end of the process. process (clock) begin if c l o c k = ~I'
end
then
e n d if; process;
Concurrent signal assignment The concurrent signal assignment is an assignment which is executed every time one of its inputs changes• Figure 15 shows an example and its interpretation as a combinational logic process.
Block statement
a
There are two types of block statement: a simple block and a guarded block. Both forms simply represent restricted
process begin w a i t on c l o c k end process;
until
clock
=
'i';
b process begin if c l o c k
Another form of process is shown in Figure 14a. This is in fact the most general form of process using a wait statement. It shows that the wait statement may in fact appear anywhere in the process body. In practice, in a simulator, the set of statements A is executed before simulation time begins; it is an initialization sequence. Then, when the wait conditions are met, the set of statements B is executed• On reaching the end of the process, the process is restarted and so the set of statements A is re-executed. Since there is no such thing as initialization code in hardware, this part of the cycle can be dispensed with. This is equivalent to the transformation shown in Figure 14b.
architecture behaviour begin z < = a a n d b; end behaviour;
of
example3
is
a
=
'i'
architecture transformed begin process (a, b) begin z < = a a n d b; end process; end transformed;
then
e n d if; wait on clock; end process;
of
example3
is
C Figure 13 a, Sensitization list for edge triggered register; b, wait until statementfor edgetriggered register;c, wait on statementfor edgetriggered register
b Figure 15 a, Concurrent signaFassignment; b, in~rpretation as a combinational logic process
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Translation of VHDL for logic synthesis: M S Abrahams and A Rushton -- guarded block block ( e n a b l e : 'i,') begin x = guarded y; end block a
block_example block port (a, b : i n b i t ; port map (a = > Sl, b begin z < = a a n d b; end block blockexample;
z : out bit); = > $2, z = > $ 3 ) ;
a GUARD <= (enable = process ( G U A R D , y) begin if G U A R D t h e n x <= y; e n d if; end process
'I');
b
<=
Sl
and
S2;
b Figure 17 a, Simple block example; b, transformed simple [)lock
for
Figure16 a, Guardedblockexample;b, trans~rmationofguardedblock levels of scope for signals in the description. A simple block is equivalent to a set of concurrent statements, whilst a guarded block is equivalent to a number of conditional concurrent statements. A guarded block example is shown in Figure 16a and its transformation to a conditional process is shown in Figure 16b. The main complication in the transformation of blocks is that a block can have an interface. Actual signals in the architecture body can be bound to formal parameters used inside the block. An example of the transformation by inlining is shown in Figure 17.
Concurrent procedure call A concurrent procedure call is very similar to a concurrent assignment. The difference is that a procedure may contain a wait statement which can make the procedure call equivalent to either a combinational logic process or a registered process. This potential ambiguity can be resolved by inlining the procedure and enclosing it in a process statement. The resultant process can be analysed in the same way as any other process statement. The main difference is that, if there is no wait statement in the procedure, there is an implied wait on all the ~N mode "parameters of the procedure, The inline expansion of procedures is described later.
Loop statements Loop statements get unrolled by the translator, such that the contents of the loop are replicated. This means that loop constraints must be static. Given this condition, any form of loop can be unrolled.
Procedures and functions Each procedure call is expanded inline. The contents of the procedure are first copied into the process which called the procedure. Then the actual parameters are substituted for the formal parameters of the procedure. Finally, constant expressions depending on the parameters are evaluated.
466
$3
i in 1 to 3 loop v := v + a ( i ) ; s <= s + a(i); end loop;
a v := s <= v := s <= v := s <=
v s v s v s
+ a(1); + a(1); + a(2); + a(2); + a(3); + a(3);
b Figure 18
a, Original for ~oop; b, unrolled for loop statement
An important implication of the inlining of procedures is that it allows unconstrained arrays to be used in the procedure's interface. In substituting actual parameters, the unconstrained arrays are replaced by constrained arrays. This makes loop constraints or calculations based on the array dimensions into constant expressions, allowing the unrolling of loops. Declarations of objects in the declarative part of the procedure become declarations of objects in the declarative part of the calling process. The only changes to the declarations are changes made to ensure that all declarations are uniquely named. Figure 19 illustrates the method. Functions are inlined in a similar way to procedures. However, the method is complicated by the fact that functions are called within expressions and it is not possible to inline the function in the expression and retain a valid VHDL description. This problem is resolved by observing that VHDL functions are not allowed to have side effects and that VHDL expressions do not allow assignments within the expression. Therefore it is possible to inline the function immediately before the expression that called it. Then the return statement is replaced by an assignment to a temporary variable and the temporary variable is substituted for the function call within the calling expression. Figure 20 illustrates the idea. Since it is possible to have a function with more than one return statement in VHDL, such functions are transformed into functions with a single return statement. This is done by surrounding code that would be executed under conditions where the function would not have returned with an if statement. An example is shown in Figure 21.
Microprocessors and Microsystems Volume 18 Number 8 October 1994
Translation of VHDL for logic synthesis: M S Abrahams and A Rushton process
(x)
procedure f u n n y (a : in i n t e g e r ; z : out i n t e g e r ; t e m p : i n t e g e r := a; begin for i n d e x in 1 to c o u n t l o o p t e m p :- t e m p + index; end loop; z := temp; e n d funny; begin f u n n y (x, y, 3); end process;
count
: in n a t u r a l )
a function cond_invert (a : natural; e : boolean) return integer is temp : integer; returned : boolea~ := false; begin if e then temp := -a; returned := true; end if; if not returned then temp := a; end if; return temp; end cond_invert;
a p r o c e s s (x) temp : integer; begin t e m p := x; t e m p := t e m p + i; t e m p := t e m p + 2; £ e m p := t e m p + 3; y := temp; end process;
b Figure 21 a, Function with two return statements; b, transformed function with single return statement
b Figure 19
a, Original procedure; b, inlined procedure
p r o c e s s (y) f u n c t i o n invert (a : natural) begin return -a; end invert; begin z := invert (y); end process;
return natural
is
a process temp
(y) : natural;
begin temp
:=
z
temp;
:=
function cond_invert (a : natural; e : boolean) return integer is begin if e then return -a; end if; return a ; end c o n d i n v e r t ;
-y;
e n d process;
b Figure20 a, Original ~nction;b, inlinedfunction
CONCLUSIONS In general, logic synthesis from VHDL is quite possible. There are few constructs in the language which have to be ruled out entirely. The main restrictions are usually that the use of a construct is in some way restricted. For example, a for loop has to be constrained to fixed bounds at compile time. The rule of thumb approach for writing VHDL which can be synthesized it to avoid constructs which have no possible implementation in hardware; these include file, access and floating point types. The operators divide, mod, rem, ** are not usable in their most general forms for logic synthesis. In this paper, a description of the techniques required to synthesize VHDL to hardware has been given. VHDL is a broad language and a paper of this type cannot illustrate synthesis from every language feature. The main language features have been considered. We have left out configurations and packages, because these change none of the hardware implementation. For example, packages consist of types, procedures and functions; synthesis of those constructs has been explained in the techniques described here.
The techniques given here are used in the TransGATE synthesis system and may also be useful for those who wish to hand design hardware from VHDL models. It should be noted that the semantic completeness of VHDL extends only to constrain simulation tools of the language and does not go so far as to state the hardware implementation required by synthesis. The techniques for hardware implementation described here will not necessarily be the same as those used by other synthesis tools. In practice, the differences of language translation are likely to be small. However, multi-level synthesis heuristics used in synthesis tools for area optimization are likely to alter the structure created by the language translators in an effort to save area in the final implementation. This will tend to hide the hardware implementation of individual VHDL constructs. The main point of consideration for users of synthesis tools is that the user must develop the design using a synchronous design methodology since there is no capability as yet for asynchronous circuit synthesis. With this restriction, synthesis can be used in the design of combinational logic processes, registered logic processes or finite state machines.
ACKNOWLEDGEMENTS The authors would like to thank Paul Johnson for his contribution to the development of the TransGATE VHDL translator. This work was partly funded by the UK DTI Information Engineering Advanced Technology Programme by project IED2/1/1509.
REFERENCES 1 IEEEStandard VHDL Language Reference Manual IEEEStandardVHDL
1076-1987, IEEE,New York, USA (March 1988) 2 Lipsett,R, Schaefer,C and Ussary,C VHDL: Hardware Description and Design Kluwer Academic, Norwell, MA, USA (1989) 3 Coelho,D The VHDL Handbook KluwerAcademic, Norwell, MA, USA (1989) 4 More information on the CLSIVHDL Tool Integration Platform can be obtained from CAD LanguageSystemsInc., Suite 310, 15245 Shady Grove Road, Rockville, MD 20850, USA
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