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Trap-controlled bunching of electrons in acoustoelectric domains
324
WORLD
ABSTRACTS
ON MICROELECTRONICS
AND RELIABILITY
Phosphosilicate glass stabilization of FET devices. P. BALK and J. M. ELDRIDGE, Proc. I E E E 57, No. 9, September (1969), p. 1558. The threshold voltage of M O S - F E T devices can be effectively stabilized from changes due to field-assisted motion of Na + in the gate oxide by the addition of a phosphosilicate glass (PSG) layer. The effectiveness of the glass for this purpose is markedly enhanced by increasing the P20 5 concentration of the PSG. However, polarization of the PSG layer can, in turn, cause an appreciable instability of the threshold voltage. It is shown that detailed knowledge of the behavior of PSG layers permits prediction of the threshold stability of P2Os-treated F E T devices. Thus, threshold stability can be maintained to within 0.1 V/1000 A under device operating conditions by making a proper compromise on PSG thickness and P205 concentration. Such stabilizing films offer satisfactory protection against realistic Na + contamination levels. Quantitative data on these phenomena are presented, and a simple structural model is given to account for the polarization and the Na + trapping behavior of the films. The formation of PSG films by doping of SiO2 with P20~ at elevated temperatures is discussed.
Collector diffusion isolated integrated circuits. B. T. MURPHY, V. J. GLINSKI, P. A. GARY and R. A. PEDERSEN, Proc. I E E E 57, No. 9, September (1969), p. 1523. A new, simplified, bipolar integrated circuit structure is described. This structure eliminates the need for the conventional isolation diffusion. Isolation is accomplished with the collector diffusion. This results in fewer fabrication steps than are required in fabrication of the standard buried collector structure. In addition, the new structure has greater circuit packing density because of the smaller area required for isolation. Transistor-transistor logic circuits have been fabricated using the new structure. Using 5 gm masking tolerances and line widths, propagation delays of 5-7 nsec have been obtained at a power dissipation of 4 mW while achieving circuit packing densities 2.5 times higher than obtainable using the standard buried collector structure with the same masking tolerances. Circuits formed using 2-3 ~m tolerances and line widths resulted in propagation delays of 20 nsec at 0'4 m W power dissipation. Silicon-oxide interface studies by a photoelectric technique. C. R. VISWANATHANand SEIKI OGURA,Proc. I E E E 57, No. 9, September (1969), p. 1552. The growth of oxide layers on silicon is frequently carried out during the fabrication of integrated circuits. This paper describes the results of the study of the oxide layer and the Si-SiO2 interface in a MOS configuration, by a photoelectric technique. The interface barrier height and the built-in voltage VMS in the oxide layer of a MOS structure are measured. The effect of ion migration has been studied by subjecting the structure to bias-heat (BH) treatment. We have constructed the band energy diagram for a p-type 0.001 f~-cm MOS structure, both before and after BH treatment. The photoelectric technique is found to be a convenient tool to study and compare different oxidation processes. C h e m i c a l vapour deposition of silicon dioxide films. R. KESAVANand V. RATNAVATI, Indian 07. Technol. 7, September (1969), p. 282. A study has been made of the conditions under which silicon dioxide films can be deposited on silicon substrates by the reaction of a gas phase mixture of silicon tetrachloride, hydrogen and water vapour. The deposited silicon dioxide is transparent and amorphous and has a density similar to that of thermally grown silica. The chemical vapour deposition technique reported is highly promising because of the high deposition rate and its applicability being not limited to silicon substrates.
Trap-controlled bunching of electrons in acoustoelectric domains. M. SCHULZ and B. K. RIDLEY,Solid St. Commun. 7 (1969), p. 1027. For an acoustoelectric domain in GaAs the saturation current is found to be independent of the electron concentration. This result and incubation time measurements are in accord with a simple model of trap-controlled bunching of electrons in the domain.
Dielectric isolated integrated circuit substrate processes. U. S. DAVIDSOH-N and F. LEE, Proc. I E E E 57, No. 9, September (1969), p. 1532. Dielectric isolation has proven effective in raising inter-device breakdown voltages, lowering parasitic capacitances and increasing resistance to radiation damage. The fabrication of a dielectric-isolated substrate, prior to diffusions, requires adequate control of the thickness of the epitaxial layer, of crowning and warpage and of a necessarily smooth, damage-free surface. The mere juxtaposition of three or more layers of different materials, even before diffusion-induced strains, creates special problems because of coefficient-of-expansion mismatches. In addition, the substrates must pass through subsequent diffusion cycles and permit the fabrication of transistors with characteristics as good as (or better than) those made on p-n junction isolated substrates. There are three major methods of using silicon dioxide as a dielectric to separate active areas of an integrated circuit: (1) shapeback to the channels of a wafer which has had channels etched out and filled with polycrystalline silicon; (2) etch out and fill in with single crystal on an n + wafer which has already had isolation moats created; and (3) growth of polycrystalline silicon prior to etching the isolating channels. This paper describes and compares these methods.
The influence of reaction kinetics between BBr3 and O~ on the uniformity of base diffusion. P. C. PAREKH and D. R. GOLDSTIEN,Proc. I E E E 57, No. 9, September (1969), p. 1507. The variables affecting the uniformity of sheet resistance in a two-step base diffusion system (deposition and drive-in), using BBra as a source, have been investigated. The uniformity after the drive-in is predominantly dependent on the process variables during the
WORLD
ABSTRACTS
ON MICROELECTRONICS
AND RELIABILITY
Phosphosilicate glass stabilization of FET devices. P. BALK and J. M. ELDRIDGE, Proc. I E E E 57, No. 9, September (1969), p. 1558. The threshold voltage of M O S - F E T devices can be effectively stabilized from changes due to field-assisted motion of Na + in the gate oxide by the addition of a phosphosilicate glass (PSG) layer. The effectiveness of the glass for this purpose is markedly enhanced by increasing the P20 5 concentration of the PSG. However, polarization of the PSG layer can, in turn, cause an appreciable instability of the threshold voltage. It is shown that detailed knowledge of the behavior of PSG layers permits prediction of the threshold stability of P2Os-treated F E T devices. Thus, threshold stability can be maintained to within 0.1 V/1000 A under device operating conditions by making a proper compromise on PSG thickness and P205 concentration. Such stabilizing films offer satisfactory protection against realistic Na + contamination levels. Quantitative data on these phenomena are presented, and a simple structural model is given to account for the polarization and the Na + trapping behavior of the films. The formation of PSG films by doping of SiO2 with P20~ at elevated temperatures is discussed.
Collector diffusion isolated integrated circuits. B. T. MURPHY, V. J. GLINSKI, P. A. GARY and R. A. PEDERSEN, Proc. I E E E 57, No. 9, September (1969), p. 1523. A new, simplified, bipolar integrated circuit structure is described. This structure eliminates the need for the conventional isolation diffusion. Isolation is accomplished with the collector diffusion. This results in fewer fabrication steps than are required in fabrication of the standard buried collector structure. In addition, the new structure has greater circuit packing density because of the smaller area required for isolation. Transistor-transistor logic circuits have been fabricated using the new structure. Using 5 gm masking tolerances and line widths, propagation delays of 5-7 nsec have been obtained at a power dissipation of 4 mW while achieving circuit packing densities 2.5 times higher than obtainable using the standard buried collector structure with the same masking tolerances. Circuits formed using 2-3 ~m tolerances and line widths resulted in propagation delays of 20 nsec at 0'4 m W power dissipation. Silicon-oxide interface studies by a photoelectric technique. C. R. VISWANATHANand SEIKI OGURA,Proc. I E E E 57, No. 9, September (1969), p. 1552. The growth of oxide layers on silicon is frequently carried out during the fabrication of integrated circuits. This paper describes the results of the study of the oxide layer and the Si-SiO2 interface in a MOS configuration, by a photoelectric technique. The interface barrier height and the built-in voltage VMS in the oxide layer of a MOS structure are measured. The effect of ion migration has been studied by subjecting the structure to bias-heat (BH) treatment. We have constructed the band energy diagram for a p-type 0.001 f~-cm MOS structure, both before and after BH treatment. The photoelectric technique is found to be a convenient tool to study and compare different oxidation processes. C h e m i c a l vapour deposition of silicon dioxide films. R. KESAVANand V. RATNAVATI, Indian 07. Technol. 7, September (1969), p. 282. A study has been made of the conditions under which silicon dioxide films can be deposited on silicon substrates by the reaction of a gas phase mixture of silicon tetrachloride, hydrogen and water vapour. The deposited silicon dioxide is transparent and amorphous and has a density similar to that of thermally grown silica. The chemical vapour deposition technique reported is highly promising because of the high deposition rate and its applicability being not limited to silicon substrates.
Trap-controlled bunching of electrons in acoustoelectric domains. M. SCHULZ and B. K. RIDLEY,Solid St. Commun. 7 (1969), p. 1027. For an acoustoelectric domain in GaAs the saturation current is found to be independent of the electron concentration. This result and incubation time measurements are in accord with a simple model of trap-controlled bunching of electrons in the domain.
Dielectric isolated integrated circuit substrate processes. U. S. DAVIDSOH-N and F. LEE, Proc. I E E E 57, No. 9, September (1969), p. 1532. Dielectric isolation has proven effective in raising inter-device breakdown voltages, lowering parasitic capacitances and increasing resistance to radiation damage. The fabrication of a dielectric-isolated substrate, prior to diffusions, requires adequate control of the thickness of the epitaxial layer, of crowning and warpage and of a necessarily smooth, damage-free surface. The mere juxtaposition of three or more layers of different materials, even before diffusion-induced strains, creates special problems because of coefficient-of-expansion mismatches. In addition, the substrates must pass through subsequent diffusion cycles and permit the fabrication of transistors with characteristics as good as (or better than) those made on p-n junction isolated substrates. There are three major methods of using silicon dioxide as a dielectric to separate active areas of an integrated circuit: (1) shapeback to the channels of a wafer which has had channels etched out and filled with polycrystalline silicon; (2) etch out and fill in with single crystal on an n + wafer which has already had isolation moats created; and (3) growth of polycrystalline silicon prior to etching the isolating channels. This paper describes and compares these methods.
The influence of reaction kinetics between BBr3 and O~ on the uniformity of base diffusion. P. C. PAREKH and D. R. GOLDSTIEN,Proc. I E E E 57, No. 9, September (1969), p. 1507. The variables affecting the uniformity of sheet resistance in a two-step base diffusion system (deposition and drive-in), using BBra as a source, have been investigated. The uniformity after the drive-in is predominantly dependent on the process variables during the