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TRAPPISTe pixel sensor with 2 μm SOI technology
Nuclear Instruments and Methods in Physics Research A 633 (2011) S19–S21
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
TRAPPISTe pixel sensor with 2 mm SOI technology E. Cortina a, L. Soung Yee a, C. Renaux b, D. Flandre b, E. Martin a,n a b
CP3—Universite´ catholique de Louvain, B-1348 Louvain-la-Neuve, Belgium DICE—Universite´ catholique de Louvain, B-1348 Louvain-la-Neuve, Belgium
a r t i c l e in fo
abstract
Available online 17 June 2010
Tracking for particle physics instrumentation in SOI technology (TRAPPISTe-1) is an R&D project to study the feasibility of manufacturing a monolithic active pixel sensor (MAPS) in silicon on insulator (SOI) technology. The first prototype of this series of sensors has been designed with a 2 mm SOI CMOS technology available in UCL, Louvain-la-Neuve. Simulations are presented for this prototype. Leakage measurements have been done on a photovoltaic cell, manufactured in the same process on a low-resistivity substrate. As a next step, a high-resistivity demonstrator will be designed. & 2010 Elsevier B.V. All rights reserved.
Keywords: SOI Pixel detectors MAPS
1. Introduction Most pixel detectors that are currently in operation are hybrid active pixel sensor (HAPS), where the interconnection is done with flip-chip and bump bonding techniques, needing twice the thickness of silicon, thereby increasing undesirable effects like multiple scattering and manufacturing cost. MAPS can simplify the interconnection problem and reduce the material budget at the same time. There have been attempts to design MAPS sensors for high energy physics (HEP) applications, such as MIMOSA [1], ISIS[2], DEPFET[3], or SOI[4]. In SOI technology, the connection of the active circuitry with the underlying bulk substrate is done in situ by vias, allowing full charge collection with CMOS electronics on the top active layer. This technology in principle allows full depletion of the bulk substrate using the back gate contact, but the applied back gate voltage will affect the value of the threshold voltages of the active circuitry. This effect is known as the back gate effect [5].
2. General description TRAPPISTe is a proof of concept that will be fabricated in a 2 mm fully depleted SOI CMOS process [6]. The substrate consists (after thinning) of a P-type bulk of 100 mm thickness with a resistivity of 15–25 O cm. In a later phase, a resistivity of 5000 O cm will also be targeted. The substrate supports a 400 nm thick buried oxide layer and a 100 nm thick silicon active epitaxial layer in which the device circuitry is implemented. To n
Corresponding author. Tel.: +32 10 47 2994; fax: + 32 10 47 2414. E-mail address: [email protected] (E. Martin).
0168-9002/$ - see front matter & 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2010.06.109
create the pixel sensor in the bulk substrate, a lateral and vertical diode structure is used. First, a hole is opened in the buried oxide. Through the hole, an n-type (5 1016–4 1017 atoms/cm3) implant is performed. Although backside illumination would give 100% fill factor, this option is not possible in the case of low-resistivity bulk, because the signal would be highly attenuated in the vicinity of the depleted region. So we did not cover the whole pixel with metal in order to allow top illumination of the prototype. The readout circuitry surrounds the active detector area. Finally, a 10 mm wide p + guard ring with several metal bias contacts surrounds the pixel (see Fig.1). On the backside of the detector an aluminum contact is evaporated, to deplete the vertical diode. The TRAPPISTe test chip consists of an 8 8 array of such pixels, each with an area of 300 300 mm. Signal generation was simulated using ISE TCADTM release 10.0. An estimate of the current signal generated in the SOI bulk was done for different depletion voltages, for a thickness of 100 mm and a resistivity of 5000 O cm. The results obtained for different applied depletion voltages of 5, 10, 15, and 25 V were 49, 68, 83, and 107 mm respectively. Full depletion over 100 mm is thus reached at 25 V. To simulate the analog signal shape, we assumed drift of the charge carriers in the depleted region and diffusion in the non-depleted regions, and as a result we obtained typical collection times of less than 9 ns for V ¼25 V.
2.1. Measurement of the diode SOI sensor Whereas the simulations were performed with high resistivity characteristics for the bulk wafer, the first prototype will be fabricated using a low-resistivity wafer due to wafer availability. To measure and evaluate the performance of the
S20
E. Cortina et al. / Nuclear Instruments and Methods in Physics Research A 633 (2011) S19–S21
Fig. 1. Cross-section of the SOI sensor (left image), with a top view (on the right image).
Fig. 3. Standard layout of TRAPPISTe pixel cell.
measurements. The second set of measurements shows that to minimize the leakage current, a positive voltage with respect to the back gate electrode has to be applied. In that way, the depletion region of the bulk substrate is increased.
3. Pixel cell and readout
Fig. 2. Leakage measurements of the diode when setting the guard ring to a fixed voltage and varying the voltage applied to the back gate.
active component, we use the guard ring instead of the back gate, to deplete the bulk substrate, because this will also affect the threshold of the transistors in the active circuitry. The diode detector in the bulk can be described as an ideal MOS capacitor. By applying a fixed voltage, the area below the metal connection can be depleted and therefore, the voltage to be applied to both the guard ring and the back gate will be minimal. But there are also inversion and accumulation conditions to consider, with the presence of an additional current. To study these effects, a set of measurements has been performed to analyze the evolution of the leakage current under different bias conditions. The device on which the measurements were performed is a PIN lateral photodiode [7] designed as an interdigitated device in a square of 500 mm. As a result, three semiconductor devices appear in the substrate: a lateral PIN diode just below the buried oxide, a vertical PN diode between the anode and the substrate back contact, and finally, a resistor between the PIN cathode and the substrate back contact. Two kinds of measurements were done with the test structures. The first one is for the basic bulk diode. The first set of measurements involve the situation of setting the guard ring to a fixed voltage (0 V) and then sweeping the value of the voltage applied to the back gate from 5 to + 5 V. Results are shown in Fig.2. These results show that the currents measured are quite high, in the order 880 nA per pixel, which corresponds to 35.2 mA/cm2, considering a pixel area of 500 500 mm2, although this value is the addition of the three different semiconductor structures. The second set of measurements involve the setting the back gate set to a fixed voltage and then sweeping the value of the voltage applied to the guard ring. The results for a back gate applied voltage of 0 V and a sweep of the guard ring voltage from 5 to + 5 V show again that the leakage currents are quite high, in the same order of magnitude present in the previous set of
The main goal of this prototype is to validate the architecture while measuring the effect of threshold variations, dependant on the voltage applied at the back gate and to assess the radiation hardness of the device. To analyze the radiation hardness, the general matrix included different transistors in order to study which is the optimal device type with respect to radiation damage. Each pixel contains readout circuitry based on the standard MAPS 3 T architecture [8]. The standard architecture is based on a reset transistor that is used to set a potential at the floating detector node, a buffer transistor that is used in a source-follower configuration to buffer the signal, and a selection transistor that is used to transmit the signal found at the pixel detector. A modification has been made, to include different storage cells per pixel to increase the speed, with the advantage of including PMOS/NMOS transistors without decreasing the efficiency of the system. The grid of pixels is divided into different sections, which contain the same readout circuit implemented with different types of transistors, to study the most optimal transistor parameters to be used in this application. Four are available for n- and p-MOSFETs in the studied technology: standard Vt (0.46/ 0.46 V), high Vt (0.77 V/ 0.95 V), low Vt (0.24 V/ 0.08 V), and graded Vt. The last is a special graded-channel transistor, which offers much higher analog performance than a standard uniformly doped channel MOSFET especially for buffer circuits [9,10], see Fig.3 for the layout corresponding to a standard Vt pixel cell. The readout of the pixel matrix is controlled by read/write control lines. The write lines of each pixel are all connected so that all pixels are written at the same time. For readout, each column is selected one at a time. This selection is controlled by a shift register with an enable and clock input. Each column is connected in sequence to an output circuit that will digitalize the value. The simulation of three types of readout circuits with standard MOSFETs shows a gain of 4 V/V at the highest gain operating point. The operating point of the low Vt cell is around 1 V while the standard Vt and high Vt cells have an operating point around 1.6 V. The power consumption during a write and read cycle shows a peak value around 20 mW, during the charge of the registers. The AC response of the readout circuit for the three
E. Cortina et al. / Nuclear Instruments and Methods in Physics Research A 633 (2011) S19–S21
types of cells shows that the three cells behave similarly. The cutoff frequency is around 270 kHz and the bandwidth is 1 MHz with a phase margin of 1001.
4. Conclusions Previous studies have shown that one of the most important drawbacks of SOI technology in MAPS is the back gate effect. The feasibility of this technology has been studied, using a photovoltaic cell fabricated in the SOI process, and a prototype chip, the TRAPPISTe, has been designed and simulated.
S21
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
R. Turchetta, Nucl. Instr. and Meth. A Sec. A 458 (2001) 677. S. Hillert, Nucl. Instr. and Meth. A Sec. A 560 (2006) 36. P. Fisher, Technical Report, Bonn University and MPI Munich, HLL, April 2002. H. Ikeda, Nucl. Instr. and Meth. A Sec. A 579 (2007) 701. J.P. Colinge, in: Silicon-On-Insulator Technology: Materials to VLSI., 3rd edition, Springer, New York, 2004. D. Flandre, Solid-State Electron. 45 (2001) 541. O. Bulteel, R. Delamare, D. Flandre, IEEE International SOI Conference, California, USA, 5–9 October, 2009. G. Deptuch., IEEE Trans. Nucl. Sci. NS-49 (2) (2002) 601. MA Pavanello, Solid-State Electron. 44 (6) (2000) 917. M Souza, Solid-State Electron. 52 (12) (2008) 1933.
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
TRAPPISTe pixel sensor with 2 mm SOI technology E. Cortina a, L. Soung Yee a, C. Renaux b, D. Flandre b, E. Martin a,n a b
CP3—Universite´ catholique de Louvain, B-1348 Louvain-la-Neuve, Belgium DICE—Universite´ catholique de Louvain, B-1348 Louvain-la-Neuve, Belgium
a r t i c l e in fo
abstract
Available online 17 June 2010
Tracking for particle physics instrumentation in SOI technology (TRAPPISTe-1) is an R&D project to study the feasibility of manufacturing a monolithic active pixel sensor (MAPS) in silicon on insulator (SOI) technology. The first prototype of this series of sensors has been designed with a 2 mm SOI CMOS technology available in UCL, Louvain-la-Neuve. Simulations are presented for this prototype. Leakage measurements have been done on a photovoltaic cell, manufactured in the same process on a low-resistivity substrate. As a next step, a high-resistivity demonstrator will be designed. & 2010 Elsevier B.V. All rights reserved.
Keywords: SOI Pixel detectors MAPS
1. Introduction Most pixel detectors that are currently in operation are hybrid active pixel sensor (HAPS), where the interconnection is done with flip-chip and bump bonding techniques, needing twice the thickness of silicon, thereby increasing undesirable effects like multiple scattering and manufacturing cost. MAPS can simplify the interconnection problem and reduce the material budget at the same time. There have been attempts to design MAPS sensors for high energy physics (HEP) applications, such as MIMOSA [1], ISIS[2], DEPFET[3], or SOI[4]. In SOI technology, the connection of the active circuitry with the underlying bulk substrate is done in situ by vias, allowing full charge collection with CMOS electronics on the top active layer. This technology in principle allows full depletion of the bulk substrate using the back gate contact, but the applied back gate voltage will affect the value of the threshold voltages of the active circuitry. This effect is known as the back gate effect [5].
2. General description TRAPPISTe is a proof of concept that will be fabricated in a 2 mm fully depleted SOI CMOS process [6]. The substrate consists (after thinning) of a P-type bulk of 100 mm thickness with a resistivity of 15–25 O cm. In a later phase, a resistivity of 5000 O cm will also be targeted. The substrate supports a 400 nm thick buried oxide layer and a 100 nm thick silicon active epitaxial layer in which the device circuitry is implemented. To n
Corresponding author. Tel.: +32 10 47 2994; fax: + 32 10 47 2414. E-mail address: [email protected] (E. Martin).
0168-9002/$ - see front matter & 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2010.06.109
create the pixel sensor in the bulk substrate, a lateral and vertical diode structure is used. First, a hole is opened in the buried oxide. Through the hole, an n-type (5 1016–4 1017 atoms/cm3) implant is performed. Although backside illumination would give 100% fill factor, this option is not possible in the case of low-resistivity bulk, because the signal would be highly attenuated in the vicinity of the depleted region. So we did not cover the whole pixel with metal in order to allow top illumination of the prototype. The readout circuitry surrounds the active detector area. Finally, a 10 mm wide p + guard ring with several metal bias contacts surrounds the pixel (see Fig.1). On the backside of the detector an aluminum contact is evaporated, to deplete the vertical diode. The TRAPPISTe test chip consists of an 8 8 array of such pixels, each with an area of 300 300 mm. Signal generation was simulated using ISE TCADTM release 10.0. An estimate of the current signal generated in the SOI bulk was done for different depletion voltages, for a thickness of 100 mm and a resistivity of 5000 O cm. The results obtained for different applied depletion voltages of 5, 10, 15, and 25 V were 49, 68, 83, and 107 mm respectively. Full depletion over 100 mm is thus reached at 25 V. To simulate the analog signal shape, we assumed drift of the charge carriers in the depleted region and diffusion in the non-depleted regions, and as a result we obtained typical collection times of less than 9 ns for V ¼25 V.
2.1. Measurement of the diode SOI sensor Whereas the simulations were performed with high resistivity characteristics for the bulk wafer, the first prototype will be fabricated using a low-resistivity wafer due to wafer availability. To measure and evaluate the performance of the
S20
E. Cortina et al. / Nuclear Instruments and Methods in Physics Research A 633 (2011) S19–S21
Fig. 1. Cross-section of the SOI sensor (left image), with a top view (on the right image).
Fig. 3. Standard layout of TRAPPISTe pixel cell.
measurements. The second set of measurements shows that to minimize the leakage current, a positive voltage with respect to the back gate electrode has to be applied. In that way, the depletion region of the bulk substrate is increased.
3. Pixel cell and readout
Fig. 2. Leakage measurements of the diode when setting the guard ring to a fixed voltage and varying the voltage applied to the back gate.
active component, we use the guard ring instead of the back gate, to deplete the bulk substrate, because this will also affect the threshold of the transistors in the active circuitry. The diode detector in the bulk can be described as an ideal MOS capacitor. By applying a fixed voltage, the area below the metal connection can be depleted and therefore, the voltage to be applied to both the guard ring and the back gate will be minimal. But there are also inversion and accumulation conditions to consider, with the presence of an additional current. To study these effects, a set of measurements has been performed to analyze the evolution of the leakage current under different bias conditions. The device on which the measurements were performed is a PIN lateral photodiode [7] designed as an interdigitated device in a square of 500 mm. As a result, three semiconductor devices appear in the substrate: a lateral PIN diode just below the buried oxide, a vertical PN diode between the anode and the substrate back contact, and finally, a resistor between the PIN cathode and the substrate back contact. Two kinds of measurements were done with the test structures. The first one is for the basic bulk diode. The first set of measurements involve the situation of setting the guard ring to a fixed voltage (0 V) and then sweeping the value of the voltage applied to the back gate from 5 to + 5 V. Results are shown in Fig.2. These results show that the currents measured are quite high, in the order 880 nA per pixel, which corresponds to 35.2 mA/cm2, considering a pixel area of 500 500 mm2, although this value is the addition of the three different semiconductor structures. The second set of measurements involve the setting the back gate set to a fixed voltage and then sweeping the value of the voltage applied to the guard ring. The results for a back gate applied voltage of 0 V and a sweep of the guard ring voltage from 5 to + 5 V show again that the leakage currents are quite high, in the same order of magnitude present in the previous set of
The main goal of this prototype is to validate the architecture while measuring the effect of threshold variations, dependant on the voltage applied at the back gate and to assess the radiation hardness of the device. To analyze the radiation hardness, the general matrix included different transistors in order to study which is the optimal device type with respect to radiation damage. Each pixel contains readout circuitry based on the standard MAPS 3 T architecture [8]. The standard architecture is based on a reset transistor that is used to set a potential at the floating detector node, a buffer transistor that is used in a source-follower configuration to buffer the signal, and a selection transistor that is used to transmit the signal found at the pixel detector. A modification has been made, to include different storage cells per pixel to increase the speed, with the advantage of including PMOS/NMOS transistors without decreasing the efficiency of the system. The grid of pixels is divided into different sections, which contain the same readout circuit implemented with different types of transistors, to study the most optimal transistor parameters to be used in this application. Four are available for n- and p-MOSFETs in the studied technology: standard Vt (0.46/ 0.46 V), high Vt (0.77 V/ 0.95 V), low Vt (0.24 V/ 0.08 V), and graded Vt. The last is a special graded-channel transistor, which offers much higher analog performance than a standard uniformly doped channel MOSFET especially for buffer circuits [9,10], see Fig.3 for the layout corresponding to a standard Vt pixel cell. The readout of the pixel matrix is controlled by read/write control lines. The write lines of each pixel are all connected so that all pixels are written at the same time. For readout, each column is selected one at a time. This selection is controlled by a shift register with an enable and clock input. Each column is connected in sequence to an output circuit that will digitalize the value. The simulation of three types of readout circuits with standard MOSFETs shows a gain of 4 V/V at the highest gain operating point. The operating point of the low Vt cell is around 1 V while the standard Vt and high Vt cells have an operating point around 1.6 V. The power consumption during a write and read cycle shows a peak value around 20 mW, during the charge of the registers. The AC response of the readout circuit for the three
E. Cortina et al. / Nuclear Instruments and Methods in Physics Research A 633 (2011) S19–S21
types of cells shows that the three cells behave similarly. The cutoff frequency is around 270 kHz and the bandwidth is 1 MHz with a phase margin of 1001.
4. Conclusions Previous studies have shown that one of the most important drawbacks of SOI technology in MAPS is the back gate effect. The feasibility of this technology has been studied, using a photovoltaic cell fabricated in the SOI process, and a prototype chip, the TRAPPISTe, has been designed and simulated.
S21
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
R. Turchetta, Nucl. Instr. and Meth. A Sec. A 458 (2001) 677. S. Hillert, Nucl. Instr. and Meth. A Sec. A 560 (2006) 36. P. Fisher, Technical Report, Bonn University and MPI Munich, HLL, April 2002. H. Ikeda, Nucl. Instr. and Meth. A Sec. A 579 (2007) 701. J.P. Colinge, in: Silicon-On-Insulator Technology: Materials to VLSI., 3rd edition, Springer, New York, 2004. D. Flandre, Solid-State Electron. 45 (2001) 541. O. Bulteel, R. Delamare, D. Flandre, IEEE International SOI Conference, California, USA, 5–9 October, 2009. G. Deptuch., IEEE Trans. Nucl. Sci. NS-49 (2) (2002) 601. MA Pavanello, Solid-State Electron. 44 (6) (2000) 917. M Souza, Solid-State Electron. 52 (12) (2008) 1933.