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Trench superjunction VDMOS with charge imbalance cells
Solid-State Electronics 64 (2011) 14–17
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Trench superjunction VDMOS with charge imbalance cells Weifeng Sun ⇑, Jing Zhu, Qingsong Qian, Pengfei Cao, Siyang Liu, Zhan Su, Shengli Lu, Longxing Shi National ASIC System Engineering Research Center, Southeast University, Nanjing, PR China
a r t i c l e
i n f o
Article history: Received 15 February 2011 Received in revised form 25 May 2011 Accepted 7 July 2011 Available online 30 July 2011 The review of this paper was arranged by Prof. A. Zaslavsky
a b s t r a c t The breakdown capability of the trench superjunction (SJ) VDMOS with strip gate and rounded corner layout pattern is experimentally investigated. The investigation shows that the local charge imbalance of device’s corner is the reason for breakdown voltage degradation. In order to improve the breakdown capability and reliability of the device, an analytical model which is verified by the simulation using Sentaurus TCAD and experiment results is proposed to optimize the doping of p-pillar with respect to different cell pitches and corner radiuses. Finally, two robust 600 V trench SJ-VDMOS structures with different curvatures of the corner are proposed and fabricated. Ó 2011 Elsevier Ltd. All rights reserved.
Keywords: Trench Superjunction VDMOS Breakdown voltage Analytical model Charge imbalance
1. Introduction Superjunction VDMOS, with a drain drift region consisting of alternating n- and p-type, highly doped region, improves RonABV trade-off characteristics beyond silicon limit in relation to conventional VDMOS [1,2]. The SJ-VDMOS is widely used for electronic switches in a variety of power applications [3,4]. SJ-VDMOS can be fabricated by different process technique, such as multi-step epitaxial growth [5] and trench-filling technique [6]. The device cell pattern is also various. The hexagonal arrays, octagonal arrays, square arrays and lattice arrays can be used in the device with the multi-step epitaxial process. However, the trench devices can only use the interdigitated pattern because of the process limitation. The electric field profile becomes flat in the off-state when the n and p pillars are completely depleted before avalanche breakdown and the optimum breakdown voltage is obtained when the charge is balanced between the pillars. So the doping of p-pillar is designed under the charge balance condition in cell region. Limited by the process of deep trench etching and epitaxial growth, the angled corners may result in plenty of holes in refilled high quality crystalline silicon. Therefore, the layout need go through the rounded process. However, not all the cells are the same in the interdigitated device with a rounded corner. In this paper, it is demonstrated that the cells in the corner region will be in charge imbalance condition when the other cells ⇑ Corresponding author. Tel./fax: +86 25 83795077. E-mail address: [email protected] (W. Sun). 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.07.006
are charge balance in trench SJ-VDMOS with strip gate and rounded corner layout. So avalanche breakdown only occurs in the cells at chip’s corner region, which will influence the breakdown voltage and reliability of the device. In order to improve the breakdown characteristics and reliability of the device, an analytical model which builds a functional relationship among the optimum p-pillar doping and cell pitch and corner radius is proposed. Based on the simulation and experiment results, it is proved that the model is helpful in designing a robust trench SJ-VDMOS with rounded corner pattern. Finally two 600 V trench SJ-VDMOS structures with different radiuses of the corner are presented and fabricated. 2. Breakdown capability of the trench SJ-VDMOS with charge balance cell Considering the complexity and difficulty in trench etching and refilling, some trench SJ-VDMOS devices are fabricated with rounded corner layout pattern instead of orthogonal corner, as shown in Fig. 1a. The active region of the device can be divided into two parts: center and corner region. The radius of the corner is R. The gray-colored region is p-pillar region which is formed by trench etching and refilling. The widths of p-pillar and n-pillar are Wp and Wn respectively. Around the active region is the ring region, where the pillars are of circular arc form and the ring region is designed for preventing the transverse electric field. In order to keep the charge balance, the spacing between the end position of the p-pillars in the corner region and the innermost p-pillar in
15
W. Sun et al. / Solid-State Electronics 64 (2011) 14–17
(a)
4.0x10
-4
3.5x10
-4
3.0x10
-4
2.5x10
-4
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-4
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-4
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-4
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-5
Wn/2
Wn
Wn
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on egi
gR
Rin
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Cell Region p-pillar n-pillar
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Wp
R
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Experiment result Simulation result
0.0
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0
100
200
300
400
500
600
700
800
900
Drain voltage (V)
(b)
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n+ n+ pbody
n
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Fig. 3. Simulation and experiment results of the Trench SJ-VDMOS.
n+ n+ pbody
p
n
Wp
Wn
p
n
cell 1 Buffer Region
N- epi N+ sub Drain
A11 A13 P-pillar x1 n-pillar
WP
A12 Wn
cell 2 x2
Cell
Fig. 4. Enlarged schematic of cells in the corner of the active region. Fig. 1. Top view of the SJ-DMOS layout under investigation (a), and the crosssectional schematic of center active region (b) (The widths of p-pillar and n-pillar are 5 lm and 12 lm respectively; the thickness of n-epi and n-buffer are 40 lm and 5 lm respectively.).
Fig. 2. Measured infrared photoemission of trench SJ-VDMOS under avalanche condition.
the ring region should be Wn/2. Fig. 1b shows the cross-sectional schematic of two adjacent cells in the active region. The trench SJ-VDMOS under investigation is fabricated with the above layout pattern (Fig. 1a). Its doping concentration of p-pillar is optimized by the simulation of the cell in center active region under charge balance condition. Fig. 2 shows a measured infrared photoemission image in the device which is under avalanche condition. The emitted infrared light results from the recombination of
charge carriers, generated by avalanche multiplication. Therefore, it can demonstrate the location of avalanche breakdown of the investigated device. As shown in Fig. 2, the avalanche breakdown only occurs at the edge of the cells located in the corner region. The measured breakdown voltage of the chip decreases by about 40 V, comparing with the simulated results of charge balanced cells in chip’s center, as can be seen in Fig. 3. So the cells in corner region turn to be the major limitation of the breakdown capability and reliability of the device. It is generally known that Eq. (1) is used in the design for the charge balance condition in the cell region, where NA and ND are the doping concentration of p-pillar and n-pillar. Specific to the structure shown in Fig. 1b, pbody and n-buffer have opposite effects on the degree of charge imbalance. Consequently, the effect of n-buffer on charge imbalance gets weaken. To simplify it, we ignore the effect of n-buffer on charge imbalance in the following discussion. Even so, the values of NA and ND suit for Eq. (1) cannot make the charge balance in the cells located in the corner because of the irregular pattern. As can be seen from Fig. 4, the cell region in the corner can be divided into several parts named Cell 1, Cell 2 and so on. Sum of A11 and A12 is the total area of n-pillar region while A13 is the area of the p-pillar region in Cell 1. The area is a function of the cell pitch and corner radius. Then, the charge imbalance degree (C.I%) in Cell 1 can be derived from Eq. (2) on the basis of mathematical deduction, where R is the radius of the corner
NA W P ¼ ND W n
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi ½2RðW n þW P ÞðW n þW P Þ 1 2 12 ½R ðW n þ W P Þ ½2R ðW n þ W P ÞðW n þ W P Þ ðW n þ W P Þ 2R W2n W2n Q n Q P N D ðA12 þ A11 Þ N A W P X 1 2 R arctan RðW n þW P Þ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ C:I:% ¼ ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi ½2RðW n þW P ÞðW n þW P Þ Qn N D ðA12 þ A11 Þ 1 2 R arctan 12 ½R ðW n þ W P Þ ½2R ðW n þ W P ÞðW n þ W P Þ W P 2R W2n W2n 2 RðW n þW P Þ
ð1Þ
ð2Þ
W. Sun et al. / Solid-State Electronics 64 (2011) 14–17
3. Analytical model and discussion From the above analysis, charge imbalance in the corner is the obstacle to achieve higher breakdown voltage and to get a reliable device if we keep charge balance in the cells located in center active region. It is better to locally increase p-doping in the corner region due to the surplus of n-doping as discussed above in order to realize the charge balance in the corner. Nevertheless, since the device under investigation is fabricated using trench-filling technique, partially change of p-doping will increase the process complexity and cost. However, we can increase the doping of p-pillar homogeneously until the breakdown voltage of the cells in corner region is identical with that of the cells in central active region. So an analytical model for designing the optimum doping concentration of p-pillar in SJ-DMOS with different cell pitches and corner radius should be proposed. Assuming the impact of positive charge imbalance degree (C.I.P%) and negative charge imbalance degree (C.I.N%) on the breakdown voltage is almost the same. Neglecting the influence of the buffer region of the device (as shown in Fig. 1b), the C.I.P% of the cell in chip’s center can be defined as the following equation:
C:I:P% ¼
ðN0A W p N D W n Þ ND W n
ð3Þ
where N 0A is the optimum p-doping, ND is the doping concentration of n-pillar. The C.I.N% of the Cell 1 in chip’s corner (as shown in Fig. 4) is:
C:I:N% ¼
ND ðA12 þ A11 Þ N0A A13 ND ðA12 þ A11 Þ
ð4Þ
In order to obtain the highest breakdown voltage of the device, the positive charge imbalance degree should be equal to the negative one (C.I.P% = C.I.N%), then the optimal doping can be expressed as
3.15E+015
Doping in p-pillar (cm-3)
The degree of charge imbalance (n > p) in Cell 1 is 14.1% when Wn = 12 lm, Wp = 5 lm and R = 207 lm. Similarly, the degree of charge imbalance in Cell 2 is 5.9% calculated by the same method. Moreover, it is worth noting that charge imbalance effect in Cell 1 is the most serious and breakdown will occur at Cell 1 initially which is corresponded to the experimental observation (as shown in Fig. 2).
Formula fitting curve Simulated results Measured results
3.14E+015 3.13E+015 3.12E+015 3.11E+015 3.10E+015 125
150
175
200
225
250
275
Corner radius (um) Fig. 5. Relationship between the optimized p-doping and the corner radius with fixed cell pitch (Wp = 5 lm, Wn = 12 lm, ND = 1.2E15 cm3).
7.00E+015
Doping in p-pillar (cm-3)
16
Formula fitting curve Simulated results Measured results
6.00E+015 5.00E+015 4.00E+015 3.00E+015 2.00E+015
2
4
6
8
WP (um) Fig. 6. Relationship between the optimized p-doping and Wp (R = 207 lm, Wn = 12 lm, ND = 1.24E15 cm3).
A good agreement can be found except that the concentration of p-pillar from test results is little higher, which due to the neglect of influence caused by buffer region (as shown in Fig. 1b). Noting
N D W n ND W n W n ND ðA12 þ A11 Þ W n W p A13 þ Wp W n A13 þ W P ðA12 þ A11 Þ 3 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ½2RðW n þW P ÞðW n þW P Þ Wn Wn 1 2 1 R arctan ½R ðW þ W Þ ½2R ðW þ W ÞðW þ W Þ ðW þ W Þ 2R n P n P n P n P 2 2 RðW n þW P Þ 2 2 7 ND W n 6 61 þ 7 ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4 5 p ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi WP ½2RðW n þW P ÞðW n þW P Þ Wn Wn 1 2 1 R arctan 2 ½R ðW n þ W P Þ ½2R ðW n þ W P ÞðW n þ W P Þ þ ðW n W P Þ 2R 2 2 RðW n þW P Þ 2
N0A ¼
From Eq. (5), it is worth noting that NDWn/Wp is the optimized value of p-pillar with only considering charge balance of the cells in chip’s center and the practical optimized value of p-pillar N 0A will be higher. The optimized p-doping of the device N 0A is closely connected with corner radius and cell pitch. Figs. 5 and 6 show the relationship between the optimized p-doping and the corner radius, the width of p-pillar, respectively. As can be observed in Figs. 5 and 6, the doping value of p-pillar shows a positive correlation to the corner radius and a negative correlation to the width of p-pillar. It is demonstrated that the model is in a good accordance with the simulation and experiment results.
ð5Þ
withstanding this limitation, this analytical model does play a guiding means in selecting the optimum p-doping of trench SJVDMOS with round corner.
4. Device structure with charge imbalance cell In this paper, two 600 V trench SJ-VDMOS with strip gate and rounded corner pattern layout are fabricated in terms of the analytical model. The radiuses of the corner in the two devices are 207 lm and 137 lm respectively. The p-pillar width is 5 lm and the space between the p-pillars is 12 lm. Using the analytical
W. Sun et al. / Solid-State Electronics 64 (2011) 14–17 -4
5. Conclusion
4.0x10
Radius=207um after optimization R=137um after optimization R=207um before optimization
-4
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17
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R=207um before optimization
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100
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300
400
500
600
700
800
900
The breakdown characteristics are studied in trench SJ-VDMOS with strip gate and rounded corner layout. It is demonstrated that local excessive n-doping in chip’s corner is the reason for breakdown voltage reduction by experiment. An analytical model is proposed which can be used to determine the optimal p-doping of SJ-DMOS with respect to different cell pitches and corner radius. Verified by simulation and experiment results, the proposed model provides an effective method to enhance the breakdown capability of trench SJ-VDMOS. In terms of the presented model, two 600 V robust device structures with different radiuses of the corner pattern are fabricated. These devices break down at center active region and their breakdown voltages are both 696 V.
Drain voltage (V) Fig. 7. Measurement breakdown voltage of the SJ-VDMOS devices with different corner radius before and after optimization (ND = 1.2E15 cm3).
model combined with Eq. (3), the C.I.% in cells after optimization are 7.6% and 7.43%, respectively. In terms of measured results, the C.I.% should be 8.3% and 7.6%, respectively. The difference between two kinds of results agrees with the difference between test results and formula fitting curve as shown in Fig. 5. Fig. 7 is the experimental breakdown voltage results of the proposed devices. As shown in Fig. 7, all these devices break down at their center active regions and their breakdown voltage are all 695 V when the p-doping are 3.12E15 cm3 and 3.1E15 cm3 respectively, while the BV under center cells in charge balance is 650 V. The improvement in BV is 6.9% approximately.
Reference [1] Chen XB, Mawby PA, Board K, Salama CAT. Theory of a novel voltage-sustaining layer for power devices. Microelectron J 1998:1005–11. [2] Lorenz L, Deboy G, Knapp A, Miirz M. COOLMOS – a new milestone in high voltage power MOS. ISPSD 1999:3–10. [3] Saito W, Omura I, Aida S, Koduki S, Izumisawa M, Yoshioka H, et al. Over 1000V semi-superjunction MOSFET with ultra-low on-resistance blow the si-limit. ISPSD 2005:27–30. [4] Takao K, Hayashi Y, Harada S, Ohashi H. Study on advanced power device performance under real circuit conditions with an exact power loss simulator. Power Electron Appl 2007:1–10. [5] Deboy G et al. A new generation of high voltage MOSFETs breaks the limit line of silicon. IEDM 1998:683–5. [6] Iwamoto S, Takahashi K, Kuribayashi H. Above 500V class Superjunction MOSFETs fabricated by deep trench etching and epitaxial growth[C]. In: The 17th international symposium on power semiconductor device and Ics; 2005. p. 31–4.
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Trench superjunction VDMOS with charge imbalance cells Weifeng Sun ⇑, Jing Zhu, Qingsong Qian, Pengfei Cao, Siyang Liu, Zhan Su, Shengli Lu, Longxing Shi National ASIC System Engineering Research Center, Southeast University, Nanjing, PR China
a r t i c l e
i n f o
Article history: Received 15 February 2011 Received in revised form 25 May 2011 Accepted 7 July 2011 Available online 30 July 2011 The review of this paper was arranged by Prof. A. Zaslavsky
a b s t r a c t The breakdown capability of the trench superjunction (SJ) VDMOS with strip gate and rounded corner layout pattern is experimentally investigated. The investigation shows that the local charge imbalance of device’s corner is the reason for breakdown voltage degradation. In order to improve the breakdown capability and reliability of the device, an analytical model which is verified by the simulation using Sentaurus TCAD and experiment results is proposed to optimize the doping of p-pillar with respect to different cell pitches and corner radiuses. Finally, two robust 600 V trench SJ-VDMOS structures with different curvatures of the corner are proposed and fabricated. Ó 2011 Elsevier Ltd. All rights reserved.
Keywords: Trench Superjunction VDMOS Breakdown voltage Analytical model Charge imbalance
1. Introduction Superjunction VDMOS, with a drain drift region consisting of alternating n- and p-type, highly doped region, improves RonABV trade-off characteristics beyond silicon limit in relation to conventional VDMOS [1,2]. The SJ-VDMOS is widely used for electronic switches in a variety of power applications [3,4]. SJ-VDMOS can be fabricated by different process technique, such as multi-step epitaxial growth [5] and trench-filling technique [6]. The device cell pattern is also various. The hexagonal arrays, octagonal arrays, square arrays and lattice arrays can be used in the device with the multi-step epitaxial process. However, the trench devices can only use the interdigitated pattern because of the process limitation. The electric field profile becomes flat in the off-state when the n and p pillars are completely depleted before avalanche breakdown and the optimum breakdown voltage is obtained when the charge is balanced between the pillars. So the doping of p-pillar is designed under the charge balance condition in cell region. Limited by the process of deep trench etching and epitaxial growth, the angled corners may result in plenty of holes in refilled high quality crystalline silicon. Therefore, the layout need go through the rounded process. However, not all the cells are the same in the interdigitated device with a rounded corner. In this paper, it is demonstrated that the cells in the corner region will be in charge imbalance condition when the other cells ⇑ Corresponding author. Tel./fax: +86 25 83795077. E-mail address: [email protected] (W. Sun). 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.07.006
are charge balance in trench SJ-VDMOS with strip gate and rounded corner layout. So avalanche breakdown only occurs in the cells at chip’s corner region, which will influence the breakdown voltage and reliability of the device. In order to improve the breakdown characteristics and reliability of the device, an analytical model which builds a functional relationship among the optimum p-pillar doping and cell pitch and corner radius is proposed. Based on the simulation and experiment results, it is proved that the model is helpful in designing a robust trench SJ-VDMOS with rounded corner pattern. Finally two 600 V trench SJ-VDMOS structures with different radiuses of the corner are presented and fabricated. 2. Breakdown capability of the trench SJ-VDMOS with charge balance cell Considering the complexity and difficulty in trench etching and refilling, some trench SJ-VDMOS devices are fabricated with rounded corner layout pattern instead of orthogonal corner, as shown in Fig. 1a. The active region of the device can be divided into two parts: center and corner region. The radius of the corner is R. The gray-colored region is p-pillar region which is formed by trench etching and refilling. The widths of p-pillar and n-pillar are Wp and Wn respectively. Around the active region is the ring region, where the pillars are of circular arc form and the ring region is designed for preventing the transverse electric field. In order to keep the charge balance, the spacing between the end position of the p-pillars in the corner region and the innermost p-pillar in
15
W. Sun et al. / Solid-State Electronics 64 (2011) 14–17
(a)
4.0x10
-4
3.5x10
-4
3.0x10
-4
2.5x10
-4
2.0x10
-4
1.5x10
-4
1.0x10
-4
5.0x10
-5
Wn/2
Wn
Wn
Wp
on egi
gR
Rin
Corner
Cell Region p-pillar n-pillar
Drain current (A)
Wn/2
Wp
R
Center
Experiment result Simulation result
0.0
Cell Region
0
100
200
300
400
500
600
700
800
900
Drain voltage (V)
(b)
Source
Gate
n+ n+ pbody
n
Source
Fig. 3. Simulation and experiment results of the Trench SJ-VDMOS.
n+ n+ pbody
p
n
Wp
Wn
p
n
cell 1 Buffer Region
N- epi N+ sub Drain
A11 A13 P-pillar x1 n-pillar
WP
A12 Wn
cell 2 x2
Cell
Fig. 4. Enlarged schematic of cells in the corner of the active region. Fig. 1. Top view of the SJ-DMOS layout under investigation (a), and the crosssectional schematic of center active region (b) (The widths of p-pillar and n-pillar are 5 lm and 12 lm respectively; the thickness of n-epi and n-buffer are 40 lm and 5 lm respectively.).
Fig. 2. Measured infrared photoemission of trench SJ-VDMOS under avalanche condition.
the ring region should be Wn/2. Fig. 1b shows the cross-sectional schematic of two adjacent cells in the active region. The trench SJ-VDMOS under investigation is fabricated with the above layout pattern (Fig. 1a). Its doping concentration of p-pillar is optimized by the simulation of the cell in center active region under charge balance condition. Fig. 2 shows a measured infrared photoemission image in the device which is under avalanche condition. The emitted infrared light results from the recombination of
charge carriers, generated by avalanche multiplication. Therefore, it can demonstrate the location of avalanche breakdown of the investigated device. As shown in Fig. 2, the avalanche breakdown only occurs at the edge of the cells located in the corner region. The measured breakdown voltage of the chip decreases by about 40 V, comparing with the simulated results of charge balanced cells in chip’s center, as can be seen in Fig. 3. So the cells in corner region turn to be the major limitation of the breakdown capability and reliability of the device. It is generally known that Eq. (1) is used in the design for the charge balance condition in the cell region, where NA and ND are the doping concentration of p-pillar and n-pillar. Specific to the structure shown in Fig. 1b, pbody and n-buffer have opposite effects on the degree of charge imbalance. Consequently, the effect of n-buffer on charge imbalance gets weaken. To simplify it, we ignore the effect of n-buffer on charge imbalance in the following discussion. Even so, the values of NA and ND suit for Eq. (1) cannot make the charge balance in the cells located in the corner because of the irregular pattern. As can be seen from Fig. 4, the cell region in the corner can be divided into several parts named Cell 1, Cell 2 and so on. Sum of A11 and A12 is the total area of n-pillar region while A13 is the area of the p-pillar region in Cell 1. The area is a function of the cell pitch and corner radius. Then, the charge imbalance degree (C.I%) in Cell 1 can be derived from Eq. (2) on the basis of mathematical deduction, where R is the radius of the corner
NA W P ¼ ND W n
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi ½2RðW n þW P ÞðW n þW P Þ 1 2 12 ½R ðW n þ W P Þ ½2R ðW n þ W P ÞðW n þ W P Þ ðW n þ W P Þ 2R W2n W2n Q n Q P N D ðA12 þ A11 Þ N A W P X 1 2 R arctan RðW n þW P Þ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ C:I:% ¼ ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi ½2RðW n þW P ÞðW n þW P Þ Qn N D ðA12 þ A11 Þ 1 2 R arctan 12 ½R ðW n þ W P Þ ½2R ðW n þ W P ÞðW n þ W P Þ W P 2R W2n W2n 2 RðW n þW P Þ
ð1Þ
ð2Þ
W. Sun et al. / Solid-State Electronics 64 (2011) 14–17
3. Analytical model and discussion From the above analysis, charge imbalance in the corner is the obstacle to achieve higher breakdown voltage and to get a reliable device if we keep charge balance in the cells located in center active region. It is better to locally increase p-doping in the corner region due to the surplus of n-doping as discussed above in order to realize the charge balance in the corner. Nevertheless, since the device under investigation is fabricated using trench-filling technique, partially change of p-doping will increase the process complexity and cost. However, we can increase the doping of p-pillar homogeneously until the breakdown voltage of the cells in corner region is identical with that of the cells in central active region. So an analytical model for designing the optimum doping concentration of p-pillar in SJ-DMOS with different cell pitches and corner radius should be proposed. Assuming the impact of positive charge imbalance degree (C.I.P%) and negative charge imbalance degree (C.I.N%) on the breakdown voltage is almost the same. Neglecting the influence of the buffer region of the device (as shown in Fig. 1b), the C.I.P% of the cell in chip’s center can be defined as the following equation:
C:I:P% ¼
ðN0A W p N D W n Þ ND W n
ð3Þ
where N 0A is the optimum p-doping, ND is the doping concentration of n-pillar. The C.I.N% of the Cell 1 in chip’s corner (as shown in Fig. 4) is:
C:I:N% ¼
ND ðA12 þ A11 Þ N0A A13 ND ðA12 þ A11 Þ
ð4Þ
In order to obtain the highest breakdown voltage of the device, the positive charge imbalance degree should be equal to the negative one (C.I.P% = C.I.N%), then the optimal doping can be expressed as
3.15E+015
Doping in p-pillar (cm-3)
The degree of charge imbalance (n > p) in Cell 1 is 14.1% when Wn = 12 lm, Wp = 5 lm and R = 207 lm. Similarly, the degree of charge imbalance in Cell 2 is 5.9% calculated by the same method. Moreover, it is worth noting that charge imbalance effect in Cell 1 is the most serious and breakdown will occur at Cell 1 initially which is corresponded to the experimental observation (as shown in Fig. 2).
Formula fitting curve Simulated results Measured results
3.14E+015 3.13E+015 3.12E+015 3.11E+015 3.10E+015 125
150
175
200
225
250
275
Corner radius (um) Fig. 5. Relationship between the optimized p-doping and the corner radius with fixed cell pitch (Wp = 5 lm, Wn = 12 lm, ND = 1.2E15 cm3).
7.00E+015
Doping in p-pillar (cm-3)
16
Formula fitting curve Simulated results Measured results
6.00E+015 5.00E+015 4.00E+015 3.00E+015 2.00E+015
2
4
6
8
WP (um) Fig. 6. Relationship between the optimized p-doping and Wp (R = 207 lm, Wn = 12 lm, ND = 1.24E15 cm3).
A good agreement can be found except that the concentration of p-pillar from test results is little higher, which due to the neglect of influence caused by buffer region (as shown in Fig. 1b). Noting
N D W n ND W n W n ND ðA12 þ A11 Þ W n W p A13 þ Wp W n A13 þ W P ðA12 þ A11 Þ 3 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ½2RðW n þW P ÞðW n þW P Þ Wn Wn 1 2 1 R arctan ½R ðW þ W Þ ½2R ðW þ W ÞðW þ W Þ ðW þ W Þ 2R n P n P n P n P 2 2 RðW n þW P Þ 2 2 7 ND W n 6 61 þ 7 ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4 5 p ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi WP ½2RðW n þW P ÞðW n þW P Þ Wn Wn 1 2 1 R arctan 2 ½R ðW n þ W P Þ ½2R ðW n þ W P ÞðW n þ W P Þ þ ðW n W P Þ 2R 2 2 RðW n þW P Þ 2
N0A ¼
From Eq. (5), it is worth noting that NDWn/Wp is the optimized value of p-pillar with only considering charge balance of the cells in chip’s center and the practical optimized value of p-pillar N 0A will be higher. The optimized p-doping of the device N 0A is closely connected with corner radius and cell pitch. Figs. 5 and 6 show the relationship between the optimized p-doping and the corner radius, the width of p-pillar, respectively. As can be observed in Figs. 5 and 6, the doping value of p-pillar shows a positive correlation to the corner radius and a negative correlation to the width of p-pillar. It is demonstrated that the model is in a good accordance with the simulation and experiment results.
ð5Þ
withstanding this limitation, this analytical model does play a guiding means in selecting the optimum p-doping of trench SJVDMOS with round corner.
4. Device structure with charge imbalance cell In this paper, two 600 V trench SJ-VDMOS with strip gate and rounded corner pattern layout are fabricated in terms of the analytical model. The radiuses of the corner in the two devices are 207 lm and 137 lm respectively. The p-pillar width is 5 lm and the space between the p-pillars is 12 lm. Using the analytical
W. Sun et al. / Solid-State Electronics 64 (2011) 14–17 -4
5. Conclusion
4.0x10
Radius=207um after optimization R=137um after optimization R=207um before optimization
-4
3.5x10
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Drain current (A)
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3.0x10
R=207um before optimization
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1.0x10
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900
The breakdown characteristics are studied in trench SJ-VDMOS with strip gate and rounded corner layout. It is demonstrated that local excessive n-doping in chip’s corner is the reason for breakdown voltage reduction by experiment. An analytical model is proposed which can be used to determine the optimal p-doping of SJ-DMOS with respect to different cell pitches and corner radius. Verified by simulation and experiment results, the proposed model provides an effective method to enhance the breakdown capability of trench SJ-VDMOS. In terms of the presented model, two 600 V robust device structures with different radiuses of the corner pattern are fabricated. These devices break down at center active region and their breakdown voltages are both 696 V.
Drain voltage (V) Fig. 7. Measurement breakdown voltage of the SJ-VDMOS devices with different corner radius before and after optimization (ND = 1.2E15 cm3).
model combined with Eq. (3), the C.I.% in cells after optimization are 7.6% and 7.43%, respectively. In terms of measured results, the C.I.% should be 8.3% and 7.6%, respectively. The difference between two kinds of results agrees with the difference between test results and formula fitting curve as shown in Fig. 5. Fig. 7 is the experimental breakdown voltage results of the proposed devices. As shown in Fig. 7, all these devices break down at their center active regions and their breakdown voltage are all 695 V when the p-doping are 3.12E15 cm3 and 3.1E15 cm3 respectively, while the BV under center cells in charge balance is 650 V. The improvement in BV is 6.9% approximately.
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