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Trends of power semiconductor wafer level packaging
Microelectronics Reliability 50 (2010) 514–521
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Trends of power semiconductor wafer level packaging Yong Liu * Fairchild Semiconductor Corp., South Portland, ME 04074, United States
a r t i c l e
i n f o
Article history: Received 18 June 2009 Received in revised form 25 August 2009 Available online 12 October 2009
a b s t r a c t A review of recent advances in power wafer level electronic packaging is presented based on the development of power device integration. The paper covers in more detail how advances in both semiconductor content and power advanced wafer level package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with next generation wafer level power packaging development, the role of modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of wafer level power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed. Ó 2009 Elsevier Ltd. All rights reserved.
1. Introduction Over the last two decades, power semiconductor technology has made impressive progress, particularly in the increasingly high power density of monolithic, system multiple function and hybrid designs [1–3], which are the driving forces towards both the monolithic package and three dimensional (3D) power solution with heterogeneous functional integration. The development of power packages depends on the development of power device integration. Current power devices include the power integrated circuit (IC)s, high voltage IC (HVIC), discrete metal oxide semiconductor field effect transistor (MOSFET), intelligent discrete power device, combined with functional integration and the integration of passive elements. Hybrid integration includes the standard power module and the intelligent power module (IPM) for high power application. Today’s power integration solution has covered multiple functions, which is one of major directions of power wafer level package development. The trends are going towards wafer level 3D heterogeneous integration with high switching frequency and with reduced or eliminated bulky magnetics and capacitances as well as soft switching technologies for high efficiency and low harmonics [3]. Silicon carbide (SiC) and other wide bandgap (WBG) semiconductor devices will ultimately be important elements for hybrid integration to advance system dynamic characteristics, overload capability, device ruggedness, and thermal and electrical performance [4–8].
* Tel.: +1 (207) 761 3155; fax: +1 (207) 761 6339. E-mail address: [email protected] 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2009.09.002
This paper introduces the power wafer level package trends based on above power device development. A review of recent advances in power wafer level electronic packaging which focuses on monolithic power integrations is presented. It covers in more detail how advances in both semiconductor content and advanced wafer level package design and the materials have co-enabled the significant advances in power device capability during recent years. Extrapolating the same trends in representative areas to the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power wafer level semiconductor solutions. Challenges of power wafer level semiconductor packaging in both next generation design and assembly process are presented and discussed. In addition to the forward looking trends it is important to recognize that the methods for concurrent engineering of these solutions (both the semiconductor content and high performance package capability) are becoming more increasingly dependent on rigorous use of proven multi-physics/FEA tools and techniques for both new power package development and its assembly process. The challenges for modeling of power semiconductor package in new package and assembly process are investigated and discussed.
2. Challenges of power wafer level semiconductor packaging Today, providing energy efficient solutions for various products is becoming increasingly important in our world due to limited energy resources and climate change. Especially significant is the fast growth of consumer electronics in both communications and entertainment, industrial power conversion, automotive, and
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standard power electronics products. Consumer demand for increased mobility with advanced features and for high efficiency energy solutions has paved the way for a variety of new products [9], and has driven advances in power electronics technology towards the high power density design of monolithic devices, discrete components and 3D heterogeneous wafer level solutions as well as the wafer level stacking with silicon through vias (TSV) [10]. As compared to the development in general IC package [11–19], the power wafer level package is far behind due to the extremely harsh operation environment. New modeling methodologies and tools are becoming necessary to support new generation power wafer level package development. This paper describes the challenges for today and the next few years in power wafer level package development which should be addressed by the industry. 2.1. Die shrinkage impact The development of power semiconductor device has begun to aim at 130 nm technology, while today 180 nm and 250 nm technologies is beginning to drive significant die size shrinkage as compared to regular 350 nm or 500 nm power technology. As the metal interconnect system inside the die continues to become thinner, current density has significantly increased. The electromigration (EM) issues will grow and new interconnect alternatives will be considered. Current techniques such as the wafer level solder bumping or Cu-stud bumping will meet the challenges of material inter metallic diffusion and mechanical cratering issue for wafer level Cu-stud bumping. As the die shrinks, the pitch of power wafer level chip scale packages (CSP) will move from current 0.5 mm towards 0.4 mm. The heat dissipation will become a very critical and significant challenge. Finding a high efficiency heat dissipation solution is necessary. 2.2. Wafer level power system on chip (SOC) vs. system in package (SIP) The power integration devices allows the state of art smart power IC with technology such as integration of bipolar, complementary metal oxide semiconductor (CMOS) and double diffused metal oxide semiconductor (DMOS)-BCDMOS, intelligent discrete power device, and the function integration in both lateral DMOS (LDMOS) and vertical DMOS (VDMOS) for power control and protection as well as other functions. This is so called power semiconductor system on chip (SOC), which is the integration of several heterogeneous technologies-analog, digital, MOSFETs, etc. into a single silicon chip. However, such power SOC technology often is too expensive and complex. This leads to a wealth of opportunities for system in package (SIP), in which multiple chips with different functions are placed in one package or module [20] which has similar function of SOC but with a lower cost. SIP has evolved as an alternative approach to SOC for electronics integration because this technology provides advantages over SOC in many market segments. In particular SIP provides more integration flexibility, faster time to market, lower research and development (R&D) or non-recurring engineering (NRE) cost, and lower product cost than SOC for many applications. SIP is not a replacement for high level, single chip, and silicon integration but should be viewed as complementary to SOC. For some very high volume applications SOC will be the preferred approach, like a power SOC with the integration of LDMOSFETs and IC controller, the cost of the SOC is not expensive due to larger volume of production as compared to the SIP with two MOSFET die and an IC controller die. In such case, the electric performance of the SOC is clearly super as compared to the SIP. Some complex SIP products will contain SOC components. Wafer level SIP/stack is one major direction for lower power application.
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As the die shrinks, SOC can add more functions, and SIP can include more chips. In SOC, the thermal density will become very high. Determining how to insulate different functions in one chip and how to effectively dissipate the heat through the package will be a challenge [21–25]. Although the cost of SIP is low, there are challenges due to the assembly of wafer level multiple chips to wafer. The internal parasitic effects of SIP, like parasitic inductance [22], are higher than SOC. The impact of heat from the power components on the electrical performance of IC drivers will be a concern. To build an advanced SIP which has good thermal and electrical performance with low cost is the largest challenge of power wafer level SIP. Modeling and simulation efforts must be used to support the SIP development from design, reliability and assembly process [26–36]. 2.3. New power package materials Development of new materials to support wafer level package process, heat transfer and good electrical performance is critical. An example is to develop new molding compound material with reasonable content of nano silica fillers to be suitable wafer level molding and to rapidly dissipate heat from the power die while keeping the adhesion strength high. At present, both Pb-free solders and green epoxy mold compound material (EMC) are used and accepted by most companies. Thermal stability is a key issue [9], especially in the automotive environment, where current epoxy mold compound materials have difficulties meeting the requirement of exceeding 180°C continuous operation. The new green EMC will have to withstand such temperatures from the power chip. Pb-free solder must have high melting temperatures and EMC should not be burnt in high temperature operation. As the chip shrinks, there are two trends in power packages. The first is the fan-in application for power wafer level packages, which are gaining wider applications without EMC. The second is the fanout wafer level package, which use the wafer level molding to make the interconnect re-distribution. This is particularly useful for the chip with smaller pitch and shrank die. For this latter trend, the EMC usage is not decreasing [18,21]. 3. Trends in discrete wafer level power MOSFET packages 3.1. Wafer level MOSFET compared to regular discrete power package Table 1 shows the typical development trends of discrete MOSFET package. It gives the representative power transistor package constituent volumetric percentages. As the package develops from Fairchild early DPak (TO252) through SO8 to MOSFET BGA and MOSFET WLCSP, the molding compound decreases as a percentage of volume, until it reaches zero with the MOSFET BGA and WLCSP packages. At the same time the silicon and interconnect metal increases as a percentage of volume. At DPAk level, leadframe is about 20% and silicon is about 4%, while EMC is about 75%. At WLCSP level, the silicon is about 82%. There is no EMC in the WL-CSP. Fig. 1 shows the discrete wafer level – CSP for schottky diode and vertical MOSFET from the released products of Vishay and Fairchild semiconductor. Those WL-CSPs are called fan-in layout. However, the advantage of EMC is that it can enhance handling and mechanical robustness, as it has in the past. It can provide substantial protection and mechanical integrity to place components across a wide generational range of pick and place equipment. So the EMC today in discrete power package is still useful as a component ‘‘encapsulant”. For wafer level power package, the EMC can be used as the re-distribution layer (fan-out) material through the molding for the fan-out wafer level package. That allows for the
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Table 1 Typical discrete power package constituent volumetric percentages towards WL-CSP [1]. Package type
Total volume (mm3)
Approximately % EMC
Approximately % silicon
Approximately % leadframe
Approximately % interconnect
TO-252 (wire) SO8 (wire) SO8 (clip) MOSFET BGA WL-CSP
90 28 28 20 20
75 83 70 0 0
4 6 6 40 82
20 10 20 50 0
1 1 2 10 18
Fig. 3. Trends of low power package development.
Fig. 1. Examples of discrete WL-CSP.
larger pitch for a smaller shrank die. Fig. 2 gives the example of fan-out structure by using wafer level epoxy molding technology. 3.2. Higher current carrying capability One trend of the discrete wafer level power package is to increase the current carrying capability per unit area; this is partly due to the customer’s request for high current capability and partly due to the die shrinkage. Fig. 3 shows the trends of low power MOSFET package development in the industry, the data was selected from the released products of Vishay, IR and Fairchild Semiconductor, which includes both wafer level power discrete package and regular power discrete package. To better manage the thermal performance with the trend to higher current carrying capability in wafer level power package,
Fig. 2. EMC as the re-distribution substrate of fan-out wafer level package in Infineon [21].
there are two approaches: one is to intensify the thermal management requirements from the print circuit board (PCB) level and the other is heat dissipation in multiple directions at the package level which is advantageous for wafer level discrete power packages. Bonding the wafer level power discrete package to a metal frame is an effective approach. Bonding die to metal wafer with preetched cavity is the wafer level process to get the wafer level package with multiple direction heat dissipation. Fig. 4 shows the examples of multiple direction heat transfer of Fairchild MOSFET BGA and Vishay PolarPAK.
3.3. Low Rdson resistance and better thermal performance To get lower Rdson and to improve the thermal performance, the wafer level MOSFET with vertical metal-oxide can be built on a silicon substrate thinned to 7 lm and plated with 50 lm copper
Fig. 4. Multiple direction heat transfer packages.
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Fig. 5. (a) Fairchild UMOSFET and (b) regular MOSFET [28].
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Fig. 7. Wafer level integrated power solution.
and ‘‘adaptive” motion control at the high end. For the voltage range at 100–700 V, next generation of integrated LDMOS structures reach the limits of Si for breakdown voltage (BVdss) as a function of geometry, which allows a corresponding increase in HV monolithic power conversion capability (AC–DC) and results in an incremental raising of the limit at which multiple die are requested in the actual products. 4.2. Smaller package footprints
as its drain, see Ref. [28] Fairchild wafer level UMSFET. This extremely reduces the Rdson resistance and improves the thermal performance. Fig. 5 shows the internal device structure of the UMOSFET and its comparison with regular MOSFET.
As power die size shrinks, the package footprints shrink as well, and maintaining the thermal transfer capacity at the package level is difficult since the function/unit area of die is increasing with advanced BCDMOS processes. While the overall package footprint trend is decreasing area, the thermal dissipation capabilities rely more on the PCB as part of the system. Therefore insuring mechanical integrity of WL-CSP in the form of bare flipped die in conjunction with board level assembly of a heat sink is difficult, see Fig. 8.
3.4. Move the MOSFET drain to front side
4.3. Wafer level micro-channel
For the wafer level discrete MOSFET, another trend which obtains the attention in the industry is to move the drain of the MOSFET to the front side of the die so that the drain, source and gate are at the same side. This would be helpful for the surface mounting application in various PCBs. Fig. 6 shows one of the lateral layouts of the drain for a LDMOS WL-CSP. Since the drain is in lateral placement, the back metal does not contact the drain directly, so its application limits to lower power and lower voltage area. For VDMOS WL-CSP, the trend is to develop the directly connection to the front side by TSV in trench area. The advantage of the direct connection the back drain to front side is its good electrical performance with lower Rdson. Because this is a vertical DMOS, the application area may be relative wider in power range as compared to the structure in Fig. 6.
Instead of air cooling for power wafer level package, one trend is to build the wafer level micro-channel on power chip. This can effectively take the heat out of the power chip. Fig. 9 gives an example of building the micro-channels on both power die active surface and back side. Due to the high efficiency of cooling through the micro-channels, heat sink is not needed anymore. This may significantly reduce the space of heat sink and remove the noise induced by the fans in the cooling system.
Fig. 6. Move the drain to the front side the MOSFET.
4. Trends in power IC packages Fig. 8. Example of WL-CSP which is hard to mount the heat sink.
4.1. Higher power density at the wafer level For the voltage range at 5–100 V, there are a wider range of inductive loads handled with a monolithic solution and higher level of functional integration in monolithic solution. The most interesting application is the wafer level integrated system power conversion solution which combines two power switches (the high side and lower side) together with an IC driver. Fig. 7 shows an example of such a wafer level power system on chip. There are also integrated advanced digital control functions for motion which includes ‘‘sensorless” positioning and fault detection at the low end
Fig. 9. Micro-channels on both active side and back side die [24].
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5. Trends in wafer level passives Although the wafer level passives (resistor, capacitor and inductor) in today are only suitable for very low and tiny power, it is possible for them to integrate with low power BCDMOS or other active IC. Integration of active power switches and passives in wafer level can greatly improve the electrical performance and significantly reduce the parasitic effects. For relative larger power products, like buck converter and DrMos with passives, the development is on going. Fig. 10 gives the development samples of wafer level inductors for power application [29], which indicates the current level with frequency. One significant advantage of the wafer level inductor integration is its frequency can reach from several MHz to 100 MHz, which the regular package level and board integration level are hard to get. 6. Trends in power SIP/3D development In many power conversion and power management applications, the optimized semiconductor solution is a combination of lateral and vertical conduction devices. This makes a monolithic silicon solution with both power switching (VDMOS/IGBT) and control function (BCDMOS/CMOS IC) impractical. Therefore the Power SIP becomes necessary. Currently there are two major trends in power SIP/3D package development: one is the wafer level CSP bumping on the leadframe to form various stacked die power package; another one is the fully wafer level 3D package with TSV.
Current flows across the front side of the die. The die is attached to the substrate by insulating die attach material. Fig. 12 shows a wafer level side by side placement SIP, a new concept of lateral interconnects is proposed for control and communication between die [30]. This concept may be used for the system power solution with side by side die placement. In power application, the value of ‘‘SIP” is directly related to reducing board level design complexity and space for power delivery and control and also related to providing reduced parasitic effects in high performance switching applications. One application of the power SIP is to expand ease of point of load (POL) power regulation and management. As an example of the POL, Fig. 13 shows a MOSFET SIP with a high side WL-CSP and a low side WL-CSP bumped on a metal substrate for a buck converter. Fig. 14 shows the profile of power efficiency (%) vs. current load of the SIP. It can be seen from the profile that the average efficiency of the SIP is about 2–5% higher than the individual MOSFETs. 6.2. Stacked/3D power SIP The above SIP with side by side placed dice has certain drawbacks: its geometry size is not as small as desired, and the electrical performance such as the parasitic effect also needs further improvement. Ref. [22] discussed a regular SIP (not a wafer level)
6.1. Side by side placed multiple die SIP The SIP as defined here contains at least two die in a package as shown in Fig. 11. One die is the VDMOS, which is attached to a wafer level metal substrate by a conductive die attach. The current flows through die and the metal layer. Another die is the driver IC which uses lateral electric conduction with substrate grounded.
Fig. 12. A wafer level side by side SIP with lateral interconnects [30].
Fig. 10. Wafer level passives [29].
Fig. 11. A two die power SIP.
Fig. 13. A SIP of buck converter.
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Fig. 16. A two phase buck converter SIP with wafer level power CSP bumped on leadframe.
Fig. 14. Power efficiency (%) vs. current load (I).
of a voltage regulator with component side by side placement and the stacked SIP and found that the stacked SIP has 55% lower parasitic inductance than side by side placed SIP. This is particularly important for portable applications, and for small size industry applications. 6.2.1. Power discrete WL-CSP bumped on leadframe The trend of stacked power package is from simply enhancing one function towards systematic function and multiple functions while reducing the board level complexity and space. Fig. 15 shows a two phase buck converter circuitry. Fig. 16 shows a stacked SIP for a two phase buck regulator, which is built by four single wafer level discrete power CSPs bumped on leadframe and encapsulated with mold. Such a SIP has inherent advantages of load splitting and output ripple dividing over its single-phase counterpart and is a suitable candidate in many applications, given the trends towards lower supply voltages and greater load–current requirements with low cost. The bottom exposed drains and top exposed source provide the two way heat dissipation for a better thermal performance. 6.2.2. Wafer level stack/3D power die SIP There are two stacking wafer level methods for power die SIP. One is to stack die on the wafer and the other is to stack two wafers. Fig. 17 shows the active IC die is stacked on the passive wafer. The power IC die with two MOSFETs and a IC driver is bonded on the passive wafer with inductor L. Fig. 18 shows an example of a wafer level stacked die package of two MOSFETs bonded together
Fig. 17. Stacked active die on passive wafer [29].
Fig. 18. Wafer level stacked power die package with TSVs by two stacked wafers.
with wafer 1 source and wafer 2 drain. The common source (wafer 1)/drain (wafer 2) may be connected to at least one front side by TSVs. This stacking process can be done through wafer on wafer. The advantage of this integration is the very good electrical performance for a half bridge with both N channel or P channel MOSFETs for products like liquid crystal display (LCD) back light inverters. Since the distance between high side die and low side die is very short, this greatly reduces the electrical resistance and parasitic effects. 7. Trends in power package modeling
Fig. 15. A typical two phase buck converter circuitry.
The power package development today is becoming increasingly dependent on rigorous use of proven multi-physics/FEA tools and techniques. Correct use of the modeling tools can definitely save design time and shorten the number of design cycles. The challenge is, can the modeling tool and methodology be ready to support the new trends in the development of new wafer level power package technology? Examples of the challenges include various designs, reliability and assembly modeling which include EM simulation; diffusion along the interface of two metal materials; contamination at the interface between different material layers; thermal resistance definition in SIP; 3D copper stud bumping simulation, etc.
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The greatest challenges in modeling for wafer level power packages today are the multi-physics and multi-scale simulations which couple the electrical, thermal and mechanical fields, and the assembly process simulation in a wafer level power package system with multi-scale layout from nanometers to millimeters. Development of highly efficient modeling algorithms for such a power WLP system is very critical for virtual prototyping of new products. In some cases, the WLP might have strong thermomechanical performance but is weak in electrical function or the WLP has very good electrical performance but is weak in thermomechanical design. Therefore it is necessary to determine the best solution using modeling in design phase. Package measurements are expensive, time consuming, and cannot provide all of the required information. ITRS SIP 2008 white paper [23] describes a future vision of chippackage system co-design: (a) One tool for simultaneous design enabled by a multi-user, cross-functional EDA + system analysis + knowledge-based tool. (b) A wizard-like interface, automatically constructs baseline design for each component based on series of user questions, analysis and an expert system for technology selection and design rules. These ideas cover stress/mechanical modeling, thermal chip-package system and electrical chip-package system. This indicates a modeling trend of the industry is towards package system design automation. Fig. 19 shows the modeling role in all areas of the semiconductor power industry from wafer IC design to final product. One of the major modeling tools for packages is finite element analysis (FEA). Advances in the power package development need the high efficiency, and short design cycles, in which the FEA use will accelerate the further miniaturization of power electronic components, and accelerate the incorporation of advanced materials and assembly structures. However, most of the power package design engineers, material engineers, test engineers and the reliability analysis engineers are not familiar with FEA. If they can run designed experiments using FEA for their product optimization in co-designed power package efforts and for material selection, that will really accelerate the power package development. Therefore, to develop the modeling automation system is one trend of the power package modeling. This system allows people who might not know FEA but wish to do design optimization for their product to run FEA. Engineers just simply input some basic information and set the numerical design of experiment (DOE), the system will automatically do the meshing, apply boundary conditions and loads, solving and automatically output the results. Refs. [26] and [27] have developed the initial modeling automation system for thermal, moisture and linear thermal–mechanical stress analysis. The results have shown great efficiency to save modeling time.
Fig. 20 shows an example of thermal simulation automation. The user only needs to input the basic information, load the sold model from computer aided design (CAD) Lib, choose the power applied, natural convention or forced convention, and then click the button ‘‘solve”, the automation system will automatically mesh the model, apply the power and thermal boundary condition, and solve the problem and out put the results the user needed. For a 40,000 degree of freedom model, it will take about 20 minutes to get the final result. Another modeling trend of the power package is to develop the advanced methodologies for the challenges due to the new development of power package in design and assembly. Examples are, as the die size and thickness shrink, die pick up process will become very critical, simulating this pick process is helpful to reduce die cracking [31]. Just as typical wafer level package, the power wafer level package needs to go through various reliability tests. Particularly EM in power WLCSP in both interconnect and solder balls will be a serious challenge as the pitch becomes small due to die shrinks. Modeling of EM can help and improve the design of the WLCSP. Simulation of 3D void generation has been developed in both interconnect and solder bumping level [32,33]. Fig. 21 shows the void generation simulation for the EM in a wafer level CSP. Passivation cracking modeling will help for the metal stacking and layout of passivation layer above the metal [34]. Moisture is a big impact to the power package at the wet environmental condition, a systematic modeling and analysis methodology for moisture and vapor pressure has been introduced in [35]. Cu-stud bumping in power wafer level CSP will induce the failure such as the silicon cratering and BPSG crack under the barrier layer. Devel-
Fig. 19. The diagram of the modeling in all areas of power semiconductor.
Fig. 21. EM void simulation [33].
Fig. 20. An example of thermal simulation automation.
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opment of 2D–3D dynamic solution for the Cu-stud bonding process can optimize the bumping parameters [36]. Drop test is always interested in and requested by the portable customers. There are a lot of studies towards the drop test modeling [37]. Power WLCSP will need fully simulation to pass the drop test requirement. There are several new studies that have paid attention to ionic polarization layers in polymer electrolytes [38] which could be potentially used for the contamination analysis of wafer level power package. Molecular dynamics approach [39] is a tool that can be used to study the structure–properties for power semiconductor wafer level package. 8. Conclusions The development of wafer level power package is closely related to the development of the power device. For discrete power device, the trends of power wafer level package are towards the smaller pitch, shrink die and package with high current carrying capability for the low voltage application. Moving the VDMOSFET drain to front side is a trend today, which allows the discrete power WL-CSP to be used in all the surface mount applications. The trends of power wafer level IC package are high power density at die level and small foot print. The trend of advanced wafer level power IC technology is the integrated solution which combines the BCDMOS and passives in wafer level. Wafer level passives can allow the power integration to obtain the switch high frequency from several MHz to 100 MHz. Most of the power SIP today is the structure with side by side die placement. This solution needs further improvement with electrical, thermal and mechanical performance like reducing parasitic inductance and warpage due to the large package size. Wafer level die side by side placement on a wafer/metal substrate is a solution which can improve the electrical and thermal performance. The trends of power SIP are towards the stacked die and 3D level for obtaining smaller package size while keeping the excellent electrical and thermal performance. Wafer level power CSP bumped on leadframe is an effective way for the power stacked SIP. Power 3D technology in wafer level is a future trend, major efforts may be focus on die to wafer and wafer to wafer stacking with TSVs. Approach for multiple direction heat transfer is the key technique for the power package design. As the power die and package shrink, larger amounts of co-design automation work are needed. Design and modeling automation is one of the major trends to reduce the cost and design cycles. At the same time, by means of modeling, some new fundamental mechanism of the power design will be found. The advanced modeling methodologies for the issues (like electronic migration, micro bumping, etc.) due to die and package size shrinkage need to be fully investigated and studied. New modeling methodologies and tools such as the molecular dynamics would be good approaches for the study of power wafer level packages. Acknowledgments The support from Fairchild Package Development, Automation Development and Fairchild Salt Lake are greatly appreciated. References [1] Liu Y, Irving S, Luk T, Kinzer D. Trends of power electronic packaging and modeling. In: EPTC 2008, Singapore; 2008. [2] Sanchez JL et al. Evolution of the classical functional integration towards a 3D heterogeneous functional integration. In: Proceedings of 14th international conference on MIXEDS, Ciechocinek, Poland; 2007. p. 23–34.
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[3] Lorenz L. Key power semiconductor devices and development trends. In: physics of semiconductor device. IWPSD 2007. p. 743–50. [4] Shen ZJ, Omura I. Power semiconductor device for hybrid, electric, and fuel cell vehicles. Proc IEEE 2007;95(4):778–89. [5] Emadi A, Lee YJ, Rajashekara K. Power electronics and motor drives in electric, hybrid electric and plug-in hybrid electric vehicles. IEEE Trans Indus Electron 2008;55(6):2237–45. [6] Caramel C et al. The Bi-IGBT: a low losses power structure by IGBT parallel association. Semicond Sci Technol 2008;23:1–8. [7] Millan J, Godignon P, Tournier D. Recent developments in SiC power device and related technology. In: Proceedings of 24th international conference on microelectronics; May 2004. p. 23–30. [8] Wolfgang E, Harder T. Power electronic technology roadmap – a bottom up approach. In: Proceedings of 5th international conference on integrated power electronics systems. Nuremberg, Germany; 2008. p. 315–7. [9] Bolannos MA. Semiconductor IC packaging technology challenges: the next five years. In: EMAP2005. [10] Desbiens D. Trends in power semiconductor packaging. In: Eurosime 2005, Berlin; 2005 [keynote]. [11] Zhang K. ENIAC and its strategic research agenda of more than Moore. In: Eurosime 2006, Italy [keynote]. [12] Cognetti C. Semiconductor packaging: present and future. In: Eurosime 2006, Italy [keynote]. [13] Wolf MJ, Reichl H. From microelectronic packaging to system integration. In: Eurosime 2007, London [keynote]. [14] Poupon G. SIP and 3D development. In: Eurosime 2007, London [keynote]. [15] Lee R. Development of wafer level packaging processes for 3D multi-flip chip stacking. In: IEEE ED society Maine chapter; 2006 [invited talk]. [16] Shimaamoto H. Technical trend of 3D chip stacked MCP/SIP. In: ECTC57 workshop; 2007. [17] Orii Y, Nishio T. Ultra thin pop technologies using 50 lm pitch flip chip C4 interconnection. In: ECTC57 workshop; 2007. [18] Meyer-Berg G. Future packaging trends. In: Eurosime 2008, Germany [keynote]. [19] Vardaman EJ. Trends in 3D packaging. In: ECTC 58 short course, 2008. [20] Fontanclli A. Sustem-in-package technology: opportunities and challenges. In: Proceedings of 9th international symposium on quality electronic design; 2008. p. 589–93. [21] Meyer T, Ofner G, Bradl S, et al. Embedded wafer level ball grid array (eWLB). In: EPTC 2008. p. 994–8. [22] Hashimoto T et al. System in package with mounted capacitor for reduced parasitic inductance in voltage regulators. In: Proceedings of the 20th international symposium on power semiconductor devices & ICs. Orlando, FL, May; 2008. p. 315–8. [23] ITRS. SIP white paper v9.0. The nest step in assembly and packaging: system level integration in the package (SIP); 2008. [24] Zhao M, Huang Z, Rena. Design of on-chip microchannel fluidic cooling structure. In: ECTC 2007, Reno, NV; 2007. p. 2017–23. [25] Prasher RS et al. Nano and micro technology-based next-generation packagelevel cooling solutions. Intel Technol 2005;9(4):285–96.. [26] Zhang Yuanxiang, Liang Lihua, et al. Highly efficiency modeling automation for electronic package thermal analysis. In: ECTC57, Reno, NV; 2007. [27] Xia YangJian, Zhang Yuanxiang, et al. Development of moisture automation analysis system for microelectronic packaging structures. In: ICEPT 9, Shanghai; 2008. [28] Wang Q, Ho I, Li M. Enhanced electrical and thermal properties of trench metal–oxide–semiconductor field-effect transistor built on copper substrate. IEEE Electron Dev Lett 2009;30:61–3. [29] Lee Fred. Survey of trends for integrated point-of-load converters. In: APEC 2009, Washington, DC; 2009. [30] Murugesan M et al. Cu lateral interconnects formed between 100 lm thick self-assembled chips. In: ECTC59, San Diego; 2009. p. 1496–501. [31] Liu Y. Modeling for assembly manufacture process. In: ICEPT 2006, Shanghai [keynote]. [32] Liu Y, Liang L, Irving S, Luk T. 3D modeling of electromigration combined with thermal–mechanical effect for IC device and package. Microelectron Reliab 2008;48:811–24. [33] Liu Y et al. A new prediction methodology for electromigration-induced solder degradation in a WL-CSP system. In: ECTC59, San Diego; 2009. p. 269–76. [34] Zhang Z, Suo Z, Liu Y. Methodology for avoidance of ratcheting-induced stable cracking (RISC) in microelectronic device. In: ECTC56; 2006. [35] Fan XJ. Moisture related reliability in electronic packaging. In: ECTC58 short course; 2008. [36] Liu Yumin, Liu Y, et al. Investigation of BPSG profile and FAB size on Cu stud bumping process by modeling and experiment. In: EuroSime2008, Germany. [37] Wong EH et al. Recent advances in drop-impact reliability. In: Eurosime 2008, Germany. [38] Biesheuvel PM. Ionic polarisation layers in polymer electrolytes. In: Eurosime 2008, Germany. [39] Wunderle B et al. Molecular dynamics approach to structure–property correlation in epoxy resins for thermo-mechanical lifetime modeling. In: ECTC59, San Diego; 2009. p 1404–13.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Trends of power semiconductor wafer level packaging Yong Liu * Fairchild Semiconductor Corp., South Portland, ME 04074, United States
a r t i c l e
i n f o
Article history: Received 18 June 2009 Received in revised form 25 August 2009 Available online 12 October 2009
a b s t r a c t A review of recent advances in power wafer level electronic packaging is presented based on the development of power device integration. The paper covers in more detail how advances in both semiconductor content and power advanced wafer level package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with next generation wafer level power packaging development, the role of modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of wafer level power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed. Ó 2009 Elsevier Ltd. All rights reserved.
1. Introduction Over the last two decades, power semiconductor technology has made impressive progress, particularly in the increasingly high power density of monolithic, system multiple function and hybrid designs [1–3], which are the driving forces towards both the monolithic package and three dimensional (3D) power solution with heterogeneous functional integration. The development of power packages depends on the development of power device integration. Current power devices include the power integrated circuit (IC)s, high voltage IC (HVIC), discrete metal oxide semiconductor field effect transistor (MOSFET), intelligent discrete power device, combined with functional integration and the integration of passive elements. Hybrid integration includes the standard power module and the intelligent power module (IPM) for high power application. Today’s power integration solution has covered multiple functions, which is one of major directions of power wafer level package development. The trends are going towards wafer level 3D heterogeneous integration with high switching frequency and with reduced or eliminated bulky magnetics and capacitances as well as soft switching technologies for high efficiency and low harmonics [3]. Silicon carbide (SiC) and other wide bandgap (WBG) semiconductor devices will ultimately be important elements for hybrid integration to advance system dynamic characteristics, overload capability, device ruggedness, and thermal and electrical performance [4–8].
* Tel.: +1 (207) 761 3155; fax: +1 (207) 761 6339. E-mail address: [email protected] 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2009.09.002
This paper introduces the power wafer level package trends based on above power device development. A review of recent advances in power wafer level electronic packaging which focuses on monolithic power integrations is presented. It covers in more detail how advances in both semiconductor content and advanced wafer level package design and the materials have co-enabled the significant advances in power device capability during recent years. Extrapolating the same trends in representative areas to the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power wafer level semiconductor solutions. Challenges of power wafer level semiconductor packaging in both next generation design and assembly process are presented and discussed. In addition to the forward looking trends it is important to recognize that the methods for concurrent engineering of these solutions (both the semiconductor content and high performance package capability) are becoming more increasingly dependent on rigorous use of proven multi-physics/FEA tools and techniques for both new power package development and its assembly process. The challenges for modeling of power semiconductor package in new package and assembly process are investigated and discussed.
2. Challenges of power wafer level semiconductor packaging Today, providing energy efficient solutions for various products is becoming increasingly important in our world due to limited energy resources and climate change. Especially significant is the fast growth of consumer electronics in both communications and entertainment, industrial power conversion, automotive, and
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standard power electronics products. Consumer demand for increased mobility with advanced features and for high efficiency energy solutions has paved the way for a variety of new products [9], and has driven advances in power electronics technology towards the high power density design of monolithic devices, discrete components and 3D heterogeneous wafer level solutions as well as the wafer level stacking with silicon through vias (TSV) [10]. As compared to the development in general IC package [11–19], the power wafer level package is far behind due to the extremely harsh operation environment. New modeling methodologies and tools are becoming necessary to support new generation power wafer level package development. This paper describes the challenges for today and the next few years in power wafer level package development which should be addressed by the industry. 2.1. Die shrinkage impact The development of power semiconductor device has begun to aim at 130 nm technology, while today 180 nm and 250 nm technologies is beginning to drive significant die size shrinkage as compared to regular 350 nm or 500 nm power technology. As the metal interconnect system inside the die continues to become thinner, current density has significantly increased. The electromigration (EM) issues will grow and new interconnect alternatives will be considered. Current techniques such as the wafer level solder bumping or Cu-stud bumping will meet the challenges of material inter metallic diffusion and mechanical cratering issue for wafer level Cu-stud bumping. As the die shrinks, the pitch of power wafer level chip scale packages (CSP) will move from current 0.5 mm towards 0.4 mm. The heat dissipation will become a very critical and significant challenge. Finding a high efficiency heat dissipation solution is necessary. 2.2. Wafer level power system on chip (SOC) vs. system in package (SIP) The power integration devices allows the state of art smart power IC with technology such as integration of bipolar, complementary metal oxide semiconductor (CMOS) and double diffused metal oxide semiconductor (DMOS)-BCDMOS, intelligent discrete power device, and the function integration in both lateral DMOS (LDMOS) and vertical DMOS (VDMOS) for power control and protection as well as other functions. This is so called power semiconductor system on chip (SOC), which is the integration of several heterogeneous technologies-analog, digital, MOSFETs, etc. into a single silicon chip. However, such power SOC technology often is too expensive and complex. This leads to a wealth of opportunities for system in package (SIP), in which multiple chips with different functions are placed in one package or module [20] which has similar function of SOC but with a lower cost. SIP has evolved as an alternative approach to SOC for electronics integration because this technology provides advantages over SOC in many market segments. In particular SIP provides more integration flexibility, faster time to market, lower research and development (R&D) or non-recurring engineering (NRE) cost, and lower product cost than SOC for many applications. SIP is not a replacement for high level, single chip, and silicon integration but should be viewed as complementary to SOC. For some very high volume applications SOC will be the preferred approach, like a power SOC with the integration of LDMOSFETs and IC controller, the cost of the SOC is not expensive due to larger volume of production as compared to the SIP with two MOSFET die and an IC controller die. In such case, the electric performance of the SOC is clearly super as compared to the SIP. Some complex SIP products will contain SOC components. Wafer level SIP/stack is one major direction for lower power application.
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As the die shrinks, SOC can add more functions, and SIP can include more chips. In SOC, the thermal density will become very high. Determining how to insulate different functions in one chip and how to effectively dissipate the heat through the package will be a challenge [21–25]. Although the cost of SIP is low, there are challenges due to the assembly of wafer level multiple chips to wafer. The internal parasitic effects of SIP, like parasitic inductance [22], are higher than SOC. The impact of heat from the power components on the electrical performance of IC drivers will be a concern. To build an advanced SIP which has good thermal and electrical performance with low cost is the largest challenge of power wafer level SIP. Modeling and simulation efforts must be used to support the SIP development from design, reliability and assembly process [26–36]. 2.3. New power package materials Development of new materials to support wafer level package process, heat transfer and good electrical performance is critical. An example is to develop new molding compound material with reasonable content of nano silica fillers to be suitable wafer level molding and to rapidly dissipate heat from the power die while keeping the adhesion strength high. At present, both Pb-free solders and green epoxy mold compound material (EMC) are used and accepted by most companies. Thermal stability is a key issue [9], especially in the automotive environment, where current epoxy mold compound materials have difficulties meeting the requirement of exceeding 180°C continuous operation. The new green EMC will have to withstand such temperatures from the power chip. Pb-free solder must have high melting temperatures and EMC should not be burnt in high temperature operation. As the chip shrinks, there are two trends in power packages. The first is the fan-in application for power wafer level packages, which are gaining wider applications without EMC. The second is the fanout wafer level package, which use the wafer level molding to make the interconnect re-distribution. This is particularly useful for the chip with smaller pitch and shrank die. For this latter trend, the EMC usage is not decreasing [18,21]. 3. Trends in discrete wafer level power MOSFET packages 3.1. Wafer level MOSFET compared to regular discrete power package Table 1 shows the typical development trends of discrete MOSFET package. It gives the representative power transistor package constituent volumetric percentages. As the package develops from Fairchild early DPak (TO252) through SO8 to MOSFET BGA and MOSFET WLCSP, the molding compound decreases as a percentage of volume, until it reaches zero with the MOSFET BGA and WLCSP packages. At the same time the silicon and interconnect metal increases as a percentage of volume. At DPAk level, leadframe is about 20% and silicon is about 4%, while EMC is about 75%. At WLCSP level, the silicon is about 82%. There is no EMC in the WL-CSP. Fig. 1 shows the discrete wafer level – CSP for schottky diode and vertical MOSFET from the released products of Vishay and Fairchild semiconductor. Those WL-CSPs are called fan-in layout. However, the advantage of EMC is that it can enhance handling and mechanical robustness, as it has in the past. It can provide substantial protection and mechanical integrity to place components across a wide generational range of pick and place equipment. So the EMC today in discrete power package is still useful as a component ‘‘encapsulant”. For wafer level power package, the EMC can be used as the re-distribution layer (fan-out) material through the molding for the fan-out wafer level package. That allows for the
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Table 1 Typical discrete power package constituent volumetric percentages towards WL-CSP [1]. Package type
Total volume (mm3)
Approximately % EMC
Approximately % silicon
Approximately % leadframe
Approximately % interconnect
TO-252 (wire) SO8 (wire) SO8 (clip) MOSFET BGA WL-CSP
90 28 28 20 20
75 83 70 0 0
4 6 6 40 82
20 10 20 50 0
1 1 2 10 18
Fig. 3. Trends of low power package development.
Fig. 1. Examples of discrete WL-CSP.
larger pitch for a smaller shrank die. Fig. 2 gives the example of fan-out structure by using wafer level epoxy molding technology. 3.2. Higher current carrying capability One trend of the discrete wafer level power package is to increase the current carrying capability per unit area; this is partly due to the customer’s request for high current capability and partly due to the die shrinkage. Fig. 3 shows the trends of low power MOSFET package development in the industry, the data was selected from the released products of Vishay, IR and Fairchild Semiconductor, which includes both wafer level power discrete package and regular power discrete package. To better manage the thermal performance with the trend to higher current carrying capability in wafer level power package,
Fig. 2. EMC as the re-distribution substrate of fan-out wafer level package in Infineon [21].
there are two approaches: one is to intensify the thermal management requirements from the print circuit board (PCB) level and the other is heat dissipation in multiple directions at the package level which is advantageous for wafer level discrete power packages. Bonding the wafer level power discrete package to a metal frame is an effective approach. Bonding die to metal wafer with preetched cavity is the wafer level process to get the wafer level package with multiple direction heat dissipation. Fig. 4 shows the examples of multiple direction heat transfer of Fairchild MOSFET BGA and Vishay PolarPAK.
3.3. Low Rdson resistance and better thermal performance To get lower Rdson and to improve the thermal performance, the wafer level MOSFET with vertical metal-oxide can be built on a silicon substrate thinned to 7 lm and plated with 50 lm copper
Fig. 4. Multiple direction heat transfer packages.
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Fig. 5. (a) Fairchild UMOSFET and (b) regular MOSFET [28].
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Fig. 7. Wafer level integrated power solution.
and ‘‘adaptive” motion control at the high end. For the voltage range at 100–700 V, next generation of integrated LDMOS structures reach the limits of Si for breakdown voltage (BVdss) as a function of geometry, which allows a corresponding increase in HV monolithic power conversion capability (AC–DC) and results in an incremental raising of the limit at which multiple die are requested in the actual products. 4.2. Smaller package footprints
as its drain, see Ref. [28] Fairchild wafer level UMSFET. This extremely reduces the Rdson resistance and improves the thermal performance. Fig. 5 shows the internal device structure of the UMOSFET and its comparison with regular MOSFET.
As power die size shrinks, the package footprints shrink as well, and maintaining the thermal transfer capacity at the package level is difficult since the function/unit area of die is increasing with advanced BCDMOS processes. While the overall package footprint trend is decreasing area, the thermal dissipation capabilities rely more on the PCB as part of the system. Therefore insuring mechanical integrity of WL-CSP in the form of bare flipped die in conjunction with board level assembly of a heat sink is difficult, see Fig. 8.
3.4. Move the MOSFET drain to front side
4.3. Wafer level micro-channel
For the wafer level discrete MOSFET, another trend which obtains the attention in the industry is to move the drain of the MOSFET to the front side of the die so that the drain, source and gate are at the same side. This would be helpful for the surface mounting application in various PCBs. Fig. 6 shows one of the lateral layouts of the drain for a LDMOS WL-CSP. Since the drain is in lateral placement, the back metal does not contact the drain directly, so its application limits to lower power and lower voltage area. For VDMOS WL-CSP, the trend is to develop the directly connection to the front side by TSV in trench area. The advantage of the direct connection the back drain to front side is its good electrical performance with lower Rdson. Because this is a vertical DMOS, the application area may be relative wider in power range as compared to the structure in Fig. 6.
Instead of air cooling for power wafer level package, one trend is to build the wafer level micro-channel on power chip. This can effectively take the heat out of the power chip. Fig. 9 gives an example of building the micro-channels on both power die active surface and back side. Due to the high efficiency of cooling through the micro-channels, heat sink is not needed anymore. This may significantly reduce the space of heat sink and remove the noise induced by the fans in the cooling system.
Fig. 6. Move the drain to the front side the MOSFET.
4. Trends in power IC packages Fig. 8. Example of WL-CSP which is hard to mount the heat sink.
4.1. Higher power density at the wafer level For the voltage range at 5–100 V, there are a wider range of inductive loads handled with a monolithic solution and higher level of functional integration in monolithic solution. The most interesting application is the wafer level integrated system power conversion solution which combines two power switches (the high side and lower side) together with an IC driver. Fig. 7 shows an example of such a wafer level power system on chip. There are also integrated advanced digital control functions for motion which includes ‘‘sensorless” positioning and fault detection at the low end
Fig. 9. Micro-channels on both active side and back side die [24].
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5. Trends in wafer level passives Although the wafer level passives (resistor, capacitor and inductor) in today are only suitable for very low and tiny power, it is possible for them to integrate with low power BCDMOS or other active IC. Integration of active power switches and passives in wafer level can greatly improve the electrical performance and significantly reduce the parasitic effects. For relative larger power products, like buck converter and DrMos with passives, the development is on going. Fig. 10 gives the development samples of wafer level inductors for power application [29], which indicates the current level with frequency. One significant advantage of the wafer level inductor integration is its frequency can reach from several MHz to 100 MHz, which the regular package level and board integration level are hard to get. 6. Trends in power SIP/3D development In many power conversion and power management applications, the optimized semiconductor solution is a combination of lateral and vertical conduction devices. This makes a monolithic silicon solution with both power switching (VDMOS/IGBT) and control function (BCDMOS/CMOS IC) impractical. Therefore the Power SIP becomes necessary. Currently there are two major trends in power SIP/3D package development: one is the wafer level CSP bumping on the leadframe to form various stacked die power package; another one is the fully wafer level 3D package with TSV.
Current flows across the front side of the die. The die is attached to the substrate by insulating die attach material. Fig. 12 shows a wafer level side by side placement SIP, a new concept of lateral interconnects is proposed for control and communication between die [30]. This concept may be used for the system power solution with side by side die placement. In power application, the value of ‘‘SIP” is directly related to reducing board level design complexity and space for power delivery and control and also related to providing reduced parasitic effects in high performance switching applications. One application of the power SIP is to expand ease of point of load (POL) power regulation and management. As an example of the POL, Fig. 13 shows a MOSFET SIP with a high side WL-CSP and a low side WL-CSP bumped on a metal substrate for a buck converter. Fig. 14 shows the profile of power efficiency (%) vs. current load of the SIP. It can be seen from the profile that the average efficiency of the SIP is about 2–5% higher than the individual MOSFETs. 6.2. Stacked/3D power SIP The above SIP with side by side placed dice has certain drawbacks: its geometry size is not as small as desired, and the electrical performance such as the parasitic effect also needs further improvement. Ref. [22] discussed a regular SIP (not a wafer level)
6.1. Side by side placed multiple die SIP The SIP as defined here contains at least two die in a package as shown in Fig. 11. One die is the VDMOS, which is attached to a wafer level metal substrate by a conductive die attach. The current flows through die and the metal layer. Another die is the driver IC which uses lateral electric conduction with substrate grounded.
Fig. 12. A wafer level side by side SIP with lateral interconnects [30].
Fig. 10. Wafer level passives [29].
Fig. 11. A two die power SIP.
Fig. 13. A SIP of buck converter.
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Fig. 16. A two phase buck converter SIP with wafer level power CSP bumped on leadframe.
Fig. 14. Power efficiency (%) vs. current load (I).
of a voltage regulator with component side by side placement and the stacked SIP and found that the stacked SIP has 55% lower parasitic inductance than side by side placed SIP. This is particularly important for portable applications, and for small size industry applications. 6.2.1. Power discrete WL-CSP bumped on leadframe The trend of stacked power package is from simply enhancing one function towards systematic function and multiple functions while reducing the board level complexity and space. Fig. 15 shows a two phase buck converter circuitry. Fig. 16 shows a stacked SIP for a two phase buck regulator, which is built by four single wafer level discrete power CSPs bumped on leadframe and encapsulated with mold. Such a SIP has inherent advantages of load splitting and output ripple dividing over its single-phase counterpart and is a suitable candidate in many applications, given the trends towards lower supply voltages and greater load–current requirements with low cost. The bottom exposed drains and top exposed source provide the two way heat dissipation for a better thermal performance. 6.2.2. Wafer level stack/3D power die SIP There are two stacking wafer level methods for power die SIP. One is to stack die on the wafer and the other is to stack two wafers. Fig. 17 shows the active IC die is stacked on the passive wafer. The power IC die with two MOSFETs and a IC driver is bonded on the passive wafer with inductor L. Fig. 18 shows an example of a wafer level stacked die package of two MOSFETs bonded together
Fig. 17. Stacked active die on passive wafer [29].
Fig. 18. Wafer level stacked power die package with TSVs by two stacked wafers.
with wafer 1 source and wafer 2 drain. The common source (wafer 1)/drain (wafer 2) may be connected to at least one front side by TSVs. This stacking process can be done through wafer on wafer. The advantage of this integration is the very good electrical performance for a half bridge with both N channel or P channel MOSFETs for products like liquid crystal display (LCD) back light inverters. Since the distance between high side die and low side die is very short, this greatly reduces the electrical resistance and parasitic effects. 7. Trends in power package modeling
Fig. 15. A typical two phase buck converter circuitry.
The power package development today is becoming increasingly dependent on rigorous use of proven multi-physics/FEA tools and techniques. Correct use of the modeling tools can definitely save design time and shorten the number of design cycles. The challenge is, can the modeling tool and methodology be ready to support the new trends in the development of new wafer level power package technology? Examples of the challenges include various designs, reliability and assembly modeling which include EM simulation; diffusion along the interface of two metal materials; contamination at the interface between different material layers; thermal resistance definition in SIP; 3D copper stud bumping simulation, etc.
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The greatest challenges in modeling for wafer level power packages today are the multi-physics and multi-scale simulations which couple the electrical, thermal and mechanical fields, and the assembly process simulation in a wafer level power package system with multi-scale layout from nanometers to millimeters. Development of highly efficient modeling algorithms for such a power WLP system is very critical for virtual prototyping of new products. In some cases, the WLP might have strong thermomechanical performance but is weak in electrical function or the WLP has very good electrical performance but is weak in thermomechanical design. Therefore it is necessary to determine the best solution using modeling in design phase. Package measurements are expensive, time consuming, and cannot provide all of the required information. ITRS SIP 2008 white paper [23] describes a future vision of chippackage system co-design: (a) One tool for simultaneous design enabled by a multi-user, cross-functional EDA + system analysis + knowledge-based tool. (b) A wizard-like interface, automatically constructs baseline design for each component based on series of user questions, analysis and an expert system for technology selection and design rules. These ideas cover stress/mechanical modeling, thermal chip-package system and electrical chip-package system. This indicates a modeling trend of the industry is towards package system design automation. Fig. 19 shows the modeling role in all areas of the semiconductor power industry from wafer IC design to final product. One of the major modeling tools for packages is finite element analysis (FEA). Advances in the power package development need the high efficiency, and short design cycles, in which the FEA use will accelerate the further miniaturization of power electronic components, and accelerate the incorporation of advanced materials and assembly structures. However, most of the power package design engineers, material engineers, test engineers and the reliability analysis engineers are not familiar with FEA. If they can run designed experiments using FEA for their product optimization in co-designed power package efforts and for material selection, that will really accelerate the power package development. Therefore, to develop the modeling automation system is one trend of the power package modeling. This system allows people who might not know FEA but wish to do design optimization for their product to run FEA. Engineers just simply input some basic information and set the numerical design of experiment (DOE), the system will automatically do the meshing, apply boundary conditions and loads, solving and automatically output the results. Refs. [26] and [27] have developed the initial modeling automation system for thermal, moisture and linear thermal–mechanical stress analysis. The results have shown great efficiency to save modeling time.
Fig. 20 shows an example of thermal simulation automation. The user only needs to input the basic information, load the sold model from computer aided design (CAD) Lib, choose the power applied, natural convention or forced convention, and then click the button ‘‘solve”, the automation system will automatically mesh the model, apply the power and thermal boundary condition, and solve the problem and out put the results the user needed. For a 40,000 degree of freedom model, it will take about 20 minutes to get the final result. Another modeling trend of the power package is to develop the advanced methodologies for the challenges due to the new development of power package in design and assembly. Examples are, as the die size and thickness shrink, die pick up process will become very critical, simulating this pick process is helpful to reduce die cracking [31]. Just as typical wafer level package, the power wafer level package needs to go through various reliability tests. Particularly EM in power WLCSP in both interconnect and solder balls will be a serious challenge as the pitch becomes small due to die shrinks. Modeling of EM can help and improve the design of the WLCSP. Simulation of 3D void generation has been developed in both interconnect and solder bumping level [32,33]. Fig. 21 shows the void generation simulation for the EM in a wafer level CSP. Passivation cracking modeling will help for the metal stacking and layout of passivation layer above the metal [34]. Moisture is a big impact to the power package at the wet environmental condition, a systematic modeling and analysis methodology for moisture and vapor pressure has been introduced in [35]. Cu-stud bumping in power wafer level CSP will induce the failure such as the silicon cratering and BPSG crack under the barrier layer. Devel-
Fig. 19. The diagram of the modeling in all areas of power semiconductor.
Fig. 21. EM void simulation [33].
Fig. 20. An example of thermal simulation automation.
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opment of 2D–3D dynamic solution for the Cu-stud bonding process can optimize the bumping parameters [36]. Drop test is always interested in and requested by the portable customers. There are a lot of studies towards the drop test modeling [37]. Power WLCSP will need fully simulation to pass the drop test requirement. There are several new studies that have paid attention to ionic polarization layers in polymer electrolytes [38] which could be potentially used for the contamination analysis of wafer level power package. Molecular dynamics approach [39] is a tool that can be used to study the structure–properties for power semiconductor wafer level package. 8. Conclusions The development of wafer level power package is closely related to the development of the power device. For discrete power device, the trends of power wafer level package are towards the smaller pitch, shrink die and package with high current carrying capability for the low voltage application. Moving the VDMOSFET drain to front side is a trend today, which allows the discrete power WL-CSP to be used in all the surface mount applications. The trends of power wafer level IC package are high power density at die level and small foot print. The trend of advanced wafer level power IC technology is the integrated solution which combines the BCDMOS and passives in wafer level. Wafer level passives can allow the power integration to obtain the switch high frequency from several MHz to 100 MHz. Most of the power SIP today is the structure with side by side die placement. This solution needs further improvement with electrical, thermal and mechanical performance like reducing parasitic inductance and warpage due to the large package size. Wafer level die side by side placement on a wafer/metal substrate is a solution which can improve the electrical and thermal performance. The trends of power SIP are towards the stacked die and 3D level for obtaining smaller package size while keeping the excellent electrical and thermal performance. Wafer level power CSP bumped on leadframe is an effective way for the power stacked SIP. Power 3D technology in wafer level is a future trend, major efforts may be focus on die to wafer and wafer to wafer stacking with TSVs. Approach for multiple direction heat transfer is the key technique for the power package design. As the power die and package shrink, larger amounts of co-design automation work are needed. Design and modeling automation is one of the major trends to reduce the cost and design cycles. At the same time, by means of modeling, some new fundamental mechanism of the power design will be found. The advanced modeling methodologies for the issues (like electronic migration, micro bumping, etc.) due to die and package size shrinkage need to be fully investigated and studied. New modeling methodologies and tools such as the molecular dynamics would be good approaches for the study of power wafer level packages. Acknowledgments The support from Fairchild Package Development, Automation Development and Fairchild Salt Lake are greatly appreciated. References [1] Liu Y, Irving S, Luk T, Kinzer D. Trends of power electronic packaging and modeling. In: EPTC 2008, Singapore; 2008. [2] Sanchez JL et al. Evolution of the classical functional integration towards a 3D heterogeneous functional integration. In: Proceedings of 14th international conference on MIXEDS, Ciechocinek, Poland; 2007. p. 23–34.
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