Tri-gate heterojunction SOI Ge-FinFETs

Accepted Manuscript Tri-gate heterojunction SOI Ge-FinFETs Rajashree Das, Rupam Goswami, Srimanta Baishya

PII:

S0749-6036(15)30341-4

DOI:

10.1016/j.spmi.2015.12.039

Reference:

YSPMI 4130

To appear in:

Superlattices and Microstructures

Received Date: 8 November 2015 Accepted Date: 24 December 2015

Please cite this article as: R. Das, R. Goswami, S. Baishya, Tri-gate heterojunction SOI Ge-FinFETs, Superlattices and Microstructures (2016), doi: 10.1016/j.spmi.2015.12.039. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

ACCEPTED MANUSCRIPT

Tri-gate heterojunction SOI Ge-FinFETs

RI PT

*Rajashree Das, Rupam Goswami and Srimanta Baishya *Department of Electronics & Communication Engineering, National Institute of Technology Silchar, Assam: 788010 E-mail: [email protected]

TE D

M AN U

SC

Abstract: This paper proposes structures of tri-gate heterojunction (HJ) FinFETs with different configuration of gate dielectric and gate material stacks: Single Gate Material Single Dielectric (SGMSD), Single Gate Material Dual Dielectric (SGMDD) and Dual Gate Material Dual Dielectric (DGMDD), and compares their characteristics with conventional FinFET. The heterojunction formed between the Germanium (fin) and Silicon layer (at source/channel or drain/channel junction) is found to produce low leakage current than conventional FinFET, the best being obtained for DGMDDHJ FinFET. Since the highest onoff current ratio is obtained for DGMDDHJ FinFET, so, further analysis is done for DGMDDHJ FinFET for various parameters like length of the Silicon layer, doping concentration of the Silicon layer and fin widths, considering two cases of position of the Silicon layer, one at source end and the other at drain end. The Subthreshold Swing reduces as fin width is increased. Interestingly, when the Silicon layer is at the drain end, the transfer characteristics are almost similar for variation in length and doping concentration of the Silicon layer. The DGMDDHJ FinFET is found to exhibit low DIBL, thus proving its superiority over MOSFETs. Keywords: heterojunction; Single Gate Material Dual Dielectric FinFET; Dual Gate Material Dual Dielectric FinFET; DIBL 1. Introduction

AC C

EP

Due to downscaling of device dimensions, the performance of MOSFETs has degraded owing to the various short channel effects [1-3] and corner effects. Reduction in thickness of gate oxide results in high drain leakage current, high direct tunneling gate leakage current, increase in Polysilicon gate depletion, and gate dopant penetration into the channel region [4]. In order to sustain the commercial demand of semiconductors according to the Moore’s Law [5], a number of novel devices have been looked out for. Such a device which can limit the drawbacks of scaling in MOSFET is the tri-gate FinFET or simply, FinFET [6]. FinFETs are the propitious alternative to planar MOSFET devices, since the channel is controlled by the gate from all three sides [7]. The characteristics of the device are dependent on the dimensions of the fin such as fin width and fin height apart from other obvious specifications (doping concentration of channel, gate length and insulator thickness) as in MOSFETs. Due to the presence of fin-shaped body, a Subthreshold Swing (SS) closer to the kT/q limit is achievable in FinFET than in MOSFET. Short Channel Effects like DIBL is also much reduced. To further improve the functionality of FinFET, various structures such as DG FinFET [811], TG FinFET [8-9], GAA FinFET [8-9], tapered FinFET structure [12], the dual material

ACCEPTED MANUSCRIPT

SC

RI PT

gate FinFET [13], halo implant for nanoscale MuGFETs [14], omega-shaped-gate nanowire FinFET [15] , pie gate bulk FinFET [16], cylindrical FinFET [17], and SOI FinFET [18] have been proposed. This work proposes for the first time a set of three heterojunction FinFETs, each modified in its structure by altering the configuration of the gate dielectric stack and gate material stack of the device. Use of low-k dielectric materials as gate insulators reduces efficiency of a FinFET in terms of current, threshold voltage and Subthreshold Swing; so high-k gate dielectric materials are much preferred with proper optimizations. A gate material of high work function causes low on current and high threshold voltage, making it unsuited for low power applications. This can, however, be resolved by replacing Polysilicon by thermally stable and low work function metal gates [19]. Section 2 describes the structural description of four different structures with doping specifications. The simulation set up is mentioned in section 3 and the results of comparisons of four different structures are shown, and discussed in section 4. Section 5 concludes the work.

M AN U

2. Device architectures

AC C

EP

TE D

Figure 1 shows the four different structures of FinFET considered in this paper. Here, the first structure is a conventional SOI FinFET. The second structure is the Single Gate Material Single Dielectric Heterojunction FinFET (SGMSDHJ FinFET). The other two different structures are Single Gate Material Dual Dielectric Heterojunction FinFET (SGMDDHJ FinFET) and Dual Gate Material Dual Dielectric Heterojunction FinFET (DGMDDHJ FinFET). The heterojunction structures have a Ge-Si-Ge body where a Silicon region is placed at the source-channel junction as evident from Figure 1. The dimensions of the various structures are listed in Table 1. The orientation of the axes and origin, O (0,0,0) for all the structures is depicted in Figure 1 (a). The dimensions for all the structures is shown in Figure 1 (d) as it is the ultimate modified structure with maximum parameters. The gate length for single gate material or single gate dielectric structures can be derived from Figure 1 (d) by adding the lengths, B and C. For the single gate material structures, Polysilicon serves as the gate material and for single gate dielectric structures, HfO2 is the oxide used. In the dual dielectric structures, SiO2 and HfO2 are laterally placed, having a length of 30 nm and 10 nm respectively. In Dual Gate Material structures, Polysilicon and Aluminum are used as two different gate materials each with a length of 30 nm and 10 nm respectively. The source and drain are each 5 nm long, which are not mentioned in Table 1. The n+ source and n+ drain are doped with 1× 1020 cm-3 each, channel with 1×1019 cm-3 and Silicon with 1×1019 cm-3.

TE D

M AN U

(a)

SC

RI PT

ACCEPTED MANUSCRIPT

AC C

EP

(b)

(c)

SC

RI PT

ACCEPTED MANUSCRIPT

(d)

M AN U

Figure 1. Cross sections of the devices (left: top view and right: front view) of (a) Conventional FinFET, (b) SGMSDHJ FinFET, (c) SGMDDHJ FinFET and (d) DGMDDHJ FinFET Table 1. Dimensions of Figure 1 (d)

Value (nm)

A

10

B

30

C

10

D

6

E

5

F

60

G

20

H

8

I

22

J

31

AC C

EP

TE D

Parameter

3. Simulation Setup

The simulation results of the four different 3-D tri-gate FinFETs have been extracted from Synopsys TCAD [20]. Fermi Dirac Statistics has been switched on to account for accurate distribution of carriers [20]. Since regions of high doping concentration are present in the devices, Bandgap Narrowing Model has been enabled [20]. The higher doping concentration lowers the mobility of carriers which results in lower on current of the device. Therefore, to consider the effect of mobility of the carriers the Doping Dependent Mobility Model has also been used [20].

ACCEPTED MANUSCRIPT 4. Results and Discussions 4. 1. Comparison of transfer characteristics of the proposed Heterojunction FinFETs and conventional FinFET

EP

TE D

M AN U

SC

RI PT

Figure 2 shows the transfer characteristics of the heterojunction FinFETs and conventional FinFET, and Table 2 lists the various parameters extracted from Figure 2. As the structure transforms from conventional FinFET to its heterojunction forms (Single Gate Material Single Dielectric, Single Gate Material Dual Dielectric and Dual Gate Material Dual Dielectric), the on current decreases whereas the off current reduces considerably. However, the change in off current is higher than that in on current. This is the reason why the Ion/Ioff increases in the order: Conventional FinFET, SGMSDHJ, SGMDDHJ and DGMDDHJ FinFETs. The Subthreshold Swing is found to be more for SGMDDHJ FinFET as compared to SGMSDHJ FinFET, but decreases again for DGMDDHJ FinFET. This can be qualitatively explained with the aid of Figure 2 (c). For conventional FinFET and SGMSDHJ FinFET, the SS is almost same due to the same configuration of their gate dielectric and gate material stacks. The structure of SGMDDHJ FinFET is achieved by replacing 30 nm of HfO2 (high-k) in SGMSDHJ FinFET with SiO2 (low-k) (indicated with dashed arrow). As a result, the region in the channel which was previously under the influence of a high-k dielectric is now under that of a low-k dielectric. So, the SS increases due to poorer action of the gate. Further, the structure of DGMDDHJ FinFET is achieved by replacing 10 nm of Polysilicon (high work function) with Aluminum (low work function) (indicated by dashed arrow). The presence of low work function in the portion previously occupied a high work function material increases the influence of the gate on the channel and hence the SS decreases again. The surface potential and electron mobility along the device lengths of SGMSDHJ, SGMDDHJ and DGMDDHJ FinFETs are shown in the Figure 3 and Figure 4. For DGMDDHJ FinFET, the potential is lower at the source end, and higher towards the drain end when compared to SGMSDHJ FinFET. As one moves from source to drain, the source end consists of a gate oxide with low dielectric constant (k = 3.9) and a gate material with high work function ( Φm = 4.25 eV), whereas the drain end consists of a gate oxide with high

AC C

dielectric constant (k=22) and a gate material with low work function ( Φm = 4.1 eV). For SGMDDHJ FinFET, the plot at the source end is exactly similar to that of DGMDDHJ due to the presence of same gate dielectric and gate material at that end. For the drain end, the gate material in DGMDDHJ FinFET changes from Polysilicon to Aluminum which is why the surface potential of SGMDDHJ FinFET reduces slightly at the drain end thus portraying the effect of the presence of a low work function metal. This is the reason why both the plots of surface potential cross at the position in the channel where the two gate dielectrics and gate materials meet. Similar conclusion can be derived from the plot of electron mobility of Figure 4. As evident from the plot, the mobility remains high for SGMSDHJ FinFET throughout the device structure from source to drain. Due to the presence of high work function material and low-k dielectric at source end in both SGMDDHJ and DGMDDHJ FinFETs, the electron mobility is quite reduced. This is the reason why the on current in SGMSDHJ FinFET is higher than the

ACCEPTED MANUSCRIPT other two structures. Both SGMSDHJ FinFET and DGMDDHJ FinFET exhibit similar on currents which can be deduced from their almost similar values of electron mobility and electrostatic potential. Transconductance is an important parameter in FinFETs [21]. It is defined as ∂I D ∂VGS

(1)

RI PT

gm =

AC C

EP

TE D

M AN U

SC

where ID is the drain current and VGS is the applied gate voltage. Transconductance gives a measure of how the drain current changes with the change in gate voltage, which is considered an essential design metric for circuit applications. gm/ID is a direct measure of a FinFET’s efficiency because it represents the amplification of the device (gm) per unit energy required to achieve it (ID) [21]. Higher the value of gm/ID, better is the ability of the FinFET to act as a potential energy saving device. Figure 2 (b) shows the plot of transconductance versus gate voltage for the four structures. Due to a smoother trend, the plots of transconductance follow the plots of the respective drain currents of Figure 2 (a). The conventional FinFET shows the highest transconductance among all. However among the proposed HJ FinFETs, SGMSDHJ FinFET proves to be the most efficient followed by SGMDDHJ and DGMDDHJ FinFETs.

(a)

M AN U

SC

RI PT

ACCEPTED MANUSCRIPT

AC C

EP

TE D

(b)

(c)

Figure 2. Comparison of (a) transfer characteristics of the four structures, and (b) transconductance versus gate voltage of the four structures; (c) Qualitative explanation of the nature of SS of transfer characteristics of (a)

ACCEPTED MANUSCRIPT

TE D

M AN U

SC

RI PT

Table 2: Comparison of on current, off current and ratio of on and off drain currents and SS for four different structures when the Silicon layer in the HJ FinFETs is at source end Structure Ion (A) Ioff (A) Ion/Ioff SS (mV/dec) -3 -10 6 Conventional FinFET 1.3×10 1.9 ×10 6.8×10 61.997 -12 −3 8 9.97 ×10 62.11 SGMSDHJ FinFET 1.21× 10 1.21 × 10 −4 −13 8 SGMDDHJ FinFET 89.72 2.41 × 10 8.32 × 10 2.89 × 10 −4 −13 8 76.36 DGMDDHJ FinFET 2.38 × 10 5.76 × 10 4.13 × 10

AC C

EP

Figure 3. Electrostatic potential in the heterojunction FinFETs versus position from source to drain (y= - 20 nm, x=30 nm)

Figure 4. Electron mobility in the heterojunction FinFETs versus the position from source to drain (y= - 20 nm, x=30 nm)

ACCEPTED MANUSCRIPT It is observed that DGMDDHJ FinFET is the best of all the four structures including conventional FinFET due to its low off current and high Ion/Ioff ratio. So, sections 4.2 and 4.3 discuss the results for various parameters taking DGMDDHJ FinFET as the device of interest. The sets of results are presented for two cases: one, when the Silicon layer forming the heterojunction is at the source end, and other, when it is at drain end.

4.2.1. Variation in length of the Silicon layer

RI PT

4. 2. Effect of doping and structural specifications on transfer characteristics of DMGDDHJ FinFET when the Silicon layer is at source end

AC C

EP

TE D

M AN U

SC

It is observed that with the increase in length of Silicon layer present at the source-channel interface, the drain current reduces as in Figure 5 (a). This is due to the presence of Silicon that possesses a comparatively higher band gap (~1.12 eV) than Germanium (~0.66 eV). As a result, electrons see a high energy barrier when they move from source to drain. This is pictorially represented in the energy band diagrams in Figure 5 (b). More the length of the Silayer more is the length for which the high energy barrier exists. So at a particular gate voltage, the drain current is reduced.

M AN U

SC

RI PT

ACCEPTED MANUSCRIPT

AC C

EP

TE D

(a)

(b) Figure 5. (a) Transfer characteristics for lengths of Silicon layer and (b) Energy band diagram for two lengths of Silicon layer (source end) 1 nm and 5 nm (y= - 20 nm, x=30 nm), explaining the drop in drain current 4.2.2. Variation in doping concentration of the Silicon layer

It is observed from the Figure 6 that with the increase in concentration of the Si-layer, the drain current reduces. However, the plots for concentration 1015, 1016 and 1017 cm-3 are almost similar. Increasing the concentration beyond 1017 cm-3 distinguishably reduces the

ACCEPTED MANUSCRIPT

M AN U

SC

RI PT

drain current. The Silicon layer being a part of the channel, increasing its p-type concentration reduces the number of electrons that can populate the surface to cause inversion. Moreover, the simulation also takes into account, the Band-gap Narrowing model which is significant for concentration equal to 1018 cm-3 and above. This is an additional factor why the plots of 1015 cm-3, 1016 cm-3 and 1017 cm-3 are superimposing.

TE D

Figure 6. Transfer characteristics of DGMDDHJ for different doping concentration of the Silicon layer 4.2.3. Variation in fin width

AC C

EP

As shown in Figure 7 (a), the drain current reduces with the increase in fin width in DMGDDHJ FinFET. The on and off currents are of the same order of magnitude but a significant difference in drain current is observed in the subthreshold region of operation. This is supported with the curves of electrostatic potential versus position for different fin widths as shown in Figure 7 (b), plotted at gate voltage 0.7 V where a significant change in drain current is observed. It is seen that the potential decreases in the channel with the increase in fin width. This means that the control of gate on the channel reduces. This is further explained with the concept of distance of a point in the fin from the triple gates in Figure 7 (c), which illustrates how a point in the mid-channel position is affected by the increase in fin widths. In Figure 7 (c), when the fin width is initially W, then the distances of the point P located in the middle of the channel from the three gates are given by AP, B1P and C1P respectively, where

B1P = C1P = W / 2

(2)

When the width is increased by an amount ∆ , then the distances of the same point P in the middle of the channel from its left and right gate sidewalls change to B2P and C2P, whereas its distance from the top gate remains same as before, that is, AP. Now,

ACCEPTED MANUSCRIPT B2P = C 2P = W / 2 + ∆ / 2

(3)

M AN U

SC

RI PT

The influence of the side gates on P reduces as the fin width increases, thus lowering the electrostatic potential in the region, and causing low drain current. This is a reason why with the increase of fin width in DMGDDHJ FinFET, Subthreshold Swing increases.

AC C

EP

TE D

(a)

(b)

M AN U

SC

RI PT

ACCEPTED MANUSCRIPT

(c) Figure 7. (a) Transfer characteristics of DGMDDHJ FinFET for different fin widths, (b) Electrostatic potential for different fin widths explaining the reduction in drain current at mid-gate voltage 0.7 V, (c) Concept of distance of a point in the channel from the three gates, further explaining the drop in potential at mid-gate voltage values

Ion(A) 2.39 × 10 −4 2.17 × 10−4 1.8 × 10−4 1.51× 10−4 1.43 × 10−4

:

AC C

EP

Fin Widths(nm) 10 12 14 16 18

TE D

Table 3 : Comparison of on drain current (Ion), off drain current (Ioff), on off drain current ratios(Ion/Ioff), subthreshold slope (SS) of varying fin widths of DGMDDHJ FinFET having Silicon layer in source side Ioff(A) 5.77 × 10 −13 6.20 × 10 −13 6.27 × 10−13 6.86 × 10 −13 6.84 × 10 −13

Ion/Ioff 4.13 × 108 3.50 × 108 2.87 × 108 2.2 × 108 2.08 × 108

SS(mV/dec) 76.36 79.82 91.65 99.96 102.22

4. 3. Effect of doping and structural specifications on transfer characteristics of DGMDDHJ FinFET when the Silicon layer is at drain end

It is observed from Figure 8 (a) that the drain current is independent of the length of the Silayer at the drain end. This can be explained from the energy band diagram of the device. The electrons at the source end see a similar barrier for all the lengths of Si-layer. The combined effect of gate and drain voltages suppresses the high energy barrier of Silicon at the drain end, thus maintaining an energy barrier which is almost similar to one another. This results in almost equal drain current for all the lengths. Similarly, the change in doping concentration of the Silicon layer at the drain end does not affect the transfer characteristics of the device as evident from Figure 8 (b). This concludes

ACCEPTED MANUSCRIPT

M AN U

SC

RI PT

that the device remains unaffected by the position of the Silicon layer at the drain end as far as its length and doping concentration are concerned. The transfer characteristics for different fin widths are depicted in Figure 8 (c). With the increase in fin width, the SS reduces as in the case of the Silicon layer at source end of Figure 7.

AC C

EP

TE D

(a)

(b)

M AN U

SC

RI PT

ACCEPTED MANUSCRIPT

AC C

EP

TE D

(c)

(d)

Figure 8. Transfer characteristics of DGMDDHJ FinFET when the Si-layer is at the drain end for: (a) different lengths of the Si-layer, (b) different doping concentrations of the Silayer, and (c) different fin widths; (d) Energy band diagrams versus position across the device for different lengths of the Si-layer (drain end)

ACCEPTED MANUSCRIPT Table 4: Comparison of on drain current (Ion), off drain current (Ioff), on off drain current ratios(Ion/Ioff), subthreshold slope (SS) of varying fin widths of DGMDDHJ FinFET having Silicon layer at drain end Ion(A) 2.44 × 10 −4 2.31× 10 −4 2.01 × 10−4 1.76 × 10−4 1.6 × 10−4

Ioff(A) 3.38 × 10−15 2.55 × 10−15 2.28 × 10−15 1.78 × 10−15 1.44 × 10−15

Ion/Ioff 7.23 × 1010 9.03 × 1010 8.82 × 1010 9.89 × 1010 1.11 × 1011

SS(mV/dec) 70.64 76.04 79.56 85.78 92.28

RI PT

Fin Widths(nm) 10 12 14 16 18

DIBL = −

M AN U

SC

4. 4. Drain Induced Barrier Lowering (DIBL) in DMGDDHJ FinFET DIBL is a detrimental short channel effect in MOS devices, and its effect on any device is significant for low power operations. The role of drain in sharing the charges from the gate in a short channel device is a matter of concern, and its effect on the threshold voltage must be as less as possible. For DMGDDHJ FinFET which has the best Ion/Ioff ratio of all the proposed HJ FinFETS, the drain current has been plotted versus gate voltage at two drain voltages, 0.1 V (low) and 1.0 V (high) as shown in Figure 9. DIBL value has been extracted from the simulator and is found to be 16.83 mV/V according to the expression

VTSAT − VTLIN SAT LIN VDS − VDS

(4)

SAT where VTSAT is the threshold voltage at high drain voltage, VDS , and VTLIN is the threshold

TE D

LIN . The negative sign in the expression of DIBL is due to the voltage at low drain voltage, VDS

AC C

EP

fact that the threshold voltage reduces at higher drain voltage.

Figure 9. Transfer characteristics of DMGDDHJ FinFET at two different drain voltages, 0.1 V and 1 V, showing the effect of DIBL

ACCEPTED MANUSCRIPT 5. Conclusion

RI PT

The analysis carried out in this work suggests that the use of heterojunction in tri-gate FinFET structures reduces the off current up to three orders of magnitude. It has been further examined that keeping other parameters constant, thinner fins exhibit better SS than thicker ones in DGMDDHJ FinFET. For variation in length and doping concentration of the Silicon layer, its position at source end causes a significant impact on device characteristics than its position at drain end. The effect of DIBL on DGMDDHJ FinFET is found to be as low as 16.84 mV/V. As such, the HJ FinFETs as the ones proposed in this work can be potential devices for low power applications, and hence their analytical modeling may be considered as a part of prospective work in future.

AC C

EP

TE D

M AN U

SC

References [1] T. Poiroux, M. Vinet, O.Faynet, J. Widiez ,J. Lolvier, B. Previtali, T. Ernst, S. Deleonibus, Multigate silicon MOSFETs for 45 nm node and beyond, Solid-State Electronics 50 (2006) 18–23. doi:10.1016/j.sse.2005.10.049. [2] T. Ernst, C. Tinella, C. Raynaud, S. Cristoloveanu, Fringing fields in sub-0 .1 μm fully depleted SOI MOSFETs : optimization of the device architecture, Solid-State Electronics 46 (2002) 373–378. [3] S.P. Wong, Beyond the conventional transistor, IBM J. RES. & DEV. Vol. 46 No. 2/3 March/May (2002) 133–168. [4] Y. Yeo, Member, IEEE, T. King, S. Member, IEEE, C. Hu, Fellow, IEEE, MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations, IEEE Transactions on Electron Devices, Vol.50, No.4, April (2003) 1027–1035. [5] Gordon E. Moore, Cramming more components onto integrated circuits, Electronics, Volume 38, Number 8, April 19, 1965. [6] H. Shang, L. Chang, X. Wang, M. Rooks, Y. Zhang, B. To, K. Babich, G. Totir, Y. Sun, E. Kiewra, M. Haench, Investigation of FinFET devices for 32nm technologies and beyond, (2006) Symposium on VLSI Technology Digest of Technical Papers 2005–2006. [7] M. Pavan Kumar, S.Kr. Gupta, M. Paul, Corner Effects in SOI-Tri gate FinFET structure by using 3D Process and Device Simulations, 3rd IEEE International Conference on Computer Science and Information Technology (ICCSIT),Volme:9, (2010) 704–707. [8] V. Narendar, R.A. Mishra, Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects ( SCEs ), Superlattices and Microstructures 85 (2015) 357–369. doi:10.1016/j.spmi.2015.06.004. [9] S.L. Tripathi, R. Mishra, R.A. Mishra, Characteristic comparison of connected DG FINFET , TG FINFET and Independent Gate FINFET on 32 nm technology, 2012 2nd International Conference on Power , Control and Embedded Systems (2012).

ACCEPTED MANUSCRIPT

[15]

[16]

[17]

[18]

[19] [20] [21]

RI PT

SC

[14]

M AN U

[13]

TE D

[12]

EP

[11]

D. Ghai, S.P. Mohanty, G. Thakral, Comparative Analysis of Double Gate FinFET Configurations for Analog Circuit Design, IEEE 56th International Midwest Symposium on Circuits ans Systems (MWSCAS) (2013) 809–812. D. Ghai, S.P. Mohanty, G. Thakral, Double Gate FinFET based Mixed-Signal Design : A VCO Case Study, 56th International Midwest Symposium on Circuits and Systems (MWSCAS) 2 (2013) 177–180. C.R. Manoj, M. Nagpal, D. Varghese, V.R. Rao, S. Member, IEEE , Device Design and Optimization Considerations for Bulk FinFETs, IEEE Transactions on Electron Devices, Vol.55, No.2, February (2008) 609–615. Yang Hong, Yufeng Guo, Hui Yang, Jiafei Yao, Jun Zhang, and Xincun Ji, A Novel Bulk-Finfet with Dual-Material Gate, 12th IEEE International Conference on SolidState and Integrated Circuit Technology (ICSICT), (2014) 10–12. M. Nawaz, P. Haibach, W. Molzer, Optimization of Halo Implant Using 3D TCAD for Nanoscale MuGFETs, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD (2006) 176–179. C.-S. Tang, S-M Yu, H.-M. Chou, J.-W. Lee, Y. Li, Simulation of Electrical Characteristics of Surrounding- and Omega-Shaped-Gate Nanowire FinFETs, 4th IEEE Conf. Nanotechnology. (2004) 281–283. doi:10.1109/NANO.2004.1392325. H. Nam, S. Member, IEEE, C. Shin, Member, IEEE, Impact of Current Flow Shape in Tapered ( Versus Rectangular ) FinFET on Threshold Voltage Variation Induced by Work-Function Variation, IEEE Transactions on Electron Devices, Vol. 61, No.6, June (2014) 2007–2011. M.K. Rai, V. Narendar, R.A. Mishra, Significance of Variation in Various Parameters on Electrical Characteristics of FinFET Devices, IEEE Students Conference on Engineering and Systems (SCES) ,1, (2014) 2–7. F. He, X. Zhou, C. Ma, J. Zhang, Z.Liu, W. Wu, X. Zhang, L. Zhang, FinFET : From Compact Modeling to Circuit Performance, IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), (2010). S.L. Tripathi, R. Mishra, R.A. Mishra, Multi-Gate MOSFET Structures with High-K Dielectric Materials, Journal of Electron Devices, Vol. 16, (2012) pp. 1388–1394. Sentaurus Device User, Synopsys, (2009) 2009. N.B. Balamurugan, K. Sankaranarayanan, M.F. John, 2D Transconductance to Drain Current Ratio Modeling of Dual Material Surrounding Gate Nanoscale SOI MOSFETs, Journal of Semiconductor Technology And Science, Vol.9, No.2, June, 2009, 110–116.

AC C

[10]

ACCEPTED MANUSCRIPT Title: Tri-gate heterojunction SOI Ge-FinFETs Authors: Rajashree Das, Rupam Goswami and Srimanta Baishya

Highlights

RI PT

SC

M AN U

•

TE D

•

EP

•

Heterojunction FinFETs improve the leakage current and Ion/ Ioff ratio as compared to conventional FinFETs, reducing it by three orders of magnitude in case of DGMDDHJ FinFET. Increase in fin width decreases the Subthreshold Swing (SS) with almost similar on and off currents. There is no effect of the variation of length and doping concentration of the Silicon layer at drain end on transfer characteristics of DGMDDHJ FinFET, but significant change is observed when the Silicon layer is located at source end. DIBL is as low as 16.84 mV/V in DGMDDHJ FinFET.

AC C

•