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Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics
Superlattices and Microstructures xxx (2016) 1e10
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Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics Gyanan a, Sandip Mondal b, Arvind Kumar b, * a b
Department of Electronics and Instrumentation (OC), Birla Institute of Technology and Science, Pilani 333031, India Department of Physics, Indian Institute of Science, Bangalore 560012, India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 17 October 2016 Accepted 19 October 2016 Available online xxx
Post-deposition annealing (PDA) is an inherent part of a sol-gel fabrication process to achieve the optimum device performance, especially in CMOS applications. Annealing removes the oxygen vacancies and improves the structural order of the dielectric films. The process also reduces the interface related defects and improves the interfacial properties. Here, we applied a sol-gel spin-coating technique to prepare high-k TiO2 films on the p-Si substrate. These films were fired at 400 C for the duration of 20, 40, 60 and 80 min to know the effects of annealing time on the device characteristics. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of annealed TiO2 films were examined in Al/ TiO2/p-Si device configuration at room temperature. The 60 min annealed film gives the optimum performance and contained 69.5% anatase and 39.5% rutile phase with refractive index 2.40 at 550 nm. The C-V and I-V characteristic showed a significant dependence on annealing time such as variation in dielectric constant and leakage current. This allows us to tune the various electrical properties of MOS systems. The accumulation capacitance (Cox), dielectric constant (k) and the equivalent oxide thickness (EOT) of the film fired for 60 min were found to be 458 pF, 33, and 4.25 nm, respectively with a low leakage current density (3.13 107 A/cm2) fired for 80 min at 1 V. The current conduction mechanisms at high bias voltage were dominated by trap-charge limited current (TCLC), while at small voltages, space charge limited current (SCLC) was more prominent. © 2016 Elsevier Ltd. All rights reserved.
1. Introduction The advancement in modern CMOS technology has played a powerful driving force towards the development of microelectronics and optoelectronics based memory and logic circuits [1,2]. Scaling of these devices has reduced the fabrication cost, enhanced the performance and facilitated large area integration of electronic devices [3]. Last five decades has seen the scaling of transistor feature size from 10 mm to ~22 nm. This decrease in transistor dimensions has exponentially increased the number of transistors on a single chip as predicted by Moore's [3]. This continuous down scaling has reached its fundamental limits for SiO2 gate oxide due to its physical limitations, large leakage current, and large area inhomogeneity at such low thickness [4]. One alternative to overcome these challenges is to substitute SiO2 with higher permittivity (high-k) dielectric
* Corresponding author. E-mail address: [email protected] (A. Kumar). http://dx.doi.org/10.1016/j.spmi.2016.10.054 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
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film as compared to SiO2 (k ¼ 3.9). The high-k oxide can provide similar equivalent capacitance densities at higher physical thickness and hence will reduce the leakage current; the equivalent oxide thickness (teq) is defined by Ref. [1].
teq ¼
tHighk kSiO2 ; kHighk
(1)
where, tHigh-k is the thickness of the high-k oxide layer and kSiO2 and kHigh-k are the dielectric constants of SiO2 and high-k film, respectively. In recent years a wide variety of transition metal oxide thin films, such as Al2O3, HfO2, TiO2, ZrO2 and their compounds are extensively evaluated as an alternative of the SiO2 gate for CMOS devices in the electronic circuits [3,5]. However, these oxide films have to confront several issues, such as thermal stability, a large number of oxide trapped charges and poor interface quality before integrating into the devices. Among all, titanium dioxide (TiO2) thin films have gained a major interest in the industry because of its widespread applications concerning to microelectronics, solar cells, memory devices and photonic crystals [6,7]. Titanium oxide with dielectric constant ranging from 16 to 100 is inherently an n-type semiconductor with a wide band gap of typically 3.5 eV and, a refractive index of about 2.6 has excellent stability with Si [8]. As grown TiO2 is amorphous in nature but crystallizes into three distinct crystallographic structures (a) anatase (a ¼ b ¼ 3.785 Å, c ¼ 9.514 Å) (b) rutile (a ¼ b ¼ 4.587 Å, c ¼ 2.953 Å) with tetragonal and brookite phase has the orthorhombic, (a ¼ 5.456 Å, b ¼ 9.182 Å, c ¼ 5.143 Å) [9]. TiO2 not only meet the requirement of electronic industry but is also favoured because of the properties such as non-toxicity and chemical stability. The electrical and structural properties of TiO2 thin films are largely dependent on the method of preparation [9,10]. The usage of low temperature deposition techniques to produce amorphous TiO2 films has improved its performance by subduing the issues related to band offset with Si and the interface defects density. Along with the preparation methodology, annealing process plays a significant role in achieving the optimal performance of TiO2 thin films [11]. Annealing removes oxygen vacancies and improves structural order, meliorates the dielectric values and results in lower leakage current [12]. Annealing transforms the amorphous phase of TiO2 film into the crystalline form at the different sintering temperature. The anatase phase of TiO2 forms at a temperature below 600 C, while rutile at 800 C. The brookite phase formed at high pressure is not suitable for electronic application because of the instability at normal temperature [9]. Various studies on electrical and dielectric properties of titania thin films deposited by electron beam evaporation, pulsed laser deposition, DC/RF sputtering, chemical vapor deposition and ion beam deposition have been reported [13e16]. Recently, Arvind et al. has reported the electrical and dielectric properties of spin-coated TiO2 thin films and have shown that the 400 C annealed films gives the optimum performance [10]. In the present work, we have used sol-gel spin-coating for the preparation of TiO2 thin films on p-Si substrate. The deposited thin films are annealed at 400 C for different time limits and the effect on its electrical and dielectric properties are studied in Al/TiO2/p-Si MOS systems. 2. Experimental All the chemicals were purchased from Sigma-Aldrich and used without further processing. TiO2 thin films were deposited on a p-Si substrate using a sol-gel spin-coating technique. In the experimental process of sol formation, 0.6 ml of titanium isopropoxide (C12H28O4Ti), the titania precursor was dissolved in 8.5 ml of isopropyl alcohol (CH3CHOHCH3). The solution was stirred continuously for 3 h and was left in an ambient condition for 24 h. The p-Si substrate was cleaned with standard piranha solution, accompanied by dipping in 1% HF for 10s to remove the native oxide and further dried in nitrogen ambiance. The substrate was treated in oxygen plasma chamber for 20 min prior to spin-coating of TiO2 to improve the adhesion of titania films to Si substrate. The solution was allowed to rotate at 4000 rpm for 30s to form a film of TiO2 on Si substrate. This film was baked on a preheated hot plate at 100 C for 5 min followed by the firing at 400 C at various time periods 20, 40, 60 and 80 min. The detailed process flow of TiO2 thin film formation is depicted in Fig. 1. The structural characterization of the films was recorded using Rigaku X-ray diffractometer at a scan rate of 2 per min in the range of 20e60 degree. The film thicknesses were assessed by variable angle spectroscopic ellipsometry (M-2000, J.A. Woollam Co., Inc., USA). The pattern was recorded at the low incident mode to improve the sensitivity of the surface. The film surface analysis and cross-sectional image were observed by Scanning Electron Microscopy image using Ultra 55, Carl Zeiss. The film texture was assessed by AFM (NDMDT Russia). XPS data was taken on AXIS ULTRA from AXIS 165 using a monochromatized Al Ka as the excitation source. The electrical and dielectric characterizations were accomplished by fabricating the metal -Oxide - semiconductor (MOS) systems. The Al metal layer of 200 nm was thermal evaporated using a metal shadow mask of diameter d ¼ 288 m on the samples as front contacts. The schematic of device structure is depicted in Fig. 2. The electrical measurements were performed with Agilent B1500A semiconductor device analyser. 3. Results and discussion The chemical reactions proposed to describe the formation of TiO2 from the solution of titanium isopropoxide and isopropyl alcohol in our experiment is given below [17]. In the detailed sol-gel process, the TiO2 formation would have occurred with the hydrolysis and polymerization of the precursors. It is believed that the reaction mechanism might have started with Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
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Fig. 1. Flow chart for the preparation of TiO2 thin film on Si substrate using sol-gel spin-coating technique.
the dehydration of isopropyl alcohol into R’ (¼ C3H6) and H2O in the reaction condition. The H2O molecules formed during this process facilitated the hydrolytic decomposition of titanium isopropoxide to form titanium hydroxide and additional alcohol molecules. Finally, these unstable titanium hydroxide molecules decomposes and condense to form the titanium oxide [18].
ROH%R0 þ H2 O
(2a)
TiðORÞ4 þ H2 O%TiðORÞ3 ðOHÞ þ ROH
(2b)
TiOR3 ðOHÞ þ H2 O%TiðORÞ2 ðOHÞ2 þ ROH
(2c)
TiOR2 ðOHÞ2 þ H2 O%TiðORÞðOHÞ3 þ ROH
(2d)
TiðORÞ2 ðOHÞ2 /TiO2 þ 2ROH
(2e)
TiðORÞðOHÞ3 /TiO2 þ H2 O þ ROH
(2f)
R is the isopropoxy group. Fig. 3 Shows the XRD pattern of TiO2 film deposited on Si substrate and annealed at 60 min for 400 C. The peak positions at 25.3 with reflection (101) and at a subsided peak of 49 with reflection (211) suggests a tetragonal structure with the presence of anatase and rutile phases. The amount (%) of the anatase and rutile phases of the films was calculated from XRD data using the equations below [19]:
0:79IA 100; ðIR þ 0:791A Þ 8 9 < = 1 i 100; Rutileð%Þ ¼ h : ðIR þ0:791A Þ ;
Anataseð%Þ ¼
(3a)
(3b)
IR
Here, IA and IR refer to the intensities corresponding to anatase and rutile phase of TiO2 in the XRD graph. The percentage of anatase and rutile phases of TiO2 in the film was estimated to be 69.5 and 30.5 respectively. The grain size of the TiO2 film was calculated using Debyee Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
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Fig. 2. Schematic representation of Al/TiO2/p-Si MOS device structure fabricated to analyze the electrical and dielectric properties of TiO2 films.
Fig. 3. XRD spectra of TiO2 thin film on silicon (100) substrate annealed at 400 C for 60 min.
Scherrer's equation given by Ref. [18].
D¼
kl b cos q
(4)
(where, l (0.15406 nm) is the wavelength of the X-ray radiation, k (constant) is taken as 0.89 here, b is the full-width half maximum, and q is the diffraction angle. The average grain size was found to be 14 nm. Fig. 4(a) depicts the experimental and fitted ellipsometric curves of the films annealed at 400 C for 60 min and measured at an incident angle of 65 . The mean square error (MSE) value is 1.93, which indicates a very good fit with the experimental data. The thickness of the film is estimated from this fit and was found to be 30 nm. For further verification, a cross-sectional SEM image was obtained [as shown in Fig. 4(b)] for the film annealed for 60 min and it was found that thickness measured by both the method are similar. The refractive index (n) dispersion plots derived from the fit are shown in Fig. 5. The refractive index values are 2.37, 2.38, 2.40 and 2.41 at 550 nm for the films annealed for 20, 40, 60 and 80 min, respectively, which are closer to the refractive index of the pore-free TiO2 films (n ¼ 2.52) [20]. The small change in ‘n’ is due to the densification of the films with increasing time duration. The porosity of the films were calculated using the equation mentioned in Ref. [21]. The porosity of the films is 13, 12, 11 and 10 for the films annealed at 20, 40, 60 and 80 min, respectively. The small value of porosity is the indication of very high quality films. Fig. 6(a) shows the surface morphology by SEM and suggests a pore and crack free smooth TiO2 films with nano-crystalline nature. The grain sizes were quite small and alike the XRD results. The AFM image of the film is shown in Fig. 6(b) and is backing the FESEM observations. The estimated RMS surface roughness was 1.7, which suggests an ultra-smooth surface of TiO2 films, well-suited to the microelectronic applications.
Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
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Fig. 4. (a) Experimental and Cauchy model fitted J-D-l plot for the films annealed at 400 C for 60 min. (b) The cross-sectional SEM micrograph to verify the thickness measured by Ellipsometry.
The elemental compositions analyses of the films were performed using XPS and the survey scan spectra are given in Fig. 7(a). All the spectra were recorded after etching to avoid the surface contamination which may debase the information of chemical compositions and valence state of Ti and O. The core level C 1s spectrum is given in Fig. 7(b), where the peak at 284 eV was used for calibration. The core level spectrum for the Ti 2p is given in Fig. 7(c). The peaks Ti 2p3/2 and Ti 2p1/2 centered at 459.70 and 465.42 eV suggests the presence of Ti in its tetravalent states [22,23]. Fig. 7(d) shows the O 1s core level spectrum, centered at 531 eV. The shoulder peak observed around 533 eV may have originated from the surface adsorbed oxygen or from the lattice oxygen defects [24]. The O/Ti atomic ratio obtained using Casa XPS software was 1.91 for the 60 min annealed films. The C-V characteristics of Al/TiO2/p-Si MOS system measured at 1 MHz AC frequency is shown in Fig. 8. The plot demonstrates a well-defined accumulation, depletion and inversion region subjected to a cyclic voltage of 4 V to þ4 V forth and back. The dielectric constant (k) of TiO2 thin films are calculated from the C-V plot using the expression.
k¼
Cox tox ; ε0 A
(5)
where, Cox, tox, ε0, A are the accumulation capacitance, oxide film thickness, permittivity of free space and the area of the device, respectively.
Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
Fig. 5. The refractive index (n) as a function of wavelength of TiO2 thin films annealed at different time domain.
Fig. 6. (a): The scanning emission micrograph (SEM) and (b) Atomic force micrograph (AFM) of TiO2 thin film on silicon substrates. The films clearly display a smooth surface with nano-sized grains.
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Fig. 7. (a) Wide scan XPS of TiO2 thin films annealed at 400 C for 60 min (b) C1s XPS core level spectra (c) Ti2p XPS core level spectra and (d) O1s XPS core level spectra of TiO2 film annealed for 60 min.
The film annealed at 400 C for 60 min shows maximum accumulation capacitance (Cox) compared to films annealed at different time limits. However, the Cox decreases further with the increasing of firing time at 80 min. The initial increase in k can be attributed to the crystallization of amorphous TiO2 film into anatase phase followed by a decrease in k for the larger annealing period due to the growth of a thick interlayer (SiOx), which reduces the effective capacitance [25]. The Cox and k of the films annealed at 400 C for 60 min are 458 pF and 33, respectively. The various electrical parameters of TiO2 based MOS system are summarized in Table 1. It can be observed that flat band voltage (VFB) and change in flat band voltage (DVFB) are varying with firing temperature. The VFB variation can be attributed to the removal and generation of oxide and interface charges [3]. The film annealed for 60 min shows the minimum hysteresis of 0.05 V and suggests a high quality interface with minimal oxide trapped charges [1]. The variation in k and EOT with the calcination time is shown in Fig. 9. The teq estimated using Eq. (1) was very low (as it is desirable for CMOS applications) for the films fired for 60 min was found to be of 4.25 nm. Fig. 10(a) shows the leakage current as a function of the bias voltage (J-V) of Al/TiO2/p-Si MOS system. The asymmetry in the plots for the gate and substrate injection mode is due to the different barriers heights [26]. The leakage current density is varying randomly with different time limits. The variation of gate injection mode at 1 V is tabulated in Table 1. The change in leakage current density is originated from the partial to complete crystallization of TiO2 films and growth of the SiOx interlayer. The films annealed for 80 min shows a low leakage current density (3.13 107 A/cm2) which is attributed to a smooth, crack-free surface and good quality interface [27]. To analyze the current conduction mechanism, J-V curve was plotted on the log-log scale as depicted in Fig. 10(b). The plot shows two different distinct regions and suggests different charge transport mechanisms across MOS device. The inset graph in Fig. 10(b) shows the experimental and fitted J-V curve for the film annealed for 60 min. The region (low voltages) with slope of 1.49 indicates that the current is approaching to a space-charge-limited region (SCLC). The slope of region two (higher voltages) is 4.54 which indicates a trap-charge limited current (TCLC) is dominating in this region [28]. It is also observed that the conduction mechanism is varying slightly with annealing time. The above findings suggest that the time dependent annealing can tune the device parameters.
Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
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Fig. 8. C-V characteristic of Al/TiO2/p-Si (100) MOS systems for the films annealed at 400 C for the 20, 40, 60 and 80 min in ambient condition.
Table 1 The summary of various electrical parameters of TiO2 based MOS systems deposited by spin-coating technique in this study. Firing time
Cox (F)
20 40 60 80
33 39 39 45
1012 1012 1012 1012
k
CFB_f (F)
24 28 33 28
8.38 9.28 9.08 1.10
1011 1011 1011 1010
CFB_r (F) 8.42 9.62 9.17 1.08
1011 1011 1011 1010
VFB_f (V)
VFB_r (V)
VFB_r (V)
DVFB (V)
Qot (cm2)
0.5 0.5 0.5 0.5
1.0 0.67 0.45 0.90
0.5 0.5 0.5 0.5
0.50 0.17 0.05 0.40
1.88 7.80 2.22 2.07
1012 1011 1011 1012
J@ 1 V (A cm2) 6.69 2.06 3.13 3.13
108 107 107 107
Note: Cox e Oxide capacitance, k e Dielectric constant, CFB e Flat band capacitance, VFB e Flat band voltage, DVFB e Change in flat band voltage, Qot e Oxide trapped charges, J e Current density, f e Forward, r e Reverse.
Fig. 9. Dielectric constant (k) and equivalent oxide thickness (EOT) of 400 C TiO2 films as a function of time duration.
4. Conclusions In conclusion, we studied the influence of time dependent annealing on the TiO2 thin films and Al/TiO2/p-Si MOS system fabricated by sol-gel spin coating technique. AFM and SEM analysis suggests a pore, crack free and compact films with small 1.7 nm RMS surface roughness. The XPS analysis concludes a nearly stoichiometric film. The firing time is found to have a significant effect on the films characteristics and hence affects MOS parameters such as Cox, VFB, k and EOT of the gate stack. Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
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Fig. 10. (a) Current-Voltage characteristics of Al/TiO2/p-Si (100) MOS systems annealed at 400 C for the 20, 40, 60 and 80 min in ambient condition (b) shows the J-V curve at log-log scale and distinct region are the indication of different charge transport at the different voltages. Inset of Fig (b) shows the experimental and fitted regions for the film annealed for 60 min.
The Cox, k and EOT of the film fired for 60 min were found to be 458 pF, 33 and 4.25 nm, respectively with a low leakage current density (3.13 107 A/cm2). The current conduction mechanisms are found to be bias voltage dependent at high voltage it is dominated by TCLC, while at small bias voltages it is approaching SCLC. Our result suggests the tuning of device parameters by using time dependent annealing. Acknowledgements The Authors thank CeNSE, IISc, Bangalore, for material characterizations. References [1] G.D. Wilk, R.M. Wallace, J.M. Anthony, High-k gate dielectrics: current status and materials properties considerations, J. Appl. Phys. 89 (2001) 5243e5275, http://dx.doi.org/10.1063/1.1361065. [2] S. Mondal, V. Venkataraman, All inorganic spin-coated nanoparticle based capacitive memory devices, IEEE Elec. Dev. Lett. 37 (2016) 396e399, http:// dx.doi.org/10.1109/LED.2016.2527689. [3] J. Robertson, R.M. Wallace, High-K materials and metal gates for CMOS applications, Mater. Sci. Eng. R. 88 (2015) 1e41, http://dx.doi.org/10.1016/j.mser. 2014.11.001.
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Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics Gyanan a, Sandip Mondal b, Arvind Kumar b, * a b
Department of Electronics and Instrumentation (OC), Birla Institute of Technology and Science, Pilani 333031, India Department of Physics, Indian Institute of Science, Bangalore 560012, India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 17 October 2016 Accepted 19 October 2016 Available online xxx
Post-deposition annealing (PDA) is an inherent part of a sol-gel fabrication process to achieve the optimum device performance, especially in CMOS applications. Annealing removes the oxygen vacancies and improves the structural order of the dielectric films. The process also reduces the interface related defects and improves the interfacial properties. Here, we applied a sol-gel spin-coating technique to prepare high-k TiO2 films on the p-Si substrate. These films were fired at 400 C for the duration of 20, 40, 60 and 80 min to know the effects of annealing time on the device characteristics. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of annealed TiO2 films were examined in Al/ TiO2/p-Si device configuration at room temperature. The 60 min annealed film gives the optimum performance and contained 69.5% anatase and 39.5% rutile phase with refractive index 2.40 at 550 nm. The C-V and I-V characteristic showed a significant dependence on annealing time such as variation in dielectric constant and leakage current. This allows us to tune the various electrical properties of MOS systems. The accumulation capacitance (Cox), dielectric constant (k) and the equivalent oxide thickness (EOT) of the film fired for 60 min were found to be 458 pF, 33, and 4.25 nm, respectively with a low leakage current density (3.13 107 A/cm2) fired for 80 min at 1 V. The current conduction mechanisms at high bias voltage were dominated by trap-charge limited current (TCLC), while at small voltages, space charge limited current (SCLC) was more prominent. © 2016 Elsevier Ltd. All rights reserved.
1. Introduction The advancement in modern CMOS technology has played a powerful driving force towards the development of microelectronics and optoelectronics based memory and logic circuits [1,2]. Scaling of these devices has reduced the fabrication cost, enhanced the performance and facilitated large area integration of electronic devices [3]. Last five decades has seen the scaling of transistor feature size from 10 mm to ~22 nm. This decrease in transistor dimensions has exponentially increased the number of transistors on a single chip as predicted by Moore's [3]. This continuous down scaling has reached its fundamental limits for SiO2 gate oxide due to its physical limitations, large leakage current, and large area inhomogeneity at such low thickness [4]. One alternative to overcome these challenges is to substitute SiO2 with higher permittivity (high-k) dielectric
* Corresponding author. E-mail address: [email protected] (A. Kumar). http://dx.doi.org/10.1016/j.spmi.2016.10.054 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
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film as compared to SiO2 (k ¼ 3.9). The high-k oxide can provide similar equivalent capacitance densities at higher physical thickness and hence will reduce the leakage current; the equivalent oxide thickness (teq) is defined by Ref. [1].
teq ¼
tHighk kSiO2 ; kHighk
(1)
where, tHigh-k is the thickness of the high-k oxide layer and kSiO2 and kHigh-k are the dielectric constants of SiO2 and high-k film, respectively. In recent years a wide variety of transition metal oxide thin films, such as Al2O3, HfO2, TiO2, ZrO2 and their compounds are extensively evaluated as an alternative of the SiO2 gate for CMOS devices in the electronic circuits [3,5]. However, these oxide films have to confront several issues, such as thermal stability, a large number of oxide trapped charges and poor interface quality before integrating into the devices. Among all, titanium dioxide (TiO2) thin films have gained a major interest in the industry because of its widespread applications concerning to microelectronics, solar cells, memory devices and photonic crystals [6,7]. Titanium oxide with dielectric constant ranging from 16 to 100 is inherently an n-type semiconductor with a wide band gap of typically 3.5 eV and, a refractive index of about 2.6 has excellent stability with Si [8]. As grown TiO2 is amorphous in nature but crystallizes into three distinct crystallographic structures (a) anatase (a ¼ b ¼ 3.785 Å, c ¼ 9.514 Å) (b) rutile (a ¼ b ¼ 4.587 Å, c ¼ 2.953 Å) with tetragonal and brookite phase has the orthorhombic, (a ¼ 5.456 Å, b ¼ 9.182 Å, c ¼ 5.143 Å) [9]. TiO2 not only meet the requirement of electronic industry but is also favoured because of the properties such as non-toxicity and chemical stability. The electrical and structural properties of TiO2 thin films are largely dependent on the method of preparation [9,10]. The usage of low temperature deposition techniques to produce amorphous TiO2 films has improved its performance by subduing the issues related to band offset with Si and the interface defects density. Along with the preparation methodology, annealing process plays a significant role in achieving the optimal performance of TiO2 thin films [11]. Annealing removes oxygen vacancies and improves structural order, meliorates the dielectric values and results in lower leakage current [12]. Annealing transforms the amorphous phase of TiO2 film into the crystalline form at the different sintering temperature. The anatase phase of TiO2 forms at a temperature below 600 C, while rutile at 800 C. The brookite phase formed at high pressure is not suitable for electronic application because of the instability at normal temperature [9]. Various studies on electrical and dielectric properties of titania thin films deposited by electron beam evaporation, pulsed laser deposition, DC/RF sputtering, chemical vapor deposition and ion beam deposition have been reported [13e16]. Recently, Arvind et al. has reported the electrical and dielectric properties of spin-coated TiO2 thin films and have shown that the 400 C annealed films gives the optimum performance [10]. In the present work, we have used sol-gel spin-coating for the preparation of TiO2 thin films on p-Si substrate. The deposited thin films are annealed at 400 C for different time limits and the effect on its electrical and dielectric properties are studied in Al/TiO2/p-Si MOS systems. 2. Experimental All the chemicals were purchased from Sigma-Aldrich and used without further processing. TiO2 thin films were deposited on a p-Si substrate using a sol-gel spin-coating technique. In the experimental process of sol formation, 0.6 ml of titanium isopropoxide (C12H28O4Ti), the titania precursor was dissolved in 8.5 ml of isopropyl alcohol (CH3CHOHCH3). The solution was stirred continuously for 3 h and was left in an ambient condition for 24 h. The p-Si substrate was cleaned with standard piranha solution, accompanied by dipping in 1% HF for 10s to remove the native oxide and further dried in nitrogen ambiance. The substrate was treated in oxygen plasma chamber for 20 min prior to spin-coating of TiO2 to improve the adhesion of titania films to Si substrate. The solution was allowed to rotate at 4000 rpm for 30s to form a film of TiO2 on Si substrate. This film was baked on a preheated hot plate at 100 C for 5 min followed by the firing at 400 C at various time periods 20, 40, 60 and 80 min. The detailed process flow of TiO2 thin film formation is depicted in Fig. 1. The structural characterization of the films was recorded using Rigaku X-ray diffractometer at a scan rate of 2 per min in the range of 20e60 degree. The film thicknesses were assessed by variable angle spectroscopic ellipsometry (M-2000, J.A. Woollam Co., Inc., USA). The pattern was recorded at the low incident mode to improve the sensitivity of the surface. The film surface analysis and cross-sectional image were observed by Scanning Electron Microscopy image using Ultra 55, Carl Zeiss. The film texture was assessed by AFM (NDMDT Russia). XPS data was taken on AXIS ULTRA from AXIS 165 using a monochromatized Al Ka as the excitation source. The electrical and dielectric characterizations were accomplished by fabricating the metal -Oxide - semiconductor (MOS) systems. The Al metal layer of 200 nm was thermal evaporated using a metal shadow mask of diameter d ¼ 288 m on the samples as front contacts. The schematic of device structure is depicted in Fig. 2. The electrical measurements were performed with Agilent B1500A semiconductor device analyser. 3. Results and discussion The chemical reactions proposed to describe the formation of TiO2 from the solution of titanium isopropoxide and isopropyl alcohol in our experiment is given below [17]. In the detailed sol-gel process, the TiO2 formation would have occurred with the hydrolysis and polymerization of the precursors. It is believed that the reaction mechanism might have started with Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
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Fig. 1. Flow chart for the preparation of TiO2 thin film on Si substrate using sol-gel spin-coating technique.
the dehydration of isopropyl alcohol into R’ (¼ C3H6) and H2O in the reaction condition. The H2O molecules formed during this process facilitated the hydrolytic decomposition of titanium isopropoxide to form titanium hydroxide and additional alcohol molecules. Finally, these unstable titanium hydroxide molecules decomposes and condense to form the titanium oxide [18].
ROH%R0 þ H2 O
(2a)
TiðORÞ4 þ H2 O%TiðORÞ3 ðOHÞ þ ROH
(2b)
TiOR3 ðOHÞ þ H2 O%TiðORÞ2 ðOHÞ2 þ ROH
(2c)
TiOR2 ðOHÞ2 þ H2 O%TiðORÞðOHÞ3 þ ROH
(2d)
TiðORÞ2 ðOHÞ2 /TiO2 þ 2ROH
(2e)
TiðORÞðOHÞ3 /TiO2 þ H2 O þ ROH
(2f)
R is the isopropoxy group. Fig. 3 Shows the XRD pattern of TiO2 film deposited on Si substrate and annealed at 60 min for 400 C. The peak positions at 25.3 with reflection (101) and at a subsided peak of 49 with reflection (211) suggests a tetragonal structure with the presence of anatase and rutile phases. The amount (%) of the anatase and rutile phases of the films was calculated from XRD data using the equations below [19]:
0:79IA 100; ðIR þ 0:791A Þ 8 9 < = 1 i 100; Rutileð%Þ ¼ h : ðIR þ0:791A Þ ;
Anataseð%Þ ¼
(3a)
(3b)
IR
Here, IA and IR refer to the intensities corresponding to anatase and rutile phase of TiO2 in the XRD graph. The percentage of anatase and rutile phases of TiO2 in the film was estimated to be 69.5 and 30.5 respectively. The grain size of the TiO2 film was calculated using Debyee Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
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Fig. 2. Schematic representation of Al/TiO2/p-Si MOS device structure fabricated to analyze the electrical and dielectric properties of TiO2 films.
Fig. 3. XRD spectra of TiO2 thin film on silicon (100) substrate annealed at 400 C for 60 min.
Scherrer's equation given by Ref. [18].
D¼
kl b cos q
(4)
(where, l (0.15406 nm) is the wavelength of the X-ray radiation, k (constant) is taken as 0.89 here, b is the full-width half maximum, and q is the diffraction angle. The average grain size was found to be 14 nm. Fig. 4(a) depicts the experimental and fitted ellipsometric curves of the films annealed at 400 C for 60 min and measured at an incident angle of 65 . The mean square error (MSE) value is 1.93, which indicates a very good fit with the experimental data. The thickness of the film is estimated from this fit and was found to be 30 nm. For further verification, a cross-sectional SEM image was obtained [as shown in Fig. 4(b)] for the film annealed for 60 min and it was found that thickness measured by both the method are similar. The refractive index (n) dispersion plots derived from the fit are shown in Fig. 5. The refractive index values are 2.37, 2.38, 2.40 and 2.41 at 550 nm for the films annealed for 20, 40, 60 and 80 min, respectively, which are closer to the refractive index of the pore-free TiO2 films (n ¼ 2.52) [20]. The small change in ‘n’ is due to the densification of the films with increasing time duration. The porosity of the films were calculated using the equation mentioned in Ref. [21]. The porosity of the films is 13, 12, 11 and 10 for the films annealed at 20, 40, 60 and 80 min, respectively. The small value of porosity is the indication of very high quality films. Fig. 6(a) shows the surface morphology by SEM and suggests a pore and crack free smooth TiO2 films with nano-crystalline nature. The grain sizes were quite small and alike the XRD results. The AFM image of the film is shown in Fig. 6(b) and is backing the FESEM observations. The estimated RMS surface roughness was 1.7, which suggests an ultra-smooth surface of TiO2 films, well-suited to the microelectronic applications.
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Fig. 4. (a) Experimental and Cauchy model fitted J-D-l plot for the films annealed at 400 C for 60 min. (b) The cross-sectional SEM micrograph to verify the thickness measured by Ellipsometry.
The elemental compositions analyses of the films were performed using XPS and the survey scan spectra are given in Fig. 7(a). All the spectra were recorded after etching to avoid the surface contamination which may debase the information of chemical compositions and valence state of Ti and O. The core level C 1s spectrum is given in Fig. 7(b), where the peak at 284 eV was used for calibration. The core level spectrum for the Ti 2p is given in Fig. 7(c). The peaks Ti 2p3/2 and Ti 2p1/2 centered at 459.70 and 465.42 eV suggests the presence of Ti in its tetravalent states [22,23]. Fig. 7(d) shows the O 1s core level spectrum, centered at 531 eV. The shoulder peak observed around 533 eV may have originated from the surface adsorbed oxygen or from the lattice oxygen defects [24]. The O/Ti atomic ratio obtained using Casa XPS software was 1.91 for the 60 min annealed films. The C-V characteristics of Al/TiO2/p-Si MOS system measured at 1 MHz AC frequency is shown in Fig. 8. The plot demonstrates a well-defined accumulation, depletion and inversion region subjected to a cyclic voltage of 4 V to þ4 V forth and back. The dielectric constant (k) of TiO2 thin films are calculated from the C-V plot using the expression.
k¼
Cox tox ; ε0 A
(5)
where, Cox, tox, ε0, A are the accumulation capacitance, oxide film thickness, permittivity of free space and the area of the device, respectively.
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Fig. 5. The refractive index (n) as a function of wavelength of TiO2 thin films annealed at different time domain.
Fig. 6. (a): The scanning emission micrograph (SEM) and (b) Atomic force micrograph (AFM) of TiO2 thin film on silicon substrates. The films clearly display a smooth surface with nano-sized grains.
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Fig. 7. (a) Wide scan XPS of TiO2 thin films annealed at 400 C for 60 min (b) C1s XPS core level spectra (c) Ti2p XPS core level spectra and (d) O1s XPS core level spectra of TiO2 film annealed for 60 min.
The film annealed at 400 C for 60 min shows maximum accumulation capacitance (Cox) compared to films annealed at different time limits. However, the Cox decreases further with the increasing of firing time at 80 min. The initial increase in k can be attributed to the crystallization of amorphous TiO2 film into anatase phase followed by a decrease in k for the larger annealing period due to the growth of a thick interlayer (SiOx), which reduces the effective capacitance [25]. The Cox and k of the films annealed at 400 C for 60 min are 458 pF and 33, respectively. The various electrical parameters of TiO2 based MOS system are summarized in Table 1. It can be observed that flat band voltage (VFB) and change in flat band voltage (DVFB) are varying with firing temperature. The VFB variation can be attributed to the removal and generation of oxide and interface charges [3]. The film annealed for 60 min shows the minimum hysteresis of 0.05 V and suggests a high quality interface with minimal oxide trapped charges [1]. The variation in k and EOT with the calcination time is shown in Fig. 9. The teq estimated using Eq. (1) was very low (as it is desirable for CMOS applications) for the films fired for 60 min was found to be of 4.25 nm. Fig. 10(a) shows the leakage current as a function of the bias voltage (J-V) of Al/TiO2/p-Si MOS system. The asymmetry in the plots for the gate and substrate injection mode is due to the different barriers heights [26]. The leakage current density is varying randomly with different time limits. The variation of gate injection mode at 1 V is tabulated in Table 1. The change in leakage current density is originated from the partial to complete crystallization of TiO2 films and growth of the SiOx interlayer. The films annealed for 80 min shows a low leakage current density (3.13 107 A/cm2) which is attributed to a smooth, crack-free surface and good quality interface [27]. To analyze the current conduction mechanism, J-V curve was plotted on the log-log scale as depicted in Fig. 10(b). The plot shows two different distinct regions and suggests different charge transport mechanisms across MOS device. The inset graph in Fig. 10(b) shows the experimental and fitted J-V curve for the film annealed for 60 min. The region (low voltages) with slope of 1.49 indicates that the current is approaching to a space-charge-limited region (SCLC). The slope of region two (higher voltages) is 4.54 which indicates a trap-charge limited current (TCLC) is dominating in this region [28]. It is also observed that the conduction mechanism is varying slightly with annealing time. The above findings suggest that the time dependent annealing can tune the device parameters.
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Fig. 8. C-V characteristic of Al/TiO2/p-Si (100) MOS systems for the films annealed at 400 C for the 20, 40, 60 and 80 min in ambient condition.
Table 1 The summary of various electrical parameters of TiO2 based MOS systems deposited by spin-coating technique in this study. Firing time
Cox (F)
20 40 60 80
33 39 39 45
1012 1012 1012 1012
k
CFB_f (F)
24 28 33 28
8.38 9.28 9.08 1.10
1011 1011 1011 1010
CFB_r (F) 8.42 9.62 9.17 1.08
1011 1011 1011 1010
VFB_f (V)
VFB_r (V)
VFB_r (V)
DVFB (V)
Qot (cm2)
0.5 0.5 0.5 0.5
1.0 0.67 0.45 0.90
0.5 0.5 0.5 0.5
0.50 0.17 0.05 0.40
1.88 7.80 2.22 2.07
1012 1011 1011 1012
J@ 1 V (A cm2) 6.69 2.06 3.13 3.13
108 107 107 107
Note: Cox e Oxide capacitance, k e Dielectric constant, CFB e Flat band capacitance, VFB e Flat band voltage, DVFB e Change in flat band voltage, Qot e Oxide trapped charges, J e Current density, f e Forward, r e Reverse.
Fig. 9. Dielectric constant (k) and equivalent oxide thickness (EOT) of 400 C TiO2 films as a function of time duration.
4. Conclusions In conclusion, we studied the influence of time dependent annealing on the TiO2 thin films and Al/TiO2/p-Si MOS system fabricated by sol-gel spin coating technique. AFM and SEM analysis suggests a pore, crack free and compact films with small 1.7 nm RMS surface roughness. The XPS analysis concludes a nearly stoichiometric film. The firing time is found to have a significant effect on the films characteristics and hence affects MOS parameters such as Cox, VFB, k and EOT of the gate stack. Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054
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Fig. 10. (a) Current-Voltage characteristics of Al/TiO2/p-Si (100) MOS systems annealed at 400 C for the 20, 40, 60 and 80 min in ambient condition (b) shows the J-V curve at log-log scale and distinct region are the indication of different charge transport at the different voltages. Inset of Fig (b) shows the experimental and fitted regions for the film annealed for 60 min.
The Cox, k and EOT of the film fired for 60 min were found to be 458 pF, 33 and 4.25 nm, respectively with a low leakage current density (3.13 107 A/cm2). The current conduction mechanisms are found to be bias voltage dependent at high voltage it is dominated by TCLC, while at small bias voltages it is approaching SCLC. Our result suggests the tuning of device parameters by using time dependent annealing. Acknowledgements The Authors thank CeNSE, IISc, Bangalore, for material characterizations. References [1] G.D. Wilk, R.M. Wallace, J.M. Anthony, High-k gate dielectrics: current status and materials properties considerations, J. Appl. Phys. 89 (2001) 5243e5275, http://dx.doi.org/10.1063/1.1361065. [2] S. Mondal, V. Venkataraman, All inorganic spin-coated nanoparticle based capacitive memory devices, IEEE Elec. Dev. Lett. 37 (2016) 396e399, http:// dx.doi.org/10.1109/LED.2016.2527689. [3] J. Robertson, R.M. Wallace, High-K materials and metal gates for CMOS applications, Mater. Sci. Eng. R. 88 (2015) 1e41, http://dx.doi.org/10.1016/j.mser. 2014.11.001.
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Please cite this article in press as: GyananS. Mondal et al., Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics, Superlattices and Microstructures (2016), http://dx.doi.org/10.1016/j.spmi.2016.10.054