- Email: [email protected]
Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control
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ARTICLE IN PRESS
FUSION-8807; No. of Pages 7
Fusion Engineering and Design xxx (2016) xxx–xxx
Contents lists available at ScienceDirect
Fusion Engineering and Design journal homepage: www.elsevier.com/locate/fusengdes
Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control Abhijeet Kumar ∗ , Rachana Rajpal, Harshad Pujara, Hitesh Mandaliya, Praveenalal Edappala Institute For Plasma Research, Gandhinagar, Gujarat, India
h i g h l i g h t s • We have designed Universal Interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for Instrumentation & Control. This project is based on Zynq® -7000 family xc7z020clg484-1 chip.
• We explored the full design flow starting from the hardware development in Vivado to software development in SDK using APIs in C language and then interfacing the host application developed in LabVIEW.
• We also explored how to make custom IP with AXI bus interface in Vivado. • Useful for those who wants to make custom hardware on Zynq® SoC.
a r t i c l e
i n f o
Article history: Received 19 June 2015 Received in revised form 2 May 2016 Accepted 13 June 2016 Available online xxx Keywords: Zynq CAN Ethernet AXI-GPIO Custom-IP UART
a b s t r a c t This paper describes an application developed on the latest Zynq® -7000 All Programmable SoC (AP SoC) [1] devices which integrate the software programmability of an ARM® -based processor with the hardware programmability of an FPGA, on a single device. In this paper we have implemented application which uses various interfaces like CAN, RS-232, Ethernet and AXI GPIO, so that our host application running on PC in LabVIEW can communicates with any hardware which has at least any one of the available interface. Zynq-7000 All Programmable SoCs (System On Chip) infuse customizable intelligence into today’s embedded systems to suit your unique application requirements. This family of FPGA is meant for high end application because it has huge resources on single chip. It offers you to make your own custom hardware IP, in fact we have made our custom IP called myIP in our design. The beauty of this chip is that it can write drivers for your custom IP which has AXI bus layer attached. After exporting the hardware information to the Software Development Kit (SDK), the tool is able to write drivers for your custom IP. This simplifies your development to a great extent. In a way this application provides the universal interfacing option to user. User can also write the digital data on the GPIO (General Purpose Input Output) through LabVIEW Test application GUI. This project can be used for remote control and monitor the data over Ethernet or CAN network. © 2016 Elsevier B.V. All rights reserved.
1. Introduction There are many front end electronics and signal conditioning units for various diagnostic of SST-1 and ADITYA tokamak. These diagnostic electronics have different types of handshaking viz. RS232, CAN bus and Ethernet. So, there is a need of system which can control these parameters remotely at one place. To fulfill this requirement zc702 development board [7] is chosen to prototype
∗ Corresponding author. E-mail addresses: [email protected], [email protected] (A. Kumar).
a control system which can be able to control the parameters like Gain of amplifier, filter frequency etc remotely and can send the acquired data to the server. The client can any time see these data remotely for analysis purpose. 2. System block diagram As shown in Fig. 1 zc-702 board [7] is shown by dotted lines it consists of many interfaces but I have highlighted only those which I have used in my design. So, it has two PMOD connector, some switches, FMC connector and Zynq® IC (xc7z020clg484-1). This IC is mainly divided into two sections Processing System (PS) and Pro-
http://dx.doi.org/10.1016/j.fusengdes.2016.06.020 0920-3796/© 2016 Elsevier B.V. All rights reserved.
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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Fig. 1. System Block Diagram.
Fig. 2. Hardware implementation design flow diagram.
grammable Logic (PL) which is a FPGA. In the PL a AXI GPIO and a custom hardware IP [6] called my IP is made. AXI GPIO is used to read the eight binary switches through PMOD-1 and PMOD-2. And my IP is interfaced to read the switches and writes the data on the FMC connector. The project is mainly divided into three main sections. Firstly, the hardware implementation on Zynq® SoC in Vivado 2014.2 tool from Xilinx [3]. Secondly, software implementation in SDK 2014.2 [3] in C using APIs for ARM Cortex A9 processor and Third part is the host application GUI development in LabVIEW 2012. 2.1. Hardware implementation In Vivado Open Vivado [4] and then create the main project, now open a blank block diagram and add all the IPs needed in your design, you can also add any custom IP made by you. Do the connection between these IP blocks and then validate your design to check whether there is any error in the block design. If there is no error then generate the output product and then create a top level wrapper for your design and also add the user constrain file. Now do the synthesis and implementation of your design and then generate the bitstream as shown in Fig. 2. Now, export this bitstream to the SDK where actual software implementation is to be done. The Fig. 3 shows the hardware block diagram of the system. Here we have added the soft IPs available, for example, we have added Zynq® 7 Processing System Block and
AXI GPIO IP [5] block into the block diagram and a custom IP named as myIP. Rest all block it automatically adds into the system while doing connection, the beauty of the system is that it automatically guides you for the connection or you can manually connect the ports. 2.2. Software implementation in SDK After you export the hardware details to the SDK [4] then it will automatically create a hardware folder which will be having all the hardware related files. First step is to create FSBL i.e. First Stage Boot Loader and its BSP i.e. Board Support Package using template as shown in Fig. 4. This BSP will carry all the driver information. The beauty of this software is that it will write the device drivers for you. The tool is able to write the device driver because you have created or used that IPs which is having AXI bus interconnects stitched while creating the IPs. This makes our life very easy because you have to just see the documentation of the drivers given in system.mss file and use these APIs to write the application code. Finally build the project and create .elf file. 2.2.1. CAN application development in SDK Here a custom IP named myIP with AXI-lite bus interface is made as shown in Fig. 3. The signals monitored by the FPGA are those of module ID and the Electronics and Data Acquisition System modules which are inserted. For the purpose of testing, the insertion and
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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Fig. 3. Hardwar Block Diagram Created in Vivado.
Fig. 4. Software implementation design flow diagram.
Fig. 5. CAN Application Programming Flowchart.
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Fig. 7. Ethernet Application Programming Flowchart.
Fig. 6. Ethernet with AXI-GPIO application Programming Flowchart.
removal of a module is imitated by the use of switches available on the board. The control signals are generated by the hardware and the parameter value which is to be set is brought out on the FMC connector. As shown in the flowchart in Fig. 5 initially the program resets the controller then it checks for whether controller is in the configuration mode or not. When it enters into the configuration mode then it sets the CAN strobe pin to LOW and also set the baud rate. Now it changes to the normal mode, in this mode the hardware can read and write the CAN packets at same time. Then it checks if the controller has entered the normal mode, if yes then it can parallely receive and transmit the data packets. While transmitting the CAN packet it checks the TX FIFO full, if NO then it sends the data and checks for Tx OK flag is set, which indicates that the transaction is completed. Whereas while receiving the CAN packets it checks for the Rx OK flag, if this flag is set then it implies that CAN packet has been received. Then it reads the data and clears the flag so that it can receive the next CAN [2] packet if available. 2.2.2. Ethernet with GPIO application development in SDK Here in this application we are reading eight bit binary switch data through AXI GPIO as shown in the system block diagram Fig. 1. The switch is connected to PMOD1 and PMOD2 connector present on the board. The data is flowing from eight Bit Binary Switch → PMOD1 and PMOD2 → AXI GPIO → AXI bus Interconnects → ARM controller → Ethernet peripheral → LabVIEW Host application → Ethernet peripheral → ARM controller. The host application is reading the data at every one second and then displaying it into the waveform graphs. In future it can be connected to ADC to acquire data at some MHz range. As shown in the flowchart in Fig. 6 the program initializes the AXI GPIO and Ethernet driver. Then it sets the direction of the AXI GPIO [2] as input so that it can read the binary switches. Also it creates a new TCP structure, bind to the specified port, listen for the connection and finally use callback for the incoming connection. Once this is done it then checks for any client is requesting for data, if yes then it starts reading the eight bit binary switch data. Then
Fig. 8. UART or RS232 Application Programming Flowchart.
it transfers the received data to Ethernet send buffer and check whether TCP send buffer is empty or not. If yes it implies that data has been sent and then terminates the program. 2.2.3. Ethernet application development in SDK Here in this Ethernet [2] application we are generating 400 bytes of data in an array in SDK and then sending this data through Ethernet APIs whenever data is requested by the user though LabVIEW host application. As shown in the flowchart in Fig. 7 the program initializes the Ethernet driver. Then it creates a new TCP structure, bind to the specified port, listen for the connection and finally use callback for the incoming connection. Once this is done it then checks for any client is requesting for data, if yes then it sends 400 bytes of data packets to TCP send buffer and check whether TCP send buffer is empty or not. If yes it implies that data has been sent. And then it terminates the program.
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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Fig. 9. CAN Application GUI in LabVIEW.
Fig. 10. Ethernet with AXI GPIO Application GUI in LabVIEW.
2.2.4. UART application development In SDK In UART [2] application we are reading the data through UART port and then sending the data by adding 2 to the received data back to the host application through UART APIs. The following Fig. 8
shows the software application code development flowchart in SDK for UART. As shown in the above Fig. 8 the program initializes the UART Driver then it configures the UART in NORMAL mode and then after setting the baud rate and data format it checks for any received data
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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Fig. 11. Ethernet Application GUI in LabVIEW.
Fig. 12. UART Application GUI in LabVIEW.
byte in the Rx buffer if something is received. Then the program adds two to the received data byte and sends it back to the Tx Buffer. It then checks for the Tx buffer for empty, if YES then it indicates that the data byte has been transmitted.
2.3. Host application development in LabVIEW An integrated host application is made in LABVIEW it gives the user a facility to interface any one protocol out of CAN, Ethernet
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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With AXI GPIO, Ethernet and UART (RS232) at a time. In CAN application, user can read and write different parameters like GAIN, Filter etc also it can read the CAN packet whenever any module gets inserted into the system. In Ethernet with AXI GPIO application user is able to read the eight bit binary switch through the AXI GPIO IP, it reads the switch at every one second interval and plot the read data into the graph. In Ethernet application user can request the server to send the data and server sends 400 bytes of data packet back to the host through Ethernet and finally in the RS232 application user can send any data to the zc702 board and system returns back the data after adding two to the received data back to the host application as shown in the results.
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available IPs but for the custom made IPs also which reduces software development to a great extent. Zynq-7000 All Programmable SoCs (System On Chip) infuse customizable intelligence into today’s embedded systems to suit your unique application requirements. Since this chip has huge resources that can be used to make big systems. Its benefits are high speed performance, reduced PCB complexities, easily configurable and compact system design. In this project we have explored the interfacing protocols like CAN, Ethernet, UART and AXI GPIO therefore this project will be very useful for those who want to make any custom application on Zynq® SoC (xc7z020clg484-1) IC. Acknowledgments
3. Results As shown in Fig. 9 CAN application GUI is reading the CAN packets if any new module is inserted into or removed from the system. This application is also able to set parameters like GAIN, Filters etc. for the particular channel of the particular module. This application also logs the data into .xls file format after you stop the application. The Fig. 10 shows a snap shot of the Ethernet with AXI GPIO application GUI in LabVIEW. In this application user can set the IP address and port address of the Ethernet to start reading the eight bit GPIO (General Purpose input output) data from the PMOD1 and PMOD2 of zc702 board every one second and plot the read data into the graph. The Fig. 11 shows Ethernet application GUI in LabVIEW here user can set the IP address and port address of the Ethernet and request the server to send the data and server sends 400 bytes of data packet back to the host through Ethernet. We are able to read 400 bytes of data packet on a single click it shows that this application can be used to make high speed data acquisition system. The Fig. 12 shows UART Application GUI in LabVIEW here in this application we are sending some data through UART and ARM controller is reading that data through UART and the modify the received data by adding two to the received data back to the host. This is just confirm that data has been read by the ARM controller and not send back locally by the UART as we see in the loop back mode.
I convey my sincere thanks and gratitude to our division head Mrs. Rachana Rajpal for giving me an opportunity to works on this latest Zynq® SoC platform. I gratefully acknowledge with my sincere regards to Mr. Harshad D. Pujara for his advice, guidance and sharing experience. I would also like to thank Mr. Hitesh Mandaliya and Mr. Praveenlal for their kind help and support. Last but not the least I would also like to thanks the members of electronics group for their kind support, valuable help and quick co-operation to make this successful. References [1] Zynq® -7000 AP SoC Technical Reference Manual (UG585) http://www.xilinx. com/support/documentation/user guides/ug585-Zynq-7000-TRM.pdf. [2] Zynq® -7000 AP SoC Software Developers Guide (UG821) http://www.xilinx. com/support/documentation/user guides/ug821-zynq-7000-swdev.pdf. [3] Zynq® Concepts, Tools, and Techniques(UG873) http://www.xilinx.com/ support/documentation/sw manuals/xilinx14 1/ug873 zynq ctt.pdf. [4] Vivado Zynq® SpeedWay Workshops http://zedboard.org/course/developingZynq%C2%AE-7000-all-programmable-soc-software-vivado-20133-and201441. [5] Vivado Design Suite AXI Reference Guide http://www.xilinx.com/support/ documentation/ip documentation/axi ref guide/latest/ug1037-vivado-axireference-guide.pdf. [6] Creating a Custom IP Block in Vivado http://www.fpgadeveloper.com/2014/08/ creating-a-custom-ip-block-in-vivado.html. [7] ZC702 Evaluation Board User Guide http://www.xilinx.com/support/ documentation/boards and kits/zc702 zvik/xtp310-zc702-quickstart.pdf.
4. Conclusion Vivado tool has made the hardware chip designing very easy and not only this it guides you while creating the block diagram of our design, so you are less prone to commit any mistake. Software Development Kit (SDK) writes driver part not only for the already
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
ARTICLE IN PRESS
FUSION-8807; No. of Pages 7
Fusion Engineering and Design xxx (2016) xxx–xxx
Contents lists available at ScienceDirect
Fusion Engineering and Design journal homepage: www.elsevier.com/locate/fusengdes
Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control Abhijeet Kumar ∗ , Rachana Rajpal, Harshad Pujara, Hitesh Mandaliya, Praveenalal Edappala Institute For Plasma Research, Gandhinagar, Gujarat, India
h i g h l i g h t s • We have designed Universal Interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for Instrumentation & Control. This project is based on Zynq® -7000 family xc7z020clg484-1 chip.
• We explored the full design flow starting from the hardware development in Vivado to software development in SDK using APIs in C language and then interfacing the host application developed in LabVIEW.
• We also explored how to make custom IP with AXI bus interface in Vivado. • Useful for those who wants to make custom hardware on Zynq® SoC.
a r t i c l e
i n f o
Article history: Received 19 June 2015 Received in revised form 2 May 2016 Accepted 13 June 2016 Available online xxx Keywords: Zynq CAN Ethernet AXI-GPIO Custom-IP UART
a b s t r a c t This paper describes an application developed on the latest Zynq® -7000 All Programmable SoC (AP SoC) [1] devices which integrate the software programmability of an ARM® -based processor with the hardware programmability of an FPGA, on a single device. In this paper we have implemented application which uses various interfaces like CAN, RS-232, Ethernet and AXI GPIO, so that our host application running on PC in LabVIEW can communicates with any hardware which has at least any one of the available interface. Zynq-7000 All Programmable SoCs (System On Chip) infuse customizable intelligence into today’s embedded systems to suit your unique application requirements. This family of FPGA is meant for high end application because it has huge resources on single chip. It offers you to make your own custom hardware IP, in fact we have made our custom IP called myIP in our design. The beauty of this chip is that it can write drivers for your custom IP which has AXI bus layer attached. After exporting the hardware information to the Software Development Kit (SDK), the tool is able to write drivers for your custom IP. This simplifies your development to a great extent. In a way this application provides the universal interfacing option to user. User can also write the digital data on the GPIO (General Purpose Input Output) through LabVIEW Test application GUI. This project can be used for remote control and monitor the data over Ethernet or CAN network. © 2016 Elsevier B.V. All rights reserved.
1. Introduction There are many front end electronics and signal conditioning units for various diagnostic of SST-1 and ADITYA tokamak. These diagnostic electronics have different types of handshaking viz. RS232, CAN bus and Ethernet. So, there is a need of system which can control these parameters remotely at one place. To fulfill this requirement zc702 development board [7] is chosen to prototype
∗ Corresponding author. E-mail addresses: [email protected], [email protected] (A. Kumar).
a control system which can be able to control the parameters like Gain of amplifier, filter frequency etc remotely and can send the acquired data to the server. The client can any time see these data remotely for analysis purpose. 2. System block diagram As shown in Fig. 1 zc-702 board [7] is shown by dotted lines it consists of many interfaces but I have highlighted only those which I have used in my design. So, it has two PMOD connector, some switches, FMC connector and Zynq® IC (xc7z020clg484-1). This IC is mainly divided into two sections Processing System (PS) and Pro-
http://dx.doi.org/10.1016/j.fusengdes.2016.06.020 0920-3796/© 2016 Elsevier B.V. All rights reserved.
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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Fig. 1. System Block Diagram.
Fig. 2. Hardware implementation design flow diagram.
grammable Logic (PL) which is a FPGA. In the PL a AXI GPIO and a custom hardware IP [6] called my IP is made. AXI GPIO is used to read the eight binary switches through PMOD-1 and PMOD-2. And my IP is interfaced to read the switches and writes the data on the FMC connector. The project is mainly divided into three main sections. Firstly, the hardware implementation on Zynq® SoC in Vivado 2014.2 tool from Xilinx [3]. Secondly, software implementation in SDK 2014.2 [3] in C using APIs for ARM Cortex A9 processor and Third part is the host application GUI development in LabVIEW 2012. 2.1. Hardware implementation In Vivado Open Vivado [4] and then create the main project, now open a blank block diagram and add all the IPs needed in your design, you can also add any custom IP made by you. Do the connection between these IP blocks and then validate your design to check whether there is any error in the block design. If there is no error then generate the output product and then create a top level wrapper for your design and also add the user constrain file. Now do the synthesis and implementation of your design and then generate the bitstream as shown in Fig. 2. Now, export this bitstream to the SDK where actual software implementation is to be done. The Fig. 3 shows the hardware block diagram of the system. Here we have added the soft IPs available, for example, we have added Zynq® 7 Processing System Block and
AXI GPIO IP [5] block into the block diagram and a custom IP named as myIP. Rest all block it automatically adds into the system while doing connection, the beauty of the system is that it automatically guides you for the connection or you can manually connect the ports. 2.2. Software implementation in SDK After you export the hardware details to the SDK [4] then it will automatically create a hardware folder which will be having all the hardware related files. First step is to create FSBL i.e. First Stage Boot Loader and its BSP i.e. Board Support Package using template as shown in Fig. 4. This BSP will carry all the driver information. The beauty of this software is that it will write the device drivers for you. The tool is able to write the device driver because you have created or used that IPs which is having AXI bus interconnects stitched while creating the IPs. This makes our life very easy because you have to just see the documentation of the drivers given in system.mss file and use these APIs to write the application code. Finally build the project and create .elf file. 2.2.1. CAN application development in SDK Here a custom IP named myIP with AXI-lite bus interface is made as shown in Fig. 3. The signals monitored by the FPGA are those of module ID and the Electronics and Data Acquisition System modules which are inserted. For the purpose of testing, the insertion and
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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Fig. 3. Hardwar Block Diagram Created in Vivado.
Fig. 4. Software implementation design flow diagram.
Fig. 5. CAN Application Programming Flowchart.
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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Fig. 7. Ethernet Application Programming Flowchart.
Fig. 6. Ethernet with AXI-GPIO application Programming Flowchart.
removal of a module is imitated by the use of switches available on the board. The control signals are generated by the hardware and the parameter value which is to be set is brought out on the FMC connector. As shown in the flowchart in Fig. 5 initially the program resets the controller then it checks for whether controller is in the configuration mode or not. When it enters into the configuration mode then it sets the CAN strobe pin to LOW and also set the baud rate. Now it changes to the normal mode, in this mode the hardware can read and write the CAN packets at same time. Then it checks if the controller has entered the normal mode, if yes then it can parallely receive and transmit the data packets. While transmitting the CAN packet it checks the TX FIFO full, if NO then it sends the data and checks for Tx OK flag is set, which indicates that the transaction is completed. Whereas while receiving the CAN packets it checks for the Rx OK flag, if this flag is set then it implies that CAN packet has been received. Then it reads the data and clears the flag so that it can receive the next CAN [2] packet if available. 2.2.2. Ethernet with GPIO application development in SDK Here in this application we are reading eight bit binary switch data through AXI GPIO as shown in the system block diagram Fig. 1. The switch is connected to PMOD1 and PMOD2 connector present on the board. The data is flowing from eight Bit Binary Switch → PMOD1 and PMOD2 → AXI GPIO → AXI bus Interconnects → ARM controller → Ethernet peripheral → LabVIEW Host application → Ethernet peripheral → ARM controller. The host application is reading the data at every one second and then displaying it into the waveform graphs. In future it can be connected to ADC to acquire data at some MHz range. As shown in the flowchart in Fig. 6 the program initializes the AXI GPIO and Ethernet driver. Then it sets the direction of the AXI GPIO [2] as input so that it can read the binary switches. Also it creates a new TCP structure, bind to the specified port, listen for the connection and finally use callback for the incoming connection. Once this is done it then checks for any client is requesting for data, if yes then it starts reading the eight bit binary switch data. Then
Fig. 8. UART or RS232 Application Programming Flowchart.
it transfers the received data to Ethernet send buffer and check whether TCP send buffer is empty or not. If yes it implies that data has been sent and then terminates the program. 2.2.3. Ethernet application development in SDK Here in this Ethernet [2] application we are generating 400 bytes of data in an array in SDK and then sending this data through Ethernet APIs whenever data is requested by the user though LabVIEW host application. As shown in the flowchart in Fig. 7 the program initializes the Ethernet driver. Then it creates a new TCP structure, bind to the specified port, listen for the connection and finally use callback for the incoming connection. Once this is done it then checks for any client is requesting for data, if yes then it sends 400 bytes of data packets to TCP send buffer and check whether TCP send buffer is empty or not. If yes it implies that data has been sent. And then it terminates the program.
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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Fig. 9. CAN Application GUI in LabVIEW.
Fig. 10. Ethernet with AXI GPIO Application GUI in LabVIEW.
2.2.4. UART application development In SDK In UART [2] application we are reading the data through UART port and then sending the data by adding 2 to the received data back to the host application through UART APIs. The following Fig. 8
shows the software application code development flowchart in SDK for UART. As shown in the above Fig. 8 the program initializes the UART Driver then it configures the UART in NORMAL mode and then after setting the baud rate and data format it checks for any received data
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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Fig. 11. Ethernet Application GUI in LabVIEW.
Fig. 12. UART Application GUI in LabVIEW.
byte in the Rx buffer if something is received. Then the program adds two to the received data byte and sends it back to the Tx Buffer. It then checks for the Tx buffer for empty, if YES then it indicates that the data byte has been transmitted.
2.3. Host application development in LabVIEW An integrated host application is made in LABVIEW it gives the user a facility to interface any one protocol out of CAN, Ethernet
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020
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ARTICLE IN PRESS A. Kumar et al. / Fusion Engineering and Design xxx (2016) xxx–xxx
With AXI GPIO, Ethernet and UART (RS232) at a time. In CAN application, user can read and write different parameters like GAIN, Filter etc also it can read the CAN packet whenever any module gets inserted into the system. In Ethernet with AXI GPIO application user is able to read the eight bit binary switch through the AXI GPIO IP, it reads the switch at every one second interval and plot the read data into the graph. In Ethernet application user can request the server to send the data and server sends 400 bytes of data packet back to the host through Ethernet and finally in the RS232 application user can send any data to the zc702 board and system returns back the data after adding two to the received data back to the host application as shown in the results.
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available IPs but for the custom made IPs also which reduces software development to a great extent. Zynq-7000 All Programmable SoCs (System On Chip) infuse customizable intelligence into today’s embedded systems to suit your unique application requirements. Since this chip has huge resources that can be used to make big systems. Its benefits are high speed performance, reduced PCB complexities, easily configurable and compact system design. In this project we have explored the interfacing protocols like CAN, Ethernet, UART and AXI GPIO therefore this project will be very useful for those who want to make any custom application on Zynq® SoC (xc7z020clg484-1) IC. Acknowledgments
3. Results As shown in Fig. 9 CAN application GUI is reading the CAN packets if any new module is inserted into or removed from the system. This application is also able to set parameters like GAIN, Filters etc. for the particular channel of the particular module. This application also logs the data into .xls file format after you stop the application. The Fig. 10 shows a snap shot of the Ethernet with AXI GPIO application GUI in LabVIEW. In this application user can set the IP address and port address of the Ethernet to start reading the eight bit GPIO (General Purpose input output) data from the PMOD1 and PMOD2 of zc702 board every one second and plot the read data into the graph. The Fig. 11 shows Ethernet application GUI in LabVIEW here user can set the IP address and port address of the Ethernet and request the server to send the data and server sends 400 bytes of data packet back to the host through Ethernet. We are able to read 400 bytes of data packet on a single click it shows that this application can be used to make high speed data acquisition system. The Fig. 12 shows UART Application GUI in LabVIEW here in this application we are sending some data through UART and ARM controller is reading that data through UART and the modify the received data by adding two to the received data back to the host. This is just confirm that data has been read by the ARM controller and not send back locally by the UART as we see in the loop back mode.
I convey my sincere thanks and gratitude to our division head Mrs. Rachana Rajpal for giving me an opportunity to works on this latest Zynq® SoC platform. I gratefully acknowledge with my sincere regards to Mr. Harshad D. Pujara for his advice, guidance and sharing experience. I would also like to thank Mr. Hitesh Mandaliya and Mr. Praveenlal for their kind help and support. Last but not the least I would also like to thanks the members of electronics group for their kind support, valuable help and quick co-operation to make this successful. References [1] Zynq® -7000 AP SoC Technical Reference Manual (UG585) http://www.xilinx. com/support/documentation/user guides/ug585-Zynq-7000-TRM.pdf. [2] Zynq® -7000 AP SoC Software Developers Guide (UG821) http://www.xilinx. com/support/documentation/user guides/ug821-zynq-7000-swdev.pdf. [3] Zynq® Concepts, Tools, and Techniques(UG873) http://www.xilinx.com/ support/documentation/sw manuals/xilinx14 1/ug873 zynq ctt.pdf. [4] Vivado Zynq® SpeedWay Workshops http://zedboard.org/course/developingZynq%C2%AE-7000-all-programmable-soc-software-vivado-20133-and201441. [5] Vivado Design Suite AXI Reference Guide http://www.xilinx.com/support/ documentation/ip documentation/axi ref guide/latest/ug1037-vivado-axireference-guide.pdf. [6] Creating a Custom IP Block in Vivado http://www.fpgadeveloper.com/2014/08/ creating-a-custom-ip-block-in-vivado.html. [7] ZC702 Evaluation Board User Guide http://www.xilinx.com/support/ documentation/boards and kits/zc702 zvik/xtp310-zc702-quickstart.pdf.
4. Conclusion Vivado tool has made the hardware chip designing very easy and not only this it guides you while creating the block diagram of our design, so you are less prone to commit any mistake. Software Development Kit (SDK) writes driver part not only for the already
Please cite this article in press as: A. Kumar, et al., Universal interface on Zynq® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control, Fusion Eng. Des. (2016), http://dx.doi.org/10.1016/j.fusengdes.2016.06.020