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Update on Texas Instruments
Update on Texas Instruments After a protracted design cycle, Texas Instruments are pleased to announce the arrival of the 9 9 4 0 and 9 9 8 5 microcomputers. More 990 cards, 64k RAMs and 256k bubbles are also on the way
Looking back over TI's involvement in the microcomputer market their performance and credibility, compared with their promises and aspirations, leaves much to be desired. Announced products have failed to materialize on schedule, and not all of their existing devices have fired the imaginations of users. However, with the imminent arrival of the 9940 single-chip microcomputer, the bus-expandable 9985 and a range of new 990 cards, TI now has a significant offering.
DESIGN PROBLEMS The history of the 9440 has been long and eventful. It was originally conceived as a single-chip microcomputer containing a subset of instructions from TI's 16-bit 9900 microprocessor. Specifications on this device were being given to customers as long ago as the first quarter of 1977, yet it is only now that the chip looks like appearing. First, the chip was redefined to maintain compatibility with its parent, the 9900. Its original 58-strong instruction set was upgraded to include all 69 of the 9900, plus three others to aid single-chip applications. (Two for decimal add and decimal subtract allow easier application in situations demanding human interface. Another instruction makes interrupt programming more efficient by allowing the operand to be defined in the same word as the instruction.) Design and production problems followed. The chip was due out in the first quarter of 1978, but since then redesigns to correct logic errors have caused major delays. However, at the time of writing (October) one or two minor rectifications only are still necessary and the 9940 is promised in sample form during the first quarter of 1979. The 9940 looks very powerful. Indeed, one of its main criticisms is that it is too sophisticated for most
352
Table 1. Approximate volume prices of single-chip microcomputers Device 8049 3870 Z8 9940 6801
Volume 1Ok
lOOk
£8.80 £4.20 £5.70 £10 £12
£6.80 £4.20 £3.30
single-chips applications. Certainly most users will want only a subset of its features, but the main problem is that this market is extremely price sensitive and unwanted facilities only push up the price. TI are claiming it will sell at £10 for orders of 10000 quantity. A comparison with the current prices of some other similar devices is shown in Table 1. However, all these figures should be viewed carefully, as each order of this size is treated on its individual merits (how many other parts are bought from the same company, etc.) and without actually being a potential customer, it is difficult to get a manufacturer to quote realistic prices. Also, prices change quite substantially during the life of a device. Thus the cost of a new device such as the 6801 can be expected to drop over the next year as Motorola learn more about its production and increase the yield.
SUPERIOR POWER A considerable improvement in power over other devices is offered by the 9940. Figure 1 shows the architecture (see also inset 'Where it all started'). Key features are • 1d-bit instruction word • 2 kbytes ROM • 128 bytes RAM • hardware multiply/divide (unsigned) • 32 bits I/O • 4 prioritized interrupts • clock generation • 14-bit programmable counter • 16 programmable flags
• • •
single 5 V suppl,, power-down multiprocessor interfacing
Comparing this with the 8048 fiom Intel, one of the market leaders amongs single-chip microcomputers, one can see that the 9940 has a clear advantage in many applications. For timing tasks the 9940 has a 14-bit timer/ event counter; there is only an 8-bit facility on the 8048. Resolution is likewise much greater. In the area ~l I/O control, the 9940 has 32 individually controlled bits compared with 24 un the 8048. It also h.i~ four vcclt)rcd interrupts as opposed tu a single inter rupt on the Intel device. Calculalion capability is far superior to most t>thc'l devicc~ as the 9940 has 16-bit opel ations and fast multipl', divide.
EPROM FOR PROTOTYPING Two ~elsions ~fl the chip ~ill bc available: the 9940L, with EPROM onchip fur prutot~,ping, and the 9940M, a mask-programmable vcr,,i~m fur mass-production. The chips ~,,ill be supplied in 40-pin packages. At present 2 kbytcs ~1 ROM
0308 5 9 5 3 / 7 8 / 0 6 0 3 5 2 - - 0 4 $02.00 © 1978 IPC Business Press
micropruccssoi,~ and micrusysiclns
Calculation capability is important in many control applications and this is implemented in most other chips by software, taking up valuable onchip ROM space, and of course taking much more time, so this feature should prove very useful.
for jobs such as AC motor control, and a mechanism for multiprocessing allows it to be used easily as a slave processor in multiprocessors. 32 I/O bits together with the CRU (communications register unit) mechanism provide a powerful interface capability. The 9440 can be connected to the standard CRU peripheral members of the 9900 support circuits
DEVELOPMENT
• 9901 I/O interface • 9902 UART • 9903 USART • 9909 high-speed serial controller • 9914 general-purpose interface bus controller Under development are more devices including: 9909 floppy-disc controller, 9911 DMA controller, 9912 single chip modem, 9913 A/D converter and 9915 RAM refresh. FEATURES
Hardware multiplication and division is something that only the 9940 single chip has. The hardware performs unsigned multiplication in only 32/is. However, for signed multiplications, some software is necessary and the time taken to process a sum goes up significantly.
~
AIDS
Software development using the 9940E is catered for by the TM9901 40DS design aid. It costs £2183 in the UK and comprises: an assembler, debug monitor, EPROM programmer (for the 9940E memory), and in-circuit emulation. The assembler is of the single-pass, iine-by-line type. As each source line is assembled, the reuslting object code is placed with the RAM development system. The monitor is TIBUG II, a version of TI standard monitor. Emulation capability, is provided by TISE (trial in-system emulation) which allows users to test the software in the target system via a cable. 9985
The major differences between the 9940 and its 9985 twin are
T°I I
IGenerol-purpose~
!
I
1 g3
! I
:
!-l;
7
--
L__
!:!- 1 : h6:
J
.............
7[ .
_~i.~'-
-"~"
cic:°:i oc, P.oo --
I RAM/~PRO" 1 ~ j I AOOR~.~ .j
.... .~,(IN}
{OUT)
I"
"
. . . . .
Key to logic blocks ALUArithmetic A Temporary B Temporary C Temporary
logic unit DECDecrementer
register register register CB Configuration bits
MA Memory address register MPSI Multiprocessor system interface register S/D Source/destinationoperandcontrol
Block diagram of the 9940 single-chip microcomputer
vol 2 no 6 december 78
SC Shift counter SD Source or destination registeraddress PC Program counter WP Workspacepointer
9985 256 bytes RAM S interrupts no power-down expandable to 64 kbits I/O
Like the 94,J,0, the 9985 comes in a 40pin package. It has an exact copy of the 9940's instruction set but has a separate bus structure. All members of the 9900 family of peripheral circuits are compatible with the 9985. TMS
1000 IN CMOS
True success has been achieved by TI with their first single-chip microcomputer TMS 1000. This is a single 4-bit device with lkbyte ROM/64 bytes RAM onchip. Its main attribute however is its low cost, coming down to as little as £1 in high volumes. TI shipped 2.8 million units last year, and confidently expect to at least double this figure for 1978. This figure may well rise even further now that CMOS versions have been announced. Higher speed and much decreased power consumption will make the chips more attractive for many applications. Estimated costs for CMOS parts are approximately 30% above the standard devices. SINGLE-BOARD
Mulhplexer ond I/O buffer A-A
CRu IN
9940 • 128 bytes RAM • 4interrupts • power down • 256 bits I/O maximum
COMPUTERS
Ready-built cards are playing an ever increasing role in the microcomputer world, as they can provide an effective solution for low-volume applications. These cards should allow designers to select the correct units with amounts of computing power, I/O and memory, to fit the job neatly. Other cards needed to complete the system, such as A/D converters, are then added, along with a power supply and box for the finished product. Project development time can be saved by using these modules, because most of the hardware/PCB design and test time is unnecessary. Designers perhaps need to add one specialized card for their particular interface needs, or customize the circuitry somewhat, and then write the software for the full system. Texas Instruments' main thrust in this direction is the 990 range of cards, designed at the Semiconductor Division in Houston, Texas; there was an earlier UK-designed board, the Micro 99, but this has now been dropped. Several boards have been added recently to this range, and many more are in the definition stage.
353
NEW BOARDS An expanding range of cards continually increases the attraction of this design approach. To help this happen, ]exas Instruments are also to publish a definition of their ]O0-pin 990 bus, although some manufacturers are already providing compatible cards. (Analogic have announced several analogue I/O systems and Analog Devices also have a range of I/O subsystems). A CPU board, TM990/lO1M, has been designed for multiprocessing applications requiring a good deal of computing power. Based on the 9900, it has 1 kword RAM (expandable to 2k), ] kword EPROM (expandable to 4k), 9901 programmable system interface (up to 16 I/O lines), twin 9902 serial communications controllers, and DMA to onboard memory. fwo further additions to the CPU range will be the 140M module, which is based on the single-chip 9940E, and the 185M which uses the busexpandable 9985 processor. (These two will not be available until early 1979.) New cards for interfacing, will be available shortly. A floppy-disc controller for doublesided double-density discs will be announced, so will a card for interfacing to the IEEE 488 bus. A/D and D/A converters and other interfaces for process control (high and low voltage inputs, opto coupled inputs) will follow. Two more dynamic memory cards with 12 and 32 kwords are also being manufactured. For the educational sector, TI are making a'Cailable , the TM990/189M University Board. It will cost under £200 and will have a 9980 CPU with 4k ROM containing the TIBUG monitor, 2k RAM, 10-digit sevensegment displays, 45-key alphanumeric keyboard, cassette interface, 10 I/O lines, loudspeaker and tutorial course notes. For very high performance, a twocard LSI implementation of the 481 bit-slice series will be available in the first quarter of 1979. It has the full 990 minicomputer instruction set plus 18 new opcodes with full floatingpoint capability, and gives a 3 5 times increase in throughput over the 9900.
EUROCARD VERSIONS 11 arc also planning to make Eurocard versions of some 990 cards, and have begun to set up a manufacturing olant at their Bedford, UK factory.
354
l l's 64# dynamic RAM
SOFTWARE In the area of high-level languages, it seems as if TI's major thrust will be towards PASCAL. They hope to provide both interpretive and compiling versions of the language on the AMPL development station. For the 990 boards, TI ha~e announced a version of the popular language, BASIC. Called Power-BASIC, this software comes in three forms. An 8 kbyte version comes in ROM and is designed to explore applications. This operates on 100M or 101M microcomputer modules plus keyboard. A larger version, Development PowerBASIC, needs 12 kbytes or memory space and offers an expanded capability for design development, debug and EPROM programming. Users need an additional board, 302 (see below) for this option. Finally, Configurable Power-BASIC is a floppy disc-based version, which includes floppy-disc file support, and a routine which reduces the size of finished programs for fast execution time. It does this by comparing the user program with the keyword table and deleting any words not used for that particular application. In addition to this, all three versions of power BASIC are multiuser, support 48-bit precision arithmetic, and are multi-tasking for use in industrial control. The extra board, TM990/302, needed by the development power BASIC, is for software development. It has ROM space and RAM onboard. Power-BASIC ROMs can be simply fitted. The board also has a two-pass symbolic assembler, two Kansas City audiocassette interfaces and an EIA terminal interface.
MEMORY MOVEMENTS Texas Instruments are the first to announce a single-rail 64k dynamic
RAM. Called the 4164, it will have a single %/power supply and has been designed to be pincurnpatible with the 16k RAM. Sample quantities ,ire promised for late 1978, with production starting in mid-1979. The chips are likely to oust £80 each at first, but this should fall to [4 by 1981. Reliability is a ke~,,wuld in the 4164'~ specification: an increased store charge and reduced alpha-ray ionization from package materials should mean fewer single-bit errors. Heat power dissipation will be lower: up to 60% of the 16k RAM. Access time is 150 ns, although a ]O0ns version is predicted, and cycle time is below 250ns. Refresh time is 4ms. As the 4164 is refresh compatible with the 16k RAM, the basic refresh controller timing does not require major changes. The only provision required is for an 8-bit refresh counter/ multiplexer when upgrading to 64k from a 16k system. Photomasks for volume production will be manufactured using electronbeam equipment to control geometries to better than 0.25/~m. Projection printing will avoid direct contact between photomask and wafer. Additionally, geometries at several critical levels of the 4164 are 2.5 to 3,urn, demanding use of positive photoresist for resolution and elineation control as well as dry processing at critical levels. f l hope to manufacture 20M devices a year by 1981, and with only 5 min ot labour required to produce each device, forecast that world supply can be satisfied by a workforce of
1000. Bubbles Samples of the 256k bubble memory for serial storage have been scheduled for the end of 1978. Priced at about $500 each, the TIB0303 will have a data capacity of 254 688 bits (224 loops cut down the possible 286 524bit capacity). The device uses block-replicate architecture. Data bits are written into the write track and exchanged with stored data in the minor [oops via swap gates. Data blocks are replicated simultaneously at minor loop and output track junctions, rather than by the serial duplication that is characteristic of major/minor loop architecture. Consequently, power-down cycle time is reduced from 12.8 ms in the 92k major/minor loop configuration to 12.5 ~s.
microprocessors and microsystenls
Other features include: advanced asymmetric chevron design for improved bubble propagation and transfer, merged data that allows a continuous flow of data bits at the read track, and a dedicated loop for storing onchip redundancy information and address synchronization. Performance specifications at 100 kHz are an average access time of 7.3 ms for the first bit of the 224-bit page and a typical power consumption of 0.9 W for continuous operation. A datamerge function allows a read data rate of 100 kbit/s. Operating temperature is 0 ° to 50°C with nonvolatile storage range of 40 ° to85°C. Bubble control functions such as generate, swap, block replicate and redundancy replicate are executed by
providing current pulses through the appropriate control elements on the chip. The bubble chip is comprised of a gadolinium-gallium garnet substrate upon which a magnetic epitaxial film is grown. Patterns of permalloy metal are deposited on the epitazial film to define the path of the bubble domains in the presence of a rotating magnetic field. As the field rotates, the bubble domains move under the permalloy pattern in shift register fashion. Taking a systems approach, TI will offer a family of interface and control circuits for the TIB0303 in the second quarter of 1979. These will include the TMS9922 and TMS9923 controllers, function timing generator, function driver, two coil drivers and sense
amplifier. An evaluation subassembly consisting of a bubble device and support circuitry will be available in late 1978. The TIB0303 is in a 20-pin package, measuring 1.2 X 1.2 X 0.4 in. The package contains the bubble chip surrounded by two orthogonal coils that provide the rotating magnetic field, a permanent magnet set and a magnetic shield to protect data from external fields. Other memory products available from TI include the 32k EPROM (announced in Microprocessors and microsystems Vol 2 No 5 (October 1978) p311) and two 4k Schottky PROMs: the SN54S/745476 and the SN54S 74S477. The 4016 16k static RAM should now be available.
WHERE IT ALL STARTED The 9940 and 9985 are derived from TI's first microprocessor, the 9900. This 16-bit CPU is an LSI implementation of the 990 minicomputer. It has the same instruction set as its parent, comprising 69 instructions, 16 general-purpose registers, seven addressing modes, and features hardware multiply,.'divide. A notable capability of the processor is its memory to memory architecture. Effectively', this allows extremely, fast context switching, for example when an interrupt is generated or subroutine called for. This is achieved by locating the workspaces offchip in memory. Thus to change context, the 9900's pointer is simply moved and the time penalty of stacking is not encountered. Another feature of the architecture is the CRU (communications register unit). This provides a third I/O capability in conjunction with DMA and memory-mapped techniques. It is an onchip multiplexer which allows via a serial line. This saves on microgeneration 9900 with significant archicheap interfacing by providing an processor pins and circuit wiring. tectural changes. It will be announced ability to address an external port TI are currently developing a second- during 1979.
vol 2 no 6 december 78
355
Looking back over TI's involvement in the microcomputer market their performance and credibility, compared with their promises and aspirations, leaves much to be desired. Announced products have failed to materialize on schedule, and not all of their existing devices have fired the imaginations of users. However, with the imminent arrival of the 9940 single-chip microcomputer, the bus-expandable 9985 and a range of new 990 cards, TI now has a significant offering.
DESIGN PROBLEMS The history of the 9440 has been long and eventful. It was originally conceived as a single-chip microcomputer containing a subset of instructions from TI's 16-bit 9900 microprocessor. Specifications on this device were being given to customers as long ago as the first quarter of 1977, yet it is only now that the chip looks like appearing. First, the chip was redefined to maintain compatibility with its parent, the 9900. Its original 58-strong instruction set was upgraded to include all 69 of the 9900, plus three others to aid single-chip applications. (Two for decimal add and decimal subtract allow easier application in situations demanding human interface. Another instruction makes interrupt programming more efficient by allowing the operand to be defined in the same word as the instruction.) Design and production problems followed. The chip was due out in the first quarter of 1978, but since then redesigns to correct logic errors have caused major delays. However, at the time of writing (October) one or two minor rectifications only are still necessary and the 9940 is promised in sample form during the first quarter of 1979. The 9940 looks very powerful. Indeed, one of its main criticisms is that it is too sophisticated for most
352
Table 1. Approximate volume prices of single-chip microcomputers Device 8049 3870 Z8 9940 6801
Volume 1Ok
lOOk
£8.80 £4.20 £5.70 £10 £12
£6.80 £4.20 £3.30
single-chips applications. Certainly most users will want only a subset of its features, but the main problem is that this market is extremely price sensitive and unwanted facilities only push up the price. TI are claiming it will sell at £10 for orders of 10000 quantity. A comparison with the current prices of some other similar devices is shown in Table 1. However, all these figures should be viewed carefully, as each order of this size is treated on its individual merits (how many other parts are bought from the same company, etc.) and without actually being a potential customer, it is difficult to get a manufacturer to quote realistic prices. Also, prices change quite substantially during the life of a device. Thus the cost of a new device such as the 6801 can be expected to drop over the next year as Motorola learn more about its production and increase the yield.
SUPERIOR POWER A considerable improvement in power over other devices is offered by the 9940. Figure 1 shows the architecture (see also inset 'Where it all started'). Key features are • 1d-bit instruction word • 2 kbytes ROM • 128 bytes RAM • hardware multiply/divide (unsigned) • 32 bits I/O • 4 prioritized interrupts • clock generation • 14-bit programmable counter • 16 programmable flags
• • •
single 5 V suppl,, power-down multiprocessor interfacing
Comparing this with the 8048 fiom Intel, one of the market leaders amongs single-chip microcomputers, one can see that the 9940 has a clear advantage in many applications. For timing tasks the 9940 has a 14-bit timer/ event counter; there is only an 8-bit facility on the 8048. Resolution is likewise much greater. In the area ~l I/O control, the 9940 has 32 individually controlled bits compared with 24 un the 8048. It also h.i~ four vcclt)rcd interrupts as opposed tu a single inter rupt on the Intel device. Calculalion capability is far superior to most t>thc'l devicc~ as the 9940 has 16-bit opel ations and fast multipl', divide.
EPROM FOR PROTOTYPING Two ~elsions ~fl the chip ~ill bc available: the 9940L, with EPROM onchip fur prutot~,ping, and the 9940M, a mask-programmable vcr,,i~m fur mass-production. The chips ~,,ill be supplied in 40-pin packages. At present 2 kbytcs ~1 ROM
0308 5 9 5 3 / 7 8 / 0 6 0 3 5 2 - - 0 4 $02.00 © 1978 IPC Business Press
micropruccssoi,~ and micrusysiclns
Calculation capability is important in many control applications and this is implemented in most other chips by software, taking up valuable onchip ROM space, and of course taking much more time, so this feature should prove very useful.
for jobs such as AC motor control, and a mechanism for multiprocessing allows it to be used easily as a slave processor in multiprocessors. 32 I/O bits together with the CRU (communications register unit) mechanism provide a powerful interface capability. The 9440 can be connected to the standard CRU peripheral members of the 9900 support circuits
DEVELOPMENT
• 9901 I/O interface • 9902 UART • 9903 USART • 9909 high-speed serial controller • 9914 general-purpose interface bus controller Under development are more devices including: 9909 floppy-disc controller, 9911 DMA controller, 9912 single chip modem, 9913 A/D converter and 9915 RAM refresh. FEATURES
Hardware multiplication and division is something that only the 9940 single chip has. The hardware performs unsigned multiplication in only 32/is. However, for signed multiplications, some software is necessary and the time taken to process a sum goes up significantly.
~
AIDS
Software development using the 9940E is catered for by the TM9901 40DS design aid. It costs £2183 in the UK and comprises: an assembler, debug monitor, EPROM programmer (for the 9940E memory), and in-circuit emulation. The assembler is of the single-pass, iine-by-line type. As each source line is assembled, the reuslting object code is placed with the RAM development system. The monitor is TIBUG II, a version of TI standard monitor. Emulation capability, is provided by TISE (trial in-system emulation) which allows users to test the software in the target system via a cable. 9985
The major differences between the 9940 and its 9985 twin are
T°I I
IGenerol-purpose~
!
I
1 g3
! I
:
!-l;
7
--
L__
!:!- 1 : h6:
J
.............
7[ .
_~i.~'-
-"~"
cic:°:i oc, P.oo --
I RAM/~PRO" 1 ~ j I AOOR~.~ .j
.... .~,(IN}
{OUT)
I"
"
. . . . .
Key to logic blocks ALUArithmetic A Temporary B Temporary C Temporary
logic unit DECDecrementer
register register register CB Configuration bits
MA Memory address register MPSI Multiprocessor system interface register S/D Source/destinationoperandcontrol
Block diagram of the 9940 single-chip microcomputer
vol 2 no 6 december 78
SC Shift counter SD Source or destination registeraddress PC Program counter WP Workspacepointer
9985 256 bytes RAM S interrupts no power-down expandable to 64 kbits I/O
Like the 94,J,0, the 9985 comes in a 40pin package. It has an exact copy of the 9940's instruction set but has a separate bus structure. All members of the 9900 family of peripheral circuits are compatible with the 9985. TMS
1000 IN CMOS
True success has been achieved by TI with their first single-chip microcomputer TMS 1000. This is a single 4-bit device with lkbyte ROM/64 bytes RAM onchip. Its main attribute however is its low cost, coming down to as little as £1 in high volumes. TI shipped 2.8 million units last year, and confidently expect to at least double this figure for 1978. This figure may well rise even further now that CMOS versions have been announced. Higher speed and much decreased power consumption will make the chips more attractive for many applications. Estimated costs for CMOS parts are approximately 30% above the standard devices. SINGLE-BOARD
Mulhplexer ond I/O buffer A-A
CRu IN
9940 • 128 bytes RAM • 4interrupts • power down • 256 bits I/O maximum
COMPUTERS
Ready-built cards are playing an ever increasing role in the microcomputer world, as they can provide an effective solution for low-volume applications. These cards should allow designers to select the correct units with amounts of computing power, I/O and memory, to fit the job neatly. Other cards needed to complete the system, such as A/D converters, are then added, along with a power supply and box for the finished product. Project development time can be saved by using these modules, because most of the hardware/PCB design and test time is unnecessary. Designers perhaps need to add one specialized card for their particular interface needs, or customize the circuitry somewhat, and then write the software for the full system. Texas Instruments' main thrust in this direction is the 990 range of cards, designed at the Semiconductor Division in Houston, Texas; there was an earlier UK-designed board, the Micro 99, but this has now been dropped. Several boards have been added recently to this range, and many more are in the definition stage.
353
NEW BOARDS An expanding range of cards continually increases the attraction of this design approach. To help this happen, ]exas Instruments are also to publish a definition of their ]O0-pin 990 bus, although some manufacturers are already providing compatible cards. (Analogic have announced several analogue I/O systems and Analog Devices also have a range of I/O subsystems). A CPU board, TM990/lO1M, has been designed for multiprocessing applications requiring a good deal of computing power. Based on the 9900, it has 1 kword RAM (expandable to 2k), ] kword EPROM (expandable to 4k), 9901 programmable system interface (up to 16 I/O lines), twin 9902 serial communications controllers, and DMA to onboard memory. fwo further additions to the CPU range will be the 140M module, which is based on the single-chip 9940E, and the 185M which uses the busexpandable 9985 processor. (These two will not be available until early 1979.) New cards for interfacing, will be available shortly. A floppy-disc controller for doublesided double-density discs will be announced, so will a card for interfacing to the IEEE 488 bus. A/D and D/A converters and other interfaces for process control (high and low voltage inputs, opto coupled inputs) will follow. Two more dynamic memory cards with 12 and 32 kwords are also being manufactured. For the educational sector, TI are making a'Cailable , the TM990/189M University Board. It will cost under £200 and will have a 9980 CPU with 4k ROM containing the TIBUG monitor, 2k RAM, 10-digit sevensegment displays, 45-key alphanumeric keyboard, cassette interface, 10 I/O lines, loudspeaker and tutorial course notes. For very high performance, a twocard LSI implementation of the 481 bit-slice series will be available in the first quarter of 1979. It has the full 990 minicomputer instruction set plus 18 new opcodes with full floatingpoint capability, and gives a 3 5 times increase in throughput over the 9900.
EUROCARD VERSIONS 11 arc also planning to make Eurocard versions of some 990 cards, and have begun to set up a manufacturing olant at their Bedford, UK factory.
354
l l's 64# dynamic RAM
SOFTWARE In the area of high-level languages, it seems as if TI's major thrust will be towards PASCAL. They hope to provide both interpretive and compiling versions of the language on the AMPL development station. For the 990 boards, TI ha~e announced a version of the popular language, BASIC. Called Power-BASIC, this software comes in three forms. An 8 kbyte version comes in ROM and is designed to explore applications. This operates on 100M or 101M microcomputer modules plus keyboard. A larger version, Development PowerBASIC, needs 12 kbytes or memory space and offers an expanded capability for design development, debug and EPROM programming. Users need an additional board, 302 (see below) for this option. Finally, Configurable Power-BASIC is a floppy disc-based version, which includes floppy-disc file support, and a routine which reduces the size of finished programs for fast execution time. It does this by comparing the user program with the keyword table and deleting any words not used for that particular application. In addition to this, all three versions of power BASIC are multiuser, support 48-bit precision arithmetic, and are multi-tasking for use in industrial control. The extra board, TM990/302, needed by the development power BASIC, is for software development. It has ROM space and RAM onboard. Power-BASIC ROMs can be simply fitted. The board also has a two-pass symbolic assembler, two Kansas City audiocassette interfaces and an EIA terminal interface.
MEMORY MOVEMENTS Texas Instruments are the first to announce a single-rail 64k dynamic
RAM. Called the 4164, it will have a single %/power supply and has been designed to be pincurnpatible with the 16k RAM. Sample quantities ,ire promised for late 1978, with production starting in mid-1979. The chips are likely to oust £80 each at first, but this should fall to [4 by 1981. Reliability is a ke~,,wuld in the 4164'~ specification: an increased store charge and reduced alpha-ray ionization from package materials should mean fewer single-bit errors. Heat power dissipation will be lower: up to 60% of the 16k RAM. Access time is 150 ns, although a ]O0ns version is predicted, and cycle time is below 250ns. Refresh time is 4ms. As the 4164 is refresh compatible with the 16k RAM, the basic refresh controller timing does not require major changes. The only provision required is for an 8-bit refresh counter/ multiplexer when upgrading to 64k from a 16k system. Photomasks for volume production will be manufactured using electronbeam equipment to control geometries to better than 0.25/~m. Projection printing will avoid direct contact between photomask and wafer. Additionally, geometries at several critical levels of the 4164 are 2.5 to 3,urn, demanding use of positive photoresist for resolution and elineation control as well as dry processing at critical levels. f l hope to manufacture 20M devices a year by 1981, and with only 5 min ot labour required to produce each device, forecast that world supply can be satisfied by a workforce of
1000. Bubbles Samples of the 256k bubble memory for serial storage have been scheduled for the end of 1978. Priced at about $500 each, the TIB0303 will have a data capacity of 254 688 bits (224 loops cut down the possible 286 524bit capacity). The device uses block-replicate architecture. Data bits are written into the write track and exchanged with stored data in the minor [oops via swap gates. Data blocks are replicated simultaneously at minor loop and output track junctions, rather than by the serial duplication that is characteristic of major/minor loop architecture. Consequently, power-down cycle time is reduced from 12.8 ms in the 92k major/minor loop configuration to 12.5 ~s.
microprocessors and microsystenls
Other features include: advanced asymmetric chevron design for improved bubble propagation and transfer, merged data that allows a continuous flow of data bits at the read track, and a dedicated loop for storing onchip redundancy information and address synchronization. Performance specifications at 100 kHz are an average access time of 7.3 ms for the first bit of the 224-bit page and a typical power consumption of 0.9 W for continuous operation. A datamerge function allows a read data rate of 100 kbit/s. Operating temperature is 0 ° to 50°C with nonvolatile storage range of 40 ° to85°C. Bubble control functions such as generate, swap, block replicate and redundancy replicate are executed by
providing current pulses through the appropriate control elements on the chip. The bubble chip is comprised of a gadolinium-gallium garnet substrate upon which a magnetic epitaxial film is grown. Patterns of permalloy metal are deposited on the epitazial film to define the path of the bubble domains in the presence of a rotating magnetic field. As the field rotates, the bubble domains move under the permalloy pattern in shift register fashion. Taking a systems approach, TI will offer a family of interface and control circuits for the TIB0303 in the second quarter of 1979. These will include the TMS9922 and TMS9923 controllers, function timing generator, function driver, two coil drivers and sense
amplifier. An evaluation subassembly consisting of a bubble device and support circuitry will be available in late 1978. The TIB0303 is in a 20-pin package, measuring 1.2 X 1.2 X 0.4 in. The package contains the bubble chip surrounded by two orthogonal coils that provide the rotating magnetic field, a permanent magnet set and a magnetic shield to protect data from external fields. Other memory products available from TI include the 32k EPROM (announced in Microprocessors and microsystems Vol 2 No 5 (October 1978) p311) and two 4k Schottky PROMs: the SN54S/745476 and the SN54S 74S477. The 4016 16k static RAM should now be available.
WHERE IT ALL STARTED The 9940 and 9985 are derived from TI's first microprocessor, the 9900. This 16-bit CPU is an LSI implementation of the 990 minicomputer. It has the same instruction set as its parent, comprising 69 instructions, 16 general-purpose registers, seven addressing modes, and features hardware multiply,.'divide. A notable capability of the processor is its memory to memory architecture. Effectively', this allows extremely, fast context switching, for example when an interrupt is generated or subroutine called for. This is achieved by locating the workspaces offchip in memory. Thus to change context, the 9900's pointer is simply moved and the time penalty of stacking is not encountered. Another feature of the architecture is the CRU (communications register unit). This provides a third I/O capability in conjunction with DMA and memory-mapped techniques. It is an onchip multiplexer which allows via a serial line. This saves on microgeneration 9900 with significant archicheap interfacing by providing an processor pins and circuit wiring. tectural changes. It will be announced ability to address an external port TI are currently developing a second- during 1979.
vol 2 no 6 december 78
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