Vapour-deposited silicon dioxide for device applications

Thin Solid Films, 22 (1974) 245-253 © Elsevier Sequoia S.A., Lausanne---Printed in Switzerland

245

VAPOUR-DEPOSITED SILICON DIOXIDE FOR DEVICE APPLICATIONS

F. LEUENBERGER Centre Electronique Horloger S.A., Neuchrtel (Switzerland) (Received December 31, 1973; accepted February 5, 1974)

Silicon dioxide layers deposited from the vapour phase at low temperatures are extensively applied in integrated circuit technology. Applications include doped oxide diffusion sources, protective layers and cross-over insulators in multilevel metallization systems. In this paper we show the feasibility of obtaining a SiO2-Si interface whose electrical characteristics closely approach those of thermally grown SiO2-Si sandwich structures. Interface state densities lying in the low l01° crn -2 eV -1 range have been determined from quasi-static C(I1) measurements. The results of excess noise measurements made on deposited gate oxide and thermally grown gate oxide MOSFETs are in reasonable agreement with the interface state density measurements. C(V) dispersion and C(V) hysteresis measurements prior to and after exposure to 107 tad of 6°C0 y radiation are also presented. Potential applications of low temperature vapour-deposited oxides include the silicon on insulating substrate (SOS) technology where it is generally desirable to minimize high temperature processing steps. Other applications are in the field of impurity profile determinations using the MOS capacitor method. In these applications one desires to measure the original profile without having to deal with the additional complication of the diffusion and redistribution phenomena that occur unavoidably during high temperature thermal oxide growth.

I. INTRODUCTION

Doped oxides deposited from the vapour phase have been used successfully as impurity sources in solid-solid diffusion processes 1, while doped or pure deposited oxides have found diverse applications, such as for scratch protection and as insulators in multilayer metallization systems2. To the author's knowledge, no applications of oxides deposited from the vapour phase at low temperatures onto an active device surface, e.g. as the gate oxide of a MOSFET, have been reported. These applications seem to be the preserve of thermally grown oxides. State of the art processes allow the growth of thermal oxides characterized by a very small mobile oxide charge (e.g. less than 50 mV drift u n d e r 10 6 V c m -1 at 200°C) and a very small fixed positive oxide charge and

246

F. L E U E N B E R G E R

interface state density. A typical value of 5x 101° states cm -2 eV -1 around mid-gap can be reproducibly obtained on a (100) silicon surface. A number of authors 3-6 have reported convincing evidence of a correlation between the density of interface states and the level of excess (l/J) noise. Careful oxide growth and annealing techniques have enabled us to fabricate p-channel MOSFETs which showed no 1If noise in the 15 Hz-50 kHz frequency range 7. Dielectric layers obtained by the decomposition of silane at low temperatures (380°-450 °C) would be very useful if their interface properties were essentially identical to those of the thermal oxide-silicon system. Possible applications include the following. (1) SOS technology. It is highly desirable to minimize high temperature steps in order to reduce the amount of diffusion of impurities from the insulating substrate into the silicon layer. In general, one also desires to reduce or even eliminate the consumption of silicon which occurs unavoidably during the thermal growth of silicon dioxide. (2) The evaluation of as diffused or as implanted impurity profiles, as well as epitaxial layer impurity profiles, using the MOS capacitor method 8' 9 (3) The conservation of specific implanted profiles in device applications. In this paper we shall show, by comparing a number of relevant parameters, that it is indeed feasible to produce SiO2 layers by the decomposition of silane at low temperatures that have interface properties approaching those of state of the art thermally grown oxide layers. As will be shown, the results depend critically on the pre-deposition surface preparation. II, SAMPLE P R E P A R A T I O N

Identical wafer cleaning procedures were applied both for samples to be oxidized thermally and for samples to be coated with a vapour-deposited oxide: (a) organic cleaning; (b) boiling in HNOa-H2SO 4 (1:1) for 10 rain; (c) a rinse in de-ionized water and spin dry; (d) a dip in dilute HF (1:5) for 1 min; (e) a rinse in de-ionized water; (f) boiling in doubly distilled water, 3 × 10 rain; (g) spin dry. All substrates were 5 ~ cm n-type silicon wafers with (100) orientation. An alternative cleaning sequence consisted of steps (a) to (e) only. The thermal oxide was grown in an induction-heated water-cooled double wall reactor at 1100 °C. Immediately after growing the 0.1 ~m thick oxide, the wafers were subjected to a 20 rain in situ annealing step in helium at the oxidation temperature. Application of this annealing step consistently led to a reduction of the densities of fixed oxide charge and fast interface states. It has been suggested x° that this might be due to traces of hydrogen and/or water vapour in the gaseous helium source. The vapour oxide, O.1 lain thick, was deposited in a double rotation reactor according to the well-known reaction

VAPOUR-DEPOSITED S i O 2 FOR DEVICE APPLICATIONS

247

SiH,~ (g) + 02 (g)~SiO2 (s) + H2T(g) The deposition temperature and rate were 450 °C and 830 /~ min -1, respectively. Following the deposition, the wafers were densified in helium at 1100 °C for 20 min. Two kinds of field electrodes were evaporated: 7000 A of aluminium, or 2500 A of molybdenum followed by 5000/~ of gold. The aluminium and molybdenum were electron-gun evaporated whereas the gold was evaporated from a tungsten boat. After a metal etch and final cleaning, all the wafers were annealed in nitrogen at 400°C for I h. III. ELECTRICAL MEASUREMENTS AND RESULTS

Using a lock-in amplifier as the signal detector, capacitance-voltage measurements were performed in the 4 Hz-100 kHz frequency range. It is seen in Fig. 1 that essentially identical results are obtained for thermal oxides and for silane oxides. In fact, the differences in fiat band voltages range from 50 mV to 200 mV. The hardly detectable dispersion in the C(V) curves indicates low levels of interface state densities for all the four combinations of insulators and electrode metals. The C(V) curves shown in Fig. 2 were measured on MOS capacitors which had undergone the alternative cleaning procedure prior to deposition mentioned

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type of oxide and the field electrode metal.

248

F. LEUENBERGER

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Fig. 2. C(II) curves for a deposited oxide MOS structure. The final surface preparation step prior to deposition consisted of a dip in dilute hydrofluoric acid followed by a rinse in de-ionized water. C(V) curves for a thermal oxide MOS capacitor are also shown.

earlier. For purposes of comparison, a typical C(V) curve obtained from a thermal oxide device is also shown in this figure. In the case of the deposited oxide only, the final preparation steps prior to deposition consisted of a 60 s dip in dilute HF (1:5), followed by a rinse in de-ionized water and the usual "spin dry ". We note the presence of an effective negative oxide charge. The measured charge density was about 8 × 1011 cm -z. Under the positive bias condition used in the C(V) measurements, a fraction of the negative ions will drift towards the field electrode. This means that the density of mobile charge will actually be somewhat higher than the value given above. A large dispersion of the C(V) curves is also observed in the figure. This dispersion is due either to interface states, to a spatial variation of the surface potential (patchiness) or, most probably, to a combination of both these effects. The limited stability of these devices did not permit sufficiently precise MOS parallel conductance measurements to be made. The sign of the observed drift agrees with the assumption of the presence of mobile dissociation products, e.g. HF~-, but no attempt was made to determine their mobility. The results we have presented so far clearly demonstrate the importance of the wafer preparation procedure prior to the oxide deposition step.

3.1. Determination of interface state densities Figure 3 presents C(V) curves obtained from quasi-static measurements 11.12 together with an ideal low frequency C(V) curve. In order to calculate the ideal curve, the doping concentration was first determined from the capacity minimum of the measured high frequency C(V) curve. The oxide capacity was determined by measuring the MOS capacity in strong accumulation. The curves were traced from inversion to accumulation with a ramp speed of 50 mV s- 1. Several lower ramp speeds were also tried in order to ensure equilibrium conditions. We determined the interface state densities from these quasi-static C(V) curves. The results are shown in Fig. 4. It should be noted that the precision, mainly limited by the

VAPOUR-DEPOSITED S i O 2 FOR DEVICE APPLICATIONS

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Fig. 3. Quasi-static C(V) curves for three different structures: (a) ideal C(V) curve; (b) I000 A of thermally grown oxide; (c) 1000 A of vapour-deposited oxide. The n-type (100) orientation substrates had a donor concentration of 1 x 1015 cm -3. The curves were traced from inversion to accumulation at a rate of 50 mV s-1. N "-fs -10 x10~

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uncertainty of the substrate impurity level, is about 1 × 101° cm -2 eV -1. As far as the increase of Nfs towards the band edge is concerned, it should be borne in mind that the semiconductor capacitance increases very rapidly as a function o f surface potential. A small error in surface potential, therefore, m a y cause a significant error in the interface state density. The interface state density observed in the deposited oxide case, whilst it is a factor of 2 larger than that for the thermal oxide structure, is nevertheless at a favourably low absolute level.

3.2. Ion drift stability After a bias-temperature stress of + 10 V at 200 °C for 2 h, the C(V) curves shifted by 0.05-0.2 V towards more negative voltages. The corresponding shift for thermal oxides was in the 0.05-0.1 V range. After a corresponding negative bias-temperature stress, the shifts observed were less than 0.05 V.

3.3. Dielectric breakdown strength Only a very limited number of destructive breakdown tests were performed. The voltage was raised at a rate of approximately 10 V s - 1. Breakdown occurred at typically 6 × 10 6 V cm -1 for the deposited oxides and at 8 x 10 6 V cm -1 for the thermal oxides.

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F. LEUENBERGER

3.4. Excess noise in p-channel MOSFETs Using the oxide deposition and densification parameters mentioned earlier, metal gate p-channel MOSFETs were also fabricated. Room temperature noise measurements at a drain current of 100 ktA were performed in the frequency range from 30 Hz to 100 kHz. At 1000 Hz (Fig. 5) the RMS input noise voltages differed by a factor of 1.5-2. There was a more or less pronounced tendency towards a generation-recombination spectrum dominated by a single time constant. The excess noise levels are in agreement with the relatively low values for the interface state densities. tv~s]

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3.5. Sensitivity to exposure to 6°Co ~t radiation MOS capacitors were exposed to a dose of 107 rad y radiation from a 6°Co source (1.3 MeV) with no bias applied during irradiation (leads shorted). C(V) measurements were made prior to and after exposure. As shown in Fig. 6, the C(II) curves measured after exposure show a high degree of dispersion for both types o f gate insulators. The density of the irradiation-induced oxide traps is somewhat higher for the deposited oxide. C(V) hysteresis measurements (Fig.7) were also performed on both groups of devices. The measurement conditions were as follows. At a signal frequency of 100 kHz the trace was started at +4.5 V (accumulation). At a constant rate of 0.2 V s -1 the voltage was swept until a field electrode voltage of - 16 V was reached. This voltage was applied for 60 s and then the return trace was started. Hysteresis of the pre-irradiated devices was less than 0.02 V and about twice as high for the deposited oxide as for the thermally grown oxide. The results are in qualitative agreement with other observations 13 showing that the amounts of oxide charge and interface states introduced by a given radiation dose are proportional to the respective levels prior to exposure.

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IV. DISCUSSION

Deposited dielectric layers have been used in combination with thermal oxides to passivate silicon semiconductor devices. It is reasonable to make full use of the excellent and reproducible interface properties o f the thermally grown oxide on silicon structures. Due to the separation from the silicon surface, dielectric films deposited on the thermal oxide play a more or less passive role. Nevertheless, one must carefully avoid polarization-conductivity differences and

252

F. LEUENBERGER

related effects. The application of double layers generally results in fixed charges and traps at the interface of the two layers. In other cases it has been observed that deposited layers can affect the properties of the underlying thermal oxidesilicon interface. For reasons outlined in the introduction we decided to investigate the extreme opposite case by depositing an oxide layer on the bare silicon surface. MIS structures prepared in this manner are characterized by insulator and interface properties approaching those obtained by state of the art thermally grown SiO2-Si systems. The alternative pre-deposition surface preparation processes investigated give evidence of the importance of these preparation steps. A considerable negative oxide charge was observed when the last operation prior to the oxide deposition consisted of a dip in dilute hydrofluoric acid followed by a cold water rinse. The negative oxide charge was of the order of 1012 cm -2. This is about 1% of the total number of initially adsorbed fluoride species ~4. The excellent interface properties obtained for the samples that had been subjected to the standard cleaning sequence might possibly be explained by assuming that the silicon-insulator interface is actually established by the growth of a very thin (___10 A) oxide during the boiling in ultrapure water. In this sense it would seem appropriate to consider the dielectric as a double layer structure. However, this point has no relevance if the supposed discontinuity between the thin grown oxide and the deposited oxide does not manifest itself as a change in the electronic properties of the MIS structure. Neither the C(1I) measurements made at different frequencies nor the excess noise measurements indicate any peculiarities related to a supposed double layer behaviour. The irradiation experiments show a slightly more pronounced dispersion of the C(1I) curves, as well as an increase in hysteresis in the case of deposited oxide structures. However, the available experimental results do not allow a definite decision of whether the additional oxide traps are located at the supposed interface or distributed in an unknown manner within the insulator. In order to assess the applicability of vapour-deposited silicon dioxide layers on active device surfaces fully we need to gain some additional information regarding the influence of certain processing parameters, in particular, the deposition temperature, densification temperature and time. Preliminary observations have revealed that the densification time may be reduced from 20 min to 5-6 rain without any adverse effects on the interface properties. ACKNOWLEDGEMENTS

The deposited oxide films have been prepared by Mr. R. Taubenest and his staff. The author would like to thank Dr. T. Gladden for suggestions concerning the manuscript and Mr. P. Brander for preparing the illustrations. He is obliged to Professor H. Luethy who rendered possible the irradiation at the 6°Co source of the university hospital, Basel, as well as to Dr. J. Golder who kindly performed the irradiation experiments. The author appreciates several stimulating discussions with Mr. Taubenest on the subjects of wafer cleaning and vapour phase oxide deposition.

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2 3 4 5 6 7 8 9 10 11 12 13 14

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