Vapour phase growth of epitaxial silicon carbide layers

Progress in Crystal Growth and Characterization of Materials 47 (2003) 139e165 www.elsevier.com/locate/pcrysgrow

Vapour phase growth of epitaxial silicon carbide layers G. Wagner, D. Schulz, D. Siche* Institute for Crystal Growth, Max-Born-Street 2, D-12489 Berlin, Germany

Abstract After a brief overview of different epitaxial layer growth techniques, the homoepitaxial chemical vapour deposition (CVD) of SiC with a focus on hot-wall CVD is reviewed. Stepcontrolled epitaxy and site competition epitaxy have been utilized to grow polytype stable layers more than 50 mm in thickness and of high purity and crystalline perfection for power devices. The influence of growth parameters including gas flow, C/Si ratio, growth temperature and pressure on growth rate and layer uniformity in thickness and doping are discussed. Background doping levels as low as 1014 cmÿ3 have been achieved as well as layers doped over a wide n-type (nitrogen) and p-type (aluminium) range. Furthermore the status of numerical process simulation is mentioned and SiC substrate preparation is described. In order to get flat and damage free epi-ready surfaces, they are prepared by different methods and characterised by atomic force microscopy and by scanning electron microscope using channelling patterns. For the investigation of defects in SiC high purity CVD layers are grown. The improvement of the quality of bulk crystal substrates by micropipe healing and so-called dislocation stop layers can further decrease the defect density and thus increase the yield and performance of devices. Due to its high growth rate functionality and scope for the use of multi-wafer equipment hot-wall CVD has become a well-established method in SiC-technology and has therefore great industrial potential. Ó 2005 Elsevier Ltd. All rights reserved. PACS: 81.15.Gh; 61.72.Qq; 68.55.Ln

* Corresponding author. Fax: C49 30 6392 3003. E-mail address: [email protected] (D. Siche). 0960-8974/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.pcrysgrow.2005.01.001

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Keywords: A1. Doping; A1. Substrates; A1. Defects; A3. Chemical vapour deposition processes; A3. Hotwall epitaxy; B2. Semiconducting silicon compounds

1. Introduction The indirect wide band gap compound semiconductor silicon carbide (SiC) exists in different polytypes. In optoelectronics single crystalline SiC of the 6H polytype is used as a substrate for the deposition of the direct semiconductor gallium nitride. Among the available substrates for gallium nitride epitaxy SiC is one of the most appropriate ones, due to its high thermal and electrical conductivity and its small lattice misfit. However, the main potential of SiC, especially of the more homogeneous 4H polytype, is in the field of power, high temperature and high frequency electronics and of UV sensors. Recently there has been significant progress in producing SiC devices for high power and high frequency applications. Infineon Technologies AG (Germany) and Cree Inc. (US) started the fabrication of unipolar SiC devices. The low total power loss and the high switching speed are the driving forces for its introduction to the market. Today yield and performance of the devices, with respect to usable active device area, are mainly dependent on the quality of wafers and epitaxial layers. For bulk crystal growth the modified Lely method (MLM), a seeded physical vapour transport (PVT) process had already been established by Tairov and Tsvetkov in 1978 and it has become the leading method on an industrial scale [1]. The extremely high growth temperatures above 2000  C, necessary to have an acceptable growth rate, result in some disadvantages. The nitrogen dominated n-type background doping level is in the order of some 1016 cmÿ3 and the concentration of defects is rather high. Furthermore, the vapour phase composition can hardly be controlled while homogeneous p-type doping is still an unsolved problem. The unique SiC properties, superior in comparison to standard semiconductors, can be utilized only when the material is of high quality. Therefore, today most SiC electronic devices are not fabricated directly on wafers prepared from sublimation grown crystals, but on epitaxial layers. In the following, different epitaxial layer growth processes will be analyzed with respect to growth temperature and vapour phase composition. Sublimation epitaxy, a method very similar to the MLM, has been developed by Vodakov et al. [2]. In a so-called sandwich structure (seed to source distance is small compared to the wafer diameter) a high growth rate can be achieved at a high growth temperature and with low expenditure for equipment. However, like in MLM, the vapour phase composition is not controllable and the purity and homogeneity of the epilayers have to be improved to reach the high quality necessary for devices [3e10]. Additionally, it is difficult to achieve large scale epitaxial production. The long tradition of development of hetero-epitaxial layers is due to the need for high material perfection as well as to the lack of large bulk SiC substrates. The latter

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was overcome by Cree Inc. in the mid-1990s. The first success in growing the cubic 3C polytype on Si substrates by chemical vapour deposition (CVD) using a buffer layer technique was reported by Nishino et al. in 1983 [11]. Growth of SiC epitaxial layers is more controllable with regard to vapour phase composition, growth rate and doping and therefore more reproducible than bulk sublimation growth. Furthermore, since the precursor gas sources are extremely pure, the impurity concentration of the deposited material is up to three orders of magnitude lower than in bulk grown SiC and it is possible to grow n-type and p-type layers with good homogeneity and reproducibility. Especially, the nitrogen dominated background doping level can be decreased, using an effect, already known for other compound materials like ZnSe [12] and applied also to SiC deposition, the so-called ‘‘site competition’’ effect [13]. Increasing the C/Si ratio in the vapour phase decreases the nitrogen level in the epitaxial layers, since nitrogen and carbon compete for the carbon lattice place. Another advantageous fact is the higher structural perfection of epitaxial layers which results from the growth at a significantly lower temperature level. This subject became relevant as the polytype stability was improved by the Matsunami group at Kyoto University in Japan, by introducing step-controlled growth on off-axis oriented (0001) 6H-SiC substrates [14]. The main disadvantage of such substrates was the behaviour of basal plane dislocations at the substrateelayer interface. A majority of basal plane dislocations in the substrates converted into threading edge dislocations in the subsequently grown 4H epilayers [15]. This may be one of the reasons for the development of a process on nearly on-axis substrates [16,17]. The success was attributed to the large improvements in surface preparation technology. In the past a variety of different methods was developed to grow epitaxial layers on single crystalline substrates. They may be classified according to the used nutrient phase or the applied temperature range, and generally the selected method is adjusted to the special goal. Very special methods, like the formation of thin 3C epitaxial films within or on a silicon wafer by ion beam synthesis (IBS) [18] are only mentioned for the sake of completeness. Liquid phase epitaxy (LPE) of SiC suffers from the low carbon solubility in a silicon melt and is carried out at temperatures slightly above the melting temperature of silicon, due to the otherwise high silicon partial pressure. LPE was used in special cases, like sandwich configuration [19], for the investigation of the step-bunching [20], for the healing of micropipe defects [21], to grow a buffer layer on substrates used for sublimation epitaxy [22] or for the growth of p-type doped contact layers [23]. Molecular beam epitaxy (MBE) is usually applied to grow very thin epitaxial layers. Consequently, the growth rate is in the order of nanometer per hour and normally the growth temperature has to be quite low. For the controlled growth of SiC heteropolytypic structures, consisting of some monolayers each of hexagonal and cubic polytypes, the growth conditions were changed from low temperatures (1550 K) and an Si-rich Si/C ratio (3C-SiC) to higher temperatures (1600 K) and a more C-rich environment (4H-SiC) [24].

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Chemical vapour deposition (CVD) is more complicated to classify, since it is used over a wide temperature range. At Hoya Corp. in Japan a novel technique to eliminate planar defects in the 3C-SiC hetero-epitaxial layer on a Si substrate was developed. It was conducted in a cold-wall-type reactor at 1623 K, a temperature well below the melting point of silicon (1683 K) [25,26]. On the other hand the coldwall reactor was also used for homoepitaxial growth of layers with limited thickness. For vapour growth of homoepitaxial SiC layers at higher temperatures, especially for thick layers, horizontal [27e31] and vertical [32e34] hot-wall reactors are suitable. Hot-wall reactors have also been used for the growth of very thick layers for power electronics [35]. In a high temperature CVD (HTCVD) vertical reactor at more than 2270 K, the advantage of high growth rate of the MLM was combined with the purity of the CVD process for the growth of bulk material with high purity [36]. Semi-insulating substrates based on HTCVD are produced by Okmetic AB in Sweden [37]. Section 2 deals with different reactor concepts for chemical vapour deposition at increased temperatures. Since in the last decade there has been much progress in utilizing the potential of homoepitaxial SiC-CVD for industrial processes, especially the hot-wall technique, the paper will then concentrate on this special design and will focus on the different properties of grown layers.

2. Methods of homoepitaxial SiC chemical vapour deposition The CVD growth techniques offer the advantages of a precise control of layer thickness and doping level, good homogeneity, as well as the throughput necessary for industrial use. Therefore this technique is generally accepted as the most promising one. The first experiments were performed using systems developed to grow IIIeV semiconductors. They were redesigned for the increased temperature operation required for SiC epitaxial growth. Further adjustment of the CVD systems to the special conditions of SiC epitaxy turned out to be necessary to grow the required high quality SiC epitaxial layers, namely laminar gas flow, special susceptor design, low total pressure, substrate rotation, effective RF heating, thermal isolation and others. Additionally, to increase the throughput for commercial production, multi-wafer CVD systems have been developed. In its simplest terms, CVD is carried out by heating single crystalline SiC substrate wafers in a reaction cell with flowing silicon- and carbon-containing gases that decompose and deposit silicon and carbon onto the substrate. This allows an epitaxial layer to grow in a well ordered crystal orientation under well-controlled growth conditions. Much effort is devoted to the development of the reactors and the growth process. Variations of the SiC-CVD process are characterised by different reactor positions, horizontally or vertically arranged, by different substrate heating and flow directions of the precursor gases e horizontal or perpendicular to the growing layer surface. The SiC growth process in horizontal reactors of either coldor hot-wall type has been well established [27e30,38e44].

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Typical SiC-CVD is performed at deposition temperatures between 1500 and 1650  C and at pressures from 1 to 960 mbar [29,40]. With increasing temperature the precursor gas will crack more easily and the radicals will attach effectively to the surface, thus leading to epitaxial growth. At the same time mass transport by diffusion and the etch rate from the surface are increased. The growth rate is therefore limited by desorption of the reaction products, by the etch rate of the surface and by the diffusion dominated mass transport of the source molecules. The resulting growth rates are in the range from some micrometers up to about 50 mm/h dependent on the CVD configuration. Both horizontal and vertical CVD systems can work under atmospheric or low pressure conditions, in a single- or multi-wafer configuration. The growth under reduced pressure conditions is helpful in order to minimise the layer non-uniformity in thickness and doping. Substrate rotation is applied for further improvement of epilayer thickness and doping uniformity. The more essential difference is the arrangement of the substrate heating system, a cold-wall or a hot-wall reactor. In a cold-wall reactor the substrate is located on the top of a specified graphite block (susceptor) and RF heated from the lower side by a tubular or pan cake coil. In a hot-wall reactor the substrate is surrounded with specified graphite forms from all sides (susceptor chamber) except the up-stream and down-stream ends and it is thermally isolated by rigid graphite felt. Generally in both versions the susceptors are coated with a polycrystalline SiC or TaC layer to encapsulate the impurities in the graphite, which otherwise lead to undesired doping during the layer growth. 2.1. The hot-wall concept The horizontal hot-wall reactor for SiC epitaxy was first introduced in 1993 [45,46] and is now well established [13,14,29,47,48]. In a hot-wall CVD set up the substrate is arranged in a susceptor which surrounds it from side walls, top and bottom. The parts of the susceptor are made from high purity graphite and may be coated preferably by SiC or TaC. The susceptor is thermally isolated by rigid graphite felt covering all sides except the up-stream and down-stream ends. This arrangement is located inside a growth cell. The heating is performed by an RF generator. The main advantage of the hot-wall concept consists in an efficient heating resulting in a high cracking efficiency of the precursor gases. Molecules in the gas phase may be effectively heated up to a temperature close to that of the susceptor. Thus, a near equilibrium can be established between the gas and the substrate surface. Due to the radiation from the susceptor ceiling, the temperature at the growing surface may be higher than in alternative CVD arrangements at a given growth or susceptor temperature. As a result of the lower temperature gradients normal to the substrate surface the migration of adsorbed species may be enhanced, leading to a better surface morphology and higher polytype stability. Another important effect of the low thermal gradients is the availability of a high growth rate up to 50 mm/h at increased temperatures in comparison to the cold-wall systems. Also the unintentional deposition on the back side of the substrates due to a face to

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face sublimation from the SiC cover of the susceptor is limited by this low thermal gradient. At the high growth temperature level thermal losses are dominated by radiation. These losses are greatly reduced by thermal insulation from graphite foam, increasing the power efficiency. 2.2. Modelling of hot-wall CVD growth Optimisation of process conditions is a permanent task, common to all crystal growth methods. This can be achieved either by try-and-error experiments or by the assistance of numerical simulations. Main issues in CVD process are temperature distribution, layer thickness as well as dopant homogeneity. There are serious differences between numerical simulations of sublimation growth and hot-wall CVD. At first, due to the geometry of the reactor (Fig. 1a) the problem cannot be treated as an axisymmetric one, but as a three-dimensional (3-D) one. Second, the reactive gas flow, often composed of silane and propane diluted in hydrogen, requires both assessment of the fluid-dynamics and the calculation of the kinetics of chemical reactions. Furthermore, since in most cases induction heating is applied, the Maxwell equations have to be solved. To summarize, simulation of hotwall CVD presently comprises the treatment of heat source generation, of heat transfer by conduction, radiation and convection (Fig. 2) and of chemical reactions in the gas phase and at the surface. Recently a model has also been presented for the prediction of the nitrogen doping level in epitaxial layers [49].

gas in

a)

b)

gas in

gas in gas in

c)

d)

Fig. 1. Schematic drawings of the most commonly used CVD reactors, (a) horizontal hot-wall reactor, (b) chimney hot-wall reactor, (c) vertical cold-wall reactor, (d) multi-wafer rotating planetary reactor in hot-wall configuration.

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Fig. 2. Temperature distribution inside a hot-wall susceptor [52].

The 3-D thermal and flow modelling of SiC hot-wall CVD was first done by Lofgren et al. [50]. Calculations were successfully used to optimise coil configuration and susceptor design in order to reduce thermal gradients. In addition, recirculation zones which were also detected in the experiments could be identified by simulations. Although it is clear that specific effects, e.g. buoyancy convection, can only be accounted for by applying 3-D models, it could be shown that most of the thermal optimisation is also achieved by 2-D simulations [51]. According to the pioneering work of Allendorf et al. a model for the silanee propaneehydrogen system has been developed for the chemical reactions involved in the gas phase as well as at the surface [53]. The chemical reaction mechanisms of 83 elementary reactions and 36 reactions with the surface were combined with a rotating disk model in a vertical reactor in order to predict deposition rates. However, large deviations from experimental results were found using this model in 3-D calculations for a hot-wall CVD reactor [54]. Simulations predicted that the deposition process is carbon mass transport limited, whereas experiments showed that the growth was silicon limited. By introducing silicon carbide etching by hydrogen into the model, much better agreement with the predicted growth rate and uniformity was found [55]. Presently, computational investigations of hot-wall CVD systems concentrate on accurate descriptions of the dopant incorporation mechanisms. For nitrogen in silicon carbide a kinetic model has been developed, which provides good agreement at least for a ‘‘standard’’ position of the wafer in the reactor [49]. However, deviations between simulations and experiment regarding specific process parameters indicate that the mechanism of nitrogen incorporation is not yet fully understood. Further refinement of the model for nitrogen incorporation was done by Meziere et al., taking into account adsorption and etching of nitrogen by hydrogen [56].

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3. Epitaxial layer growth process A typical epitaxial growth process requires consideration of substrate preparation as well as layer deposition. 3.1. Substrate preparation The surface morphology and, in particular, the crystalline perfection of the subsurface region of the substrates used for epitaxial growth of SiC substantially influence the defect density in the grown epitaxial layer. The surface of commercially prepared substrates contains a variety of defects. A typical fabrication process for SiC wafers includes a slicing step which damages the subsurface region up to a considerable thickness. This damaged layer can be removed step by step by grinding and polishing using a slurry with boron carbide or diamond powder of different grain size, under an optimised load. SiC wafers prepared in this way have been found to have a large number of scratches and a residual damage layer of some nanometers in thickness [57,58]. Research on the epitaxial growth of 4H- and 6H-SiC layers has shown that these preparation induced defects on the substrate surface may be sources for polytype inclusions and defects such as triangular features and growth pits [39]. When investigating the surface of a polished substrate using an optical microscope or atomic force microscopy (AFM), a large number of randomly oriented scratches can be observed. After the final polishing step (0.25 mm diamond, low vertical load) the scratches are typically 2e5 nm deep (measured by AFM). A subsurface damage layer always exists as a result of the mechanical preparation steps. The thickness of this damaged subsurface region as well as the roughness of the wafer surface correlates directly with the polishing parameters. The electron channelling pattern (ECP) technique performed in a scanning electron microscope (SEM) can be used to characterise the surface damage. After calibration of the ECP intensity ratio vs. the damaged layer thickness obtained from HVTEM micrographs it is possible to characterise the damaged layer and to estimate the surface quality very quickly without complicated sample preparation. Fig. 3aed shows the ECP images of the wafer surfaces and the corresponding HVTEM crosssectional micrographs after polishing with diamond abrasive of different grain size (1 and 0.25 mm) and decreasing vertical load (0.8, 0.4 N cmÿ2). The individual preparation parameters are listed in Table 1. The ECP intensity ratio is determined by dividing the maximum change in intensity across the C11.0D channelling lines measured for a damaged surface by the same quantity for the undamaged reference surface (as-grown sample). It is clearly seen from Fig. 3aed that the nature and extent of subsurface damage depends on the grain size and vertical load during polishing. The final surface presents damage up to 20 nm in depth. The decrease of the damaged layer thickness with decreased grain size of the abrasive and reduced vertical load during polishing is clearly visible in the HVTEM micrographs. Correspondingly, the ECP intensity ratio, which is correlated to the damaged layer thickness, increases from 44 to 62%.

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Fig. 3. ECP images and corresponding cross-sectional HVTEM micrographs of 4H-SiC (0001)8  surfaces obtained after preparation using various conditions (see Table 1).

off

wafer

An additional etching step in hydrogen/propane gas prior to epitaxial growth substantially improves the structural and morphological properties of the substrate surface. This process removes the subsurface damage and leaves a smooth surface without scratches, characterised by the average roughness Ra (Fig. 4) [58,59]. This final etching is normally carried out in a hot-wall CVD reactor at temperatures between 1550 and 1600  C for 5e10 min at a system pressure of about 250 mbar. Currently, chemo-mechanical polishing (CMP) [60e63] has been developed to overcome the disadvantages of mechanical preparation techniques. The combination of the abrasives in the slurry with the chemical reaction of the surface results in mirror-like surfaces and very low roughness. Because of the low chemical reactivity of SiC the etching rate is very small and this technique may be employed as the final step in the preparation of epi-ready surfaces. Using CMP-prepared substrates additional hydrogen/propane gas etching before layer deposition is not necessary. In the process of heating up to the growth temperature the wafer surface is in any case weakly etched (some nanometers) by the chemical reaction between hydrogen and SiC.

Table 1 Surface characteristics of 4H-SiC (0001)8  grain size and vertical load

off

oriented substrates, polished with diamond slurry of different

Sample

a

b

c

d

Grain size (mm) Load (N cmÿ2) H2/C3H8-etching Damaged layer thickness (nm) ECP intensity ratio (%)

1 0.8 e %40 44

1 0.4 e %30 48

0.25 0.4 e %15 62

1 0.4 T Z 1550  C, t Z 30 min Not visible 95

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Fig. 4. Atomic force microscopy images of 4H-SiC (0001)8  off surfaces after (a) mechanical surface preparation, Ra ! 1 nm, (b) etching in hydrogen/propane gas (propane partial pressure 2 ! 10ÿ2 mbar), Ra ! 2 nm.

3.2. Layer deposition The introduction of the step-controlled epitaxial growth technique by Matsunami [14] and the application of the site competition principle for SiC epitaxy by Larkin [13,64] are two significant milestones in the technology for the preparation of suitable homoepitaxial SiC layers. Site competition involves the incorporation of acceptor or donor atoms during epitaxial growth by controlling the carbon to silicon ratio (C/Si ratio) in the gas phase. These two growth principles in combination with hot-wall CVD-technology provide a fundamental basis for the growth of SiC layers for application in power, high frequency and high temperature electronics. At the Institute for Crystal Growth homoepitaxial growth of SiC is carried out by low pressure CVD in a horizontal hot-wall reaction cell. Reaction gases, SiH4 and C3H8 diluted in hydrogen, are carried by palladium-purified H2 gas. Nitrogen is used for n-type doping and trimethylaluminium (TMA) for p-type doping. As mentioned above, a mixture of H2 and C3H8 is used for etching the substrate to remove the damage layer before growth. Normally, commercial 4H-SiC (0001) substrates with a slight offorientation towards the !11.0O are used. The layer growth on such substrates is characterised by the step-controlled growth mode. The formation of surface steps due to the off-orientation enhances the repetition of the substrate polytype in the epitaxial layer. In this way the grown polytype is stabilised. The distance between the individual steps on the grown surface is lower, the necessary surface diffusion lengths of the adsorbed molecules are reduced and the bidimensional epitaxial layer growth can be performed at lower temperatures, between 1500 and 1600  C. The typical range of experimental parameters for hot-wall CVD epitaxy is given in Table 2. The growth rate is proportional to the SiH4 partial pressure as shown in Fig. 5 and weakly sensitive to the growth temperature between 1500 and 1600  C. The growth rate increases linearly in the investigated SiH4 partial pressure range. The

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G. Wagner et al. / Progress in Crystal Growth and Characterization of Materials 47 (2003) 139e165 Table 2 Typical growth parameters for hot-wall CVD Silane flow (sccm)

Propane flow (sccm)

C/Si ratio

Temperature (  C)

System pressure (mbar)

Carrier gas main flow (slm)

10e25

5e17

1e2

1500e1600

100e250

20e50

maximum growth rate to get layers with mirror-like surfaces is about 15 mm/h at 1550  C. With increasing growth temperature and silane flow the growth rate also increases. In a vertical chimney reactor the growth rate increases from 15 to 35 mm/h between 1650 and 1900  C [32,34]. Only minor effects of the system pressure and the growth temperature on the growth rate are observed. The growth rate does not change significantly in the investigated pressure range. A reduction of the system pressure from 250 to 150 mbar increases the growth rate by about 4% whereas its change between growth temperatures of 1550 and 1600  C is negligible (see Fig. 6). A spatially resolved investigation of the growth rate dependence on the system pressure has shown that at least two factors play a significant role [65]. The supersaturation decreases due to the consumption of input source gases in the upstream region. Furthermore, with decreasing pressure, i.e. increasing flow velocity, the relative amount of species, which are transported to the temperature maximum, increases towards the down-stream region above the wafer.

16 14

R [µm/h]

12 10 8 6 4 2 0.02

0.04

0.06

0.08

0.10

0.12

0.14

SiH4 partial pressure [mbar] Fig. 5. Growth rate dependence on the silane partial pressure (Tg Z 1550  C, psys Z 150 mbar, C/Si Z 1.5).

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8

150 mbar

R [µm/h]

250 mbar

7

6 1540

1560

1580

1600

1620

Fig. 6. Growth rate dependence vs. growth temperature at pSiH4 Z 0.06 mbar (parameter system pressure).

3.2.1. Homogeneity of layer thickness The growth rate as well as the layer thickness distribution are both strongly influenced by the main flow of H2 carrier gas. As a result of this flow the position of the maximum layer thickness is shifted from the susceptor inlet via the full susceptor length up to the outlet. The reason for this behaviour is that at high H2 flow rates the majority of the dissociated gas molecules are deposited on the reaction cell behind the susceptor. On the other hand at low H2 flow rate the deposition takes place in the front of the susceptor. By optimisation of the carrier gas flow it is possible to adjust the area of highest deposition efficiency to the area of highest temperature homogeneity, where the substrate is positioned. With optimal values for carrier gas flow and system pressure a maximum growth rate of 15 mm/h at an SiH4 partial pressure of 0.13 mbar is possible at a growth temperature of about 1550  C. The standard deviation in layer thickness under such optimised conditions is in the range of 1% on 2 inch wafers, as shown in Fig. 7. In a hot-wall susceptor with wafer rotation an additional improvement in layer homogeneity is possible [27,30]. In such machines a standard deviation of the thickness of about 0.5% is typically measured on 2 inch wafers with 5 mm edge exclusion. Especially in configurations with multi-wafer susceptors wafer rotation is helpful in order to get a homogeneous thickness distribution with a standard deviation below 1%. 3.2.2. Unintentional doping The main impurities in epitaxial layers are nitrogen, aluminium and boron. Since the first one is a shallow donor and the other two are acceptors their balance

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G. Wagner et al. / Progress in Crystal Growth and Characterization of Materials 47 (2003) 139e165 d [µm] 49,0-51,0

6

47,0-49,0

12

45,0-47,0

18 24

mm

30 36 42 48 3

9

15

21

27

mm

33

39

45

51

Fig. 7. 4H-SiC epilayer of about 50 mm in thickness with a standard deviation of about 1% on a 2 inch wafer.

a)

1016 n-type p-type

1015

1014 0.0

0.5

1.0

1.5

C/Si

2.0

2.5

net doping concentration [cm-3]

net doping concentration [cm-3]

determines type and value of the final conductivity. Unintentionally doped epitaxial layers are usually n-type by nitrogen doping. Sources of the residual nitrogen may be the susceptor, the thermal insulation and the reaction cell all of which can absorb nitrogen during sample loading. In accordance with the site competition mechanism the nitrogen incorporation can be controlled by the C/Si ratio. In Fig. 8a the C/Si ratio was varied by changing the propane flow from 0.5 to 2 while keeping all other growth parameters constant.

b)

1016 n-type p-type

1015

1014 100

200

300

400

500

system pressure [mbar]

Fig. 8. Dependence of the net doping concentration for unintentionally doped 4H-SiC epilayers (Si face) on (a) C/Si ratio at p Z 150 mbar and (b) system pressure at C/Si Z 2.

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The expected suppression of the N incorporation with increasing C/Si ratio is confirmed by the decreasing average net-donor concentration determined by capacitanceevoltage (CeV) measurements as seen in Fig. 8a. For a C/Si ratio of 2 the N-concentration is already lowered down to the level of residual acceptor impurities and the CeV data indicate nearly completely compensated epilayers or even their conversion to p-type conduction. A similar behaviour is also observed for the dependence of the net doping concentration on the system pressure shown in Fig. 8b. It can be seen that the N incorporation is also reduced by decreasing the system pressure [44,66]. Fig. 9 shows a CeV map of the net doping concentration of an epilayer already converted to p-type. In the central area the net acceptor concentration amounts to (1e2) ! 1014 cmÿ3 whereas it is higher at the rim. Secondary ion mass spectroscopy (SIMS) measurements near the centre of the epilayers determined Al and B in the concentration range of (1e 2) ! 1014 cmÿ3 (Fig. 10). This is well above the detection limit of 2 ! 1013 cmÿ3 for Al and 6 ! 1013 cmÿ3 for B supporting the interpretation of the CeV measurements. These impurities can be out-diffused from the susceptor graphite which is normally coated with SiC. However, after several growth runs, this coating is partly etched away enabling the evaporation of B and Al at high temperatures. 3.2.3. Intentional doping A prerequisite in developing SiC devices for high power application is a background doping concentration as low as 1014 cmÿ3 and well controlled n-type

35

NA-ND [cm-3] at 10µm depth

30 5E13

y [mm]

25

1E14 2E14

20

4E14

15 8E14

10 5 0 0

5

10

15

20

25

30

35

x [mm] Fig. 9. Mapping of the net doping concentration at a depth of 10 mm of an epilayer which is converted to p-type at a C/Si ratio of 2 and a system pressure of 150 mbar.

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1016 Al

atoms [cm-3]

B

1015

1014

1013 0.1

0.2

0.3

0.4

0.5

0.6

depth [µm] Fig. 10. Al and B profiles in the centre of an unintentionally doped 4H-SiC epilayer (SIMS, same layer as in Fig. 9).

and p-type doping. A diffusion doping technology similar to that used for electronic silicon is not possible because the common dopants in SiC have very low diffusion coefficients. The SiC epitaxial layers for device structures can be doped by ion implantation or during layer growth by adding a dopant to the growth atmosphere. An undesirable result of implantation is the generation of additional defects in the epitaxial layers [67], which cannot be completely eliminated by any subsequent annealing at high temperature. Furthermore, the high temperature treatment adversely influences the properties of the layer surface. The surface roughness increases and the doping profiles can be changed. The alternative way is to incorporate the dopants in situ during layer growth. The most common p-type sources are the acceptor sources trimethylaluminium (TMA) and diborane (B2H6) for obtaining Al-doped and B-doped SiC layers. Nitrogen is the most common n-type dopant (donor). Also phosphorus (using PH3) is possible, but because of its high vapour pressure it is rarely employed. As mentioned above, by changing the C/Si ratio it is possible to prevent or enhance the incorporation of a particular doping atom on either a Si lattice site (Si-site) or C lattice site (C-site) of the growing layer. The dopants must occupy specific lattice sites in order to be electrically active. Nitrogen occupies the carbon sites while aluminium occupies the silicon sites of the SiC lattice. Therefore, an increase of the relative C/Si ratio in the source gas hinders the nitrogen atoms from finding free carbon sites in the growing lattice. The analogous situation exists for a relative decrease of the C/Si ratio, which impedes aluminium atoms from occupying free Si lattice sites. This relation between the C/Si ratio and the doping incorporation has enabled an expansion of the

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n-type doping range from 1014 up to 1019 cmÿ3 [13] and for the p-type doping range from 1 ! 1014 up to 5 ! 1020 cmÿ3, respectively. 3.2.3.1. Aluminium-doped p-type layers. Aluminium (Al) is the most common p-type doping element in SiC and substitutes for the Si atom. Boron can also be used as a p-dopant, but Al is preferred because its ionisation energy (220e250 meV) is lower in comparison to that of B (300e390 meV). Moreover, boron tends to induce deep defects (D-centres) in the band gap. The incorporation of Al can be controlled by the TMA-flow and by means of site competition by proper variation of the Si/C ratio during epitaxial growth [48,68,69]. Even small amounts of TMA added to the process gases are effective for intentional aluminium doping. The doping efficiency is much higher on the Si-terminated face than on the C-face of SiC [38]. In doping experiments on (0001) 4H-SiC the acceptor concentration increases linearly with TMA partial pressure. This is an indication of mass transport limited incorporation of Al [68]. When the TMA partial pressure is varied from 7 ! 10ÿ8 to 3 ! 10ÿ5 mbar an Al-concentration in the range from 3 ! 1014 up to 4 ! 1019 cmÿ3 is achieved. Epilayers with very smooth, mirror-like surfaces are grown corresponding to this doping range with morphologies generally depending on the quality of the substrates. Fig. 11 shows the chemical Al-concentration [Al] and the net acceptor concentration determined by SIMS and CeV measurements, respectively, with their dependence on the TMA partial pressure. From a linear fit of the logelog scaled data, both [Al] and NAeND are seen to be proportional to (pTMA)1.5. However, the absolute [Al] values exceed those of the net acceptor

1021

NA-ND, [AI] [cm-3]

1020 1019 1018 1017 1016

C-V SIMS

1015 1014 10-8

Hall

10-7

10-6

10-5

10-4

10-3

10-4

pTMA [mbar] Fig. 11. Al and acceptor concentrations determined by SIMS, Hall and CeV measurements, respectively, as a function of the TMA partial pressure.

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concentration by an average factor of 2.5 (G1 maximum spread). The concentration of residual donors determined by Hall effect measurements [68] is more than two magnitudes lower as the net acceptor concentration. Therefore, the compensation of acceptors can be neglected. Only 30e70% of the incorporated Al atoms are electrically active as shallow acceptors. Increasing [Al] from 6 ! 1019 to 2 ! 1020 cmÿ3 normally causes an increase of the surface roughness and [Al] saturates with its dependence on pTMA. At [Al] w 1.5 ! 1020 cmÿ3 the surface is characterised by strong step-bunching and macro step formation. The macro steps are composed of large facets with zigzag front sides (Fig. 12b). The AFM analysis reveals that the Ra values are around 15e 20 nm. The surface roughness as a function of the [Al] in 4H-SiC layers is shown in Fig. 13. The increase of the roughness and the much coarser surface morphology are the result of a change in the growth mode. The diffusion limited mass transport changes to a kinetically controlled growth. For [Al] O 6 ! 1019 cmÿ3 the roughness increases dramatically and for [Al] O 1020 cmÿ3 it is about a factor 6e10 higher. Fig. 12 shows typical atomic force microscope (AFM) images of about 8 mm thick epitaxial layers with acceptor concentrations of 3.6 ! 1019 and 1.5 ! 1020 cmÿ3. Investigations using high resolution transmission electron microscopy (HRTEM) show a high density of defects along with a high number of stacking faults [70]. Therefore it can be concluded that the solubility limit of Al in 4H-SiC is exceeded under these specific growth conditions. This is in agreement with the Al-solubility limit of 2 ! 1020 cmÿ3 published in Ref. [71]. 3.2.3.2. Nitrogen-doped n-type layers. Nitrogen is the most important n-type dopant in SiC and its incorporation mechanisms during epitaxial growth have been investigated

Fig. 12. AFM images for chemical Al-concentration: (a) [Al] Z 3.6 ! 1019 cmÿ3, Ra Z 0.3 nm, (b) [Al] Z 1.5 ! 1020 cmÿ3, Ra Z 16.7 nm.

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18 16 14

Ra [nm]

12 10 8 6 4 2 0 1018

1019

1020

[Al]

1021

[cm-3]

Fig. 13. Surface roughness Ra of layers vs. [Al], Tg Z 1550  C, C/Si Z 1.5, p Z 150 mbar.

by several groups [32,33,48,72e74]. The process parameters which influence the nitrogen incorporation are the nitrogen partial pressure, the reactor pressure during growth, the C/Si ratio, the growth rate and temperature. A detailed description of the corresponding effects of each of these parameters is given in Refs. [32,48]. The site competition principle enables one to control the nitrogen doping in SiC layers from less than 1014 to 1019 cmÿ3 (Fig. 14). The nitrogen incorporation decreases with increasing C/Si ratio for both Si- and C-face samples. Since a nitrogen atom takes a C-site in the SiC lattice, an increased concentration of C containing species with higher C/Si ratio results in a reduced nitrogen incorporation. The nitrogen incorporation increases on both faces with increasing nitrogen flow. A decreasing total pressure leads to lower incorporation. The incorporation of nitrogen increases exponentially with the temperature [32]. By utilizing optimum growth parameters to grow intentionally nitrogen-doped layers a maximum netdonor concentration of 5 ! 1019 cmÿ3 has been achieved [48]. The uniformity of the doping distribution over the full wafer area depends on the temperature homogeneity, the carrier gas flow and the total pressure. A significant improvement in doping homogeneity has been achieved by using reactors with wafer rotation. Under optimised growth conditions a standard variation with mean value of about 6% and a maximum variation with mean value of about 35% were reported [27].

4. Improvement of the structural perfection of 4H-SiC seeds Infineon Technologies AG and Cree Inc. have started the industrial-scale fabrication of unipolar SiC devices [75,76]. The yield and performance of devices

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1020 1019

ND-NA [cm-3]

1018 1017 1016 1015 1014

10-4

10-3

10-2

10-1

100

pN [mbar] 2

Fig. 14. Net-donor concentration determined by CeV measurements as function of the nitrogen partial pressure (Tg Z 1550  C, psys Z 150 mbar, C/Si Z 1.5).

with regard to usable active area are mainly dependent on the quality of wafers and epitaxial layers. The reduction of defects in substrates and epilayers is a most significant target for further progress in high power SiC device development. In bulk SiC a variety of defects have been observed [77], most of them interact with the growing CVD layer. Among the basal-, screw- and edge-dislocations, stacking faults, micropipes, inclusions and low angle grain boundaries, the micropipe density is the most limiting factor for the production of large area 4H-SiC devices for high power applications. The early breakdown of such devices is indeed caused by the ignition of a microplasma within a micropipe in the device area [78,79]. In the last few years the micropipe density has been decreased continuously from 100 to 10 cmÿ2 in commercial wafers. However, the operational current of devices prepared on such wafers is very low. To increase this current, it is necessary to enlarge the active area of devices, but this enlargement is limited by the micropipe density. A micropipe is a super screw dislocation with an additional edge-dislocation component [80] and with a hollow core some micrometers in diameter. It penetrates a (0001) SiC substrate from front to back nearly along the c-axis. Micropipes have a screw component with Burgers vectors b R 3c for the 4H-SiC polytype, where c is the lattice constant in the !00.1O direction [81]. Most of the micropipes located in the seed propagate through the growing crystal during bulk growth. Recently it has been shown that the deposition of epitaxial layers on the seeds can lead to a reduction in the micropipe density [82e86]. At first, a thin (!0.1 mm) buffer layer was grown by liquid phase epitaxy (LPE) on a commercial wafer. The influence on

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the subsequent CVD epitaxial layer was investigated [86]. The LPE filling process caused a significant improvement in the structural quality of CVD layers. Cathodoluminescence data and electrical characteristics of Schottky barriers revealed that the concentration profiles of the uncompensated donors and recombination centres for holes as well as the hole diffusion lengths were more uniform. Furthermore an increase of the breakdown voltage was observed. While LPE buffer layers are useful for filling large micropipes, CVD-grown buffer layers on micropipes can convert them to closed-core screw dislocations before growing the electrically active layers [82]. By applying Si-rich conditions (C/Si ratio % 1) a structural improvement of the epitaxial layer, compared to the underlying substrate, has been achieved on both the Si- and C-faces. At the Institute for Crystal Growth (IKZ) experiments were carried out to overgrow micropipes. Home-made nitrogen-doped 2 inch 4H-SiC wafers with the C-face about 7  off-axis oriented towards the !11.0O direction were used as substrates [87]. These (000ÿ1) 4H-SiC substrates with epitaxial buffer layers may subsequently be used as seeds for bulk crystal growth, leading to crystals with lower micropipe density. Epitaxial growth was performed in a horizontal hot-wall CVD equipment [66]. Micropipe conversion has been investigated by varying the C/Si ratio in the source gas atmosphere. With a carbon excess (C/Si O 1), the necessary condition for low nitrogen background doping, the micropipes propagate in the layer without any changes. With silicon excess (C/Si % 1) they dissociate into separate dislocations. In Fig. 15 Nomarski images (a, c) of 20 mm thick layers and the

Fig. 15. Surface images of an epitaxial layer in Nomarski contrast (a, c) and micropipes in the (000ÿ1) 4HSiC substrate at the same positions in transmission light (b, d) (C/Si Z 0.9 (a, b); C/Si Z 1.5 (c, d)).

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Fig. 16. Image of a scar like region at the surface of the epitaxial layer (C/Si Z 0.9) in Nomarski contrast (a) and at the same position the EBIC-image (b) of the dissociated micropipe.

transmission light images of two micropipes (b, d) at the same positions in the substrates are shown. At a C/Si Z 0.9 the micropipe is dissociated into separate dislocations leaving a scar like formed surface region. At a C/Si Z 1.5 the micropipe was not dissociated but propagates into the epilayer. Fig. 16 shows the surface fault (a) as a result of micropipe dissociation and the corresponding electron beam induced current (EBIC) image (b). Recently investigations on the reliability of Schottky devices produced from substrates with overgrown micropipes have shown that the remaining defects lead to strong long term degradation [88]. Consequently, for this type of high power device the process of micropipe filling during epitaxy seems to be inappropriate to increase the device yield. However, substrates with epitaxially closed micropipes could be used as seeds for bulk sublimation growth in order to decrease the micropipe density. Wafers from these crystals could offer improved properties compared to the substrates described above. In addition to the defects propagating from the substrate volume (Fig. 17a) or originating at the emergence points of substrate defects, other types of defects are due to the substrate surface preparation and also to the CVD process. They can be seen as triangular depressions, shallow growth pits and carrot like groves on the surface (Fig. 17bed). Fig. 18 shows that carrot like defects can occasionally be correlated to deep scratches which were not removed by hydrogen/propane etching before the layer deposition. The occurrence of these defects can be significantly reduced by using chemo-mechanical polishing in order to give a wafer surface free from subsurface damage layer and free from scratches. As soon as the micropipe density is sufficiently decreased, stacking faults and dislocations come into the focus of research. As already mentioned in Section 1, the propagation of basal plane dislocations (BDs) from off-axis substrates into epitaxial layers is partly coupled with a conversion of these dislocations into threading edge dislocations. The conversion was interpreted as a result of the image force in the epilayers between flowing growth steps and BDs. It was suggested that this effect could lead to an apparent improvement of the structural quality of epilayers compared to that of substrates [15]. The BDs are inclined towards !1ÿ1.0O or

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Fig. 17. A 20 mm thick 4H-SiC epilayer with various defects: (a) micropipe; (b) triangle defect; (c) growth pits; (d) carrot like defect (Nomarski photograph).

!11.0O depending on the off-cut direction in the substrate, but no significant difference was found in their density [89]. Obviously, the number of converted basal plane dislocations should decrease with decreasing off-axis orientation. This was one motivation to develop an epitaxial process on lower off-axis angle substrates [16,17].

Fig. 18. Carrot like defects on the epilayer surface, seeded at a deep scratch on the substrate wafer surface.

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The second motivation is based on economic interests. Bulk grown crystals are usually grown on on-axis substrates to minimise the defect formation from the seed wafer edge. Additionally they are relatively short, due to the growth rate decrease with time. On the one hand there is a great interest to use larger substrate diameters for epitaxy, but on the other hand the 8  off-axis substrate preparation results in a waste of bulk material and a decrease in wafer yield with increasing crystal diameter to length ratio. This was the reason for the development of a 3 inch epitaxial growth process at Infineon Technologies AG for 4  off-cut substrates [90]. Recently, the formation of threading edge dislocations, revealed by characteristic arrays of etch pit pairs on the epilayer surface and arranged perpendicular to the offcut direction has been reported [91]. The arrays were nucleated during epitaxial growth, had a length up to 600 mm and a linear dislocation density of about 103 cmÿ1. The Burgers vectors of two dislocations in each pair were consistent with pairs nucleating as half loops and they were all parallel to each other in an array. The nucleation mechanism could not be explained and is therefore one of the topics of future research. The stacking fault (SF) formation is strongly enhanced in 4H substrates with nitrogen concentrations above 2 ! 1019 cmÿ3 after thermal treatment. This was revealed by the replacement of the dominating band gap emission (394 nm) by an intense PL band at about 500 nm in RT-PL spectra and is also confirmed by the strong anisotropy of the resistivity measured by the Hall effect [92]. But SF formation is a more general problem. The high potential of 4H-SiC pin diodes can be exploited only in substrates and epilayers with low defect density. Unfortunately, during device operation a forward voltage drift to higher values was observed and is due to the SF formation. These SFs can propagate through the intrinsic layer, increasing their resistance. The SF density has been significantly reduced by appropriate buffer layer design. This layer can efficiently stop the SF propagation [93].

5. Summary and outlook Much progress has been made in the field of homoepitaxial SiC-CVD, especially hot-wall CVD, for industrial processes. Material quality as well as device efficiency are the driving forces to develop epitaxial layers on large diameter substrates of high perfection and homogeneity. Presently the standard diameter is changing from 2 to 3 inch; 4 inch prototype wafers have already been demonstrated by Cree Inc. some years ago. In the past the breakthrough in polytype stable growth was due to step flow mode by using (0001) substrates off-cut to the !11.0O direction by some degrees. But, nowadays there is an increasing search for an on-axis process. The off-angle reduction is motivated by the interaction of basal plane dislocations in the substrate with the growing layer and by the higher wafer yield from relatively short on-axis bulk crystals.

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The CVD was made more effective by using multi-wafer equipment and by increasing the growth rate for thick (O50 mm) layer growth for power electronics. As a rule, a layer thickness of 1 mm is necessary for each 100 V blocking voltage. With a dislocation stop layer a further decrease of defect density was achieved. This is one of the prerequisites for the improvement of the electrical properties of pnjunction structures, a great challenge for the near future. These junctions are expected to be superior to the implanted ones, where the elimination of the implantation damage by high temperature annealing is not complete and the doping profiles are changed. CVD is also very useful for the investigation of defects in SiC and for improving the quality of bulk crystal substrates by micropipe healing. Hot-wall CVD has turned out to be a fundamental method in SiC-technology and has a great potential for future developments.

Acknowledgements This work was supported by the German Ministry of Education and Research under contract 01BM070. The authors are grateful to Prof. R. Fornari for critical reading of the manuscript.

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Gu¨nter Wagner received the diploma degree in crystallography from the Humboldt-Universita¨t zu Berlin in 1975. Until 1979 he did his doctoral research at the Institute of Optics and Spectroscopy of the Academy of Science and received the PhD degree in 1980. The thesis was on the preparation of semiconductor layer structures for laser devices by LPE. From 1980 to 1991 he was working on different technologies to prepare epitaxial semiconductor layers for optoelectronic devices. In 1992 he joined the Institute for Crystal Growth (IKZ), Berlin. His current research is focused on epitaxial growth of silicon carbide by chemical vapour deposition for power devices and detectors.

Detlev Schulz received his diploma degree in crystallography from the Humboldt-Universita¨t zu Berlin in 1990. Two years later he joined the Institute for Crystal Growth (IKZ), Berlin. Until 1996 he was engaged in the crystal growth of SiGe solid solutions by the Rf-heated floating zone technique. Then he was involved in vapour phase growth of silicon carbide. In 2001 he received his PhD degree in physics from the Brandenburg University of Technology. The main focus of his current research is bulk crystal growth of silicon carbide.

Dietmar Siche graduated in physics from the Humboldt-Universita¨t zu Berlin in 1977. From there he received the PhD degree in 1981 and was engaged in the preparation of compound semiconductor crystals with small band gap till 1992. Since 1993 he is working in the Institute for Crystal Growth (IKZ), Berlin, on the growth of wide band gap materials ZnSe and SiC from the vapour phase. In 2003 he obtained his postdoctoral qualification from the Brandenburg University of Technology, working there also as a private lecturer.