VERSAbus—a multiprocessor bus standard—and VMEbus—its Eurocard counterpart

VERSAIms a m u l t i p r o c e s s o r bus standard - and V M E b u s its E u r o c a r d c o u n t e r p a r t Bus architectures capable of handling multiprocessor systems have an advantage in microcomputer applications. Richard DeBock examines two buses with such a capability Descriptions o f VERSAbus and VMEbus are given. Features of each bus architecture are compared by being broken down into five separate buses: data transfer, priority interrupt, D TB arbitration, utility and interintelligence buses. Sequence diagrams for protocol layers including write and read data transfer cycles and read modify write are ~iven. Bus drivers recommended by both bus specifications are mentioned. The future for each of the buses is outlined. Appendices include details o f Pl and P2 edge connector pin assignments. microsystems

bus standards VERSAbus/VMEbus

The advent of microprocessors in the 1970s has had a revolutionary effect on the thinking of computer system architects. The early architectures were designed to maximize the use of an expensive central processing unit. Today, peripherals and software are now the most expensive part of a system. However, microprocessors are still not running at mainframe speeds. If extra data processing or task handling speed is required, the least costly hardware solution is to add another microprocessor. As a result, today's bus architectures must be capable of handling multiprocessor

Figure 1. The boards for VERSAbus are large (9.3 x 14.5 in) Motorola Microsysterns,3102 North 56 Street, Pheonix, AZ 85018, USA

vol6no 9 november 1982

configurations. Another important feature of any bus not destined for early obsolecence is the ability to handle data and address paths of up to 32-bits. Both VERSAbus and the VMEbus (Figures 1-3) provide these features. VERSAbus boards are large (9.3 x 14.5 in) allowing them to be packed with a lot of processing power and large amounts of memory. It is now possible to build ½ Mbyte memory boards with error detect and correct (EDAC) using current MSI and LSI technologies (2 Mbyte memory boards are possible with 256 kbyte dynamic RAMs when they become available in production quantities). Large EDP and/or large industrial control applications are usually best accomplished using these boards. VM Ebus boards are much smaller than VE RSAbus boards and use the single and double Eurocard form factors. The double boards allow a reasonable mix of processing power and memory for small to medium scale industrial control applications. The greater modularity of VME boards allows an end user to mix-and-match processor, memory and I/O boards to uniquely match a particular application while still allowing future expansion as his system needs change. These systems might be tailored to the high growth applications where the end user adds a memory board to handle

.... Figure 2. VMEbus is configured on double or single Eurocard boards (9.2 x 6.3 in)

0141-9331/82/090475-07 $03.00 © 1982 Butterworth & Co (Publishers) Ltd

475

Tabie 1. VMEbus and VERSAbus comparisons VM Ebus Double Eurocard

V E RSAbus

VM Ebus

Single Eurocard

Single Eurocard No

Board size

6.3 x 9.2 in 6.3 x 3.9 in 160x233mm 160x 100ram (IEC 297, 2nd edition)

9.3 x 14.5 in 235x236mm

Address parity

No

Board area

58 in 2 37280 mm 2

25 in 2 16000 mm 2

t35 in 2 8 6 4 8 0 mm ~

Control signals

Number o l connectors type

2

1

2

7 Address strobe Data strobe 0 Data strobe 1

9 Address strobe Data strobe 0 Data strobe 1

pin and socket (DIN 41612)

pin and socket (DIN 41612)

edge finger

Drivers Receivers

TSHC HYS

I'SHC STD

P1 contacts use

96 VMEbus

96 VMEbus

140 VERSAbus

Write Long word (32-bit data)

P2 contacts use

96 standard RowBfor32 bit expansion, Rows A and C for I/O connectiGriS (in nonexpanded systems, P2 can be any type of DIN standard connector)

Write Long word (32-bit data) Address parity valid Data parity valid

TS LC STD

rS LC STD

Data transfer Acknowledge Bus error

Data transfer Acknowledge Bus error

Drivers

OC

OC

Priority Interrupt bus Interrupt lines Prioritized Drivers Receivers

7 Yes OC STD

7 Yes OC STD

Yes (interrupt acknowledge)

Yes (daisychain may be used for other than interrupt acknowledgement)

4 (I level optional) Yes

5 Yes

Daisychains (Bus grant in/bus grant out)

4

5

Utility bus signals

4

System clock (16MHz}

7 AC clock AC failure System failure System reset System test (2 lines) System clock (16MHz)

In terintelligence bus Signals

Yes Serial clock Serial data

Yes Serial clock Serial data

Reserved pins

All of P2 pins None are user defined for 16-bit option. (I reserved pin for 32-bit option)

9 (28 with 32-bit option)

3 3 1 I (for backup power) I I ! 1 7 7

6 2

120 Pins 67 120 used for 32-bit expansion. Pins 17- 66 used. I/O (in nonexpanded systems, 7 1 - I 20 may be used for I/O connectors)

Bandwidth

5 MHz

Terminators (Thevenin Equivalent)

2.94 V in series with 194 ,~ connected at each end of the bus

5 MHz

5 MHz 2.94 V in series with 194 ~ connected at each end of the bus

Bus drivers

r T L family

TTL family

Three state (TS HC) high current

Ioi = 64 mA at 0.6 V

Ioi = 64 mA at 0.55 V

Three state (TS LC} low current

Ioi = 48 mA at 0,6 V

Totem pole (TP HC) high current

Ioi - 48 mA at 0,6 V

Totem pole (TP LC) low current

Iol = 8 mA at 0.6 V

Iol = 8 mA at 0.6 V

Open collector (OC)

Iol = 40 mA at i3.7 V

Bus receivers Special (HYS) (positive threshold

TTL family

Iol = 40 mA at 0.7V TTL family

Vih - 1.0 V rain 2.7 V max Vil= 0.8 V rain 1,8 V max 0,2 V rain

Vih - 1.0 V rain 2.7 V max Vil = 0,8 V max 1.8 V max 0.2 V rain

Vih = 0.8 V min 2.0 V max Vil - 0,8 V min 2,0 V max

Vih = 0.8 V min 2.0 V max Vil - 0.8 V rain 2.0 V max

Drivers Receivers

Daisychain

D IB arbitration bus Bus request levels Prioritized

(negative threshold (h ysteresisl Standard (STD) (positive threshold (negative threshold

Data Iransler bus Data width (option) Drivers Receivers Sense Smallest add ressable data location Data parity

Address width (option)

476

V E RSAbus

Double Eurocard

1oi = 64 mA at 0,55 V

16-bit 32-bit TS LC STD

TS LC $I D

16-bit 32-bit TS LC STD

noninverted

noninver ted

inverted

g-bit byte No

8-bit byte No

8-bit byte Yes. 2-bit, even parity. (4-bit with 32-bit expansion)

23-bit + derived AO 31 bit + derived AO

Address modiliers

6-bit + interrupt acknowledge line

Drivers Receivers Sense

[S LC SI D noninvcl led

16-bi t

23-bit + derivedAO

23-bit + derivedAO 31-bit + derived AO

8-bit

TS LC 51 D noninverled

TS LC STD inverted

AC failure System failure System reset

Power connections PI pins used for +5 V +5 V standby ~-12V -12 V Ground P2 pins used for +5 V +12V -12 V Ground

-(3 with 32-bit option)

- (4 with 32-bit option)

-

-

Yes, 1 bit (2-bit with32-bit expansion)

4 2 24

6 2 2 6 (10 with 32-bit option)

Analogue power +15 V -15V Ground Note: all voltages are externally regulated

microprocessors and m icrosystems

Figure 3. Rack system for VMEbus more memory intensive programming. He may also choose to increase system throughout by adding another processor board. In each case, the incremental cost to enhance system performance is small.

LOGICAL DESCRIPTION The VERSAbus and VMEbus have similar architectures. Table 1 lists the features of each. Figure 4 shows respective board sizes. The bus architectures can be broken down into five separate buses, the data transfer bus (DTB), priority interrupt bus, DTI3 arbitration bus, utility bus and the interintelligence bus (11B). The data transfer bus consists of a 16-bit data path (expandible to 32-bit via the second connector), a 23-bit address path (expandible to 31-bit via the second connector), resource protection and cycle definition bits (called address modifiers), and the necessary control signals to coordinate data transfers between a bus master and a bus slave. The address and data paths are not multiplexed. Three control lines are used to dynamically determine the data transfer width. These lines, labelled LWORD*, DSO*, AND DS1 *, also determine which set of data lines will be used to make the data transfers. If LWORD* (long word) is high, the data transfer type will be either a 16-bit word or 8-bit byte. DS0* (data strobe 0) controls data transfers on D0-D7 of the bus, and DS1 * (data strobe 1) controls data transfers on D8-D15 of the bus. When LWORD* is low, the data transfer type will be a 32-bit word.

VERSAbus board

VMEbus board Single Eurocclrd VMEbus board Double Eurocard PI /

P2

P;)

~

PI

Figure 4. Board size comparisons (component side)

re~ 6 no 9 november 1982

Each slave in a system may be dynamically or statically configured to respond to single or multiple address modifier codes, or may be designed to respond to different addresses based upon certain address modifier codes. If there are several masters in a system, each may be identified by its own set of address modifier codes. Slave boards may respond to only certain address modifier codes during data transfers. This partitioning of resources helps to prevent a single malfunctioning master from taking the entire system down. A set of address modifiers is reserved to indicate when memory is being accessed in a sequential mode. When this mode is sensed by memory slaves, they latch the address into a counter and increment the counter after each oddbyte data transfer. Each memory board then tests to see if the new address is within its addressing bounds. If the address is within bounds, the memory board performs the data transfer specified by the bus master. The priority interrupt bus allows interrupt generation from multiple devices. There are seven interrupt lines on the bus labelled I RQ1 * through I RQ7*. The '*' indicates low true. Also included is an acknowledge daisychain. This daisychain permits more than one system resource to generate an interrupt on a shared interrupt line. The resource that is configured to respond to the interrupts uses the DTB and the acknowledge daisychain to signal the interrupter that it is responding to an interrupt. Multiple masters can gain orderly access to slave resources via the DTB arbitration bus. Potential bus masters request and receive bus mastership via the bus request and bus grant lines. There are five bus request lines (four on the VMEbus). The bus mastership is granted to the highest priority request line. If more than five masters (four on VMEbus) need to request the bus, two can share a common bus request line. Bus grants from the bus arbiter are daisychained, and the first master in the daisychain has the highest priority. Appendices A - E show the DIN assignments for VERSAbus and VMEbus (in Eurocard format). Broadcasted system status and control signals are handled by the utility bus. The signals handled by this bus include test status (not on VMEbus), system failure status, power failure notification, system reset/reinitialization control and a free running 16 MHz system clock. In multiprocessor systems, resources are usually shared by many processors. The major interprocessor communications path in small multiprocessor systems is often global memory, but as the number of processors in a system grows, so does bus traffic. The DTB becomes the most time-critical system resource. To keep the DTB from becoming a bottleneck, the interintelligence bus was created. This two-wire 4 MHz synchronous serial bus is used to pass short messages between multiple intelligent boards and frees the DTB of th is traffic.

PROTOCOL The protocol for the various buses is relatively straightforward and can be shown using the sequence diagrams. Sequence diagrams (Figure 5) show the protocol layer for write and read data transfer cycles. Figure 6 shows the readmodify-write (r-m-w) cycle protocol. The r-m-w cycle is a concatenation of the read and write cycles while holding the address strobe low on the bus. The cycle is not interruptable by another bus master, and thus forms the kind of indivisible operation required, in multiple-processor systems for coordinating access to shared data.

477

DTB master

DTB slave

DTB master

Initiate cycle

Initiate c'r CIc

•

place address on the bus

•

•

assert address and data strobes

•

DTB slave

place address and data on the bus assert address and data str~be~

Respond to master

•

•

• •

remove address and data from the bus negate address and dat~ st rol~cs

•

Terminate response

removedata from thebus • negate data transfer acknowledge

•

I

I.i&. °~,~cycle

acknowledge

) BG2OUi

I

W~ Initiate next cycle

J,

Detect bus clear Negate busbusy and complete current transfer

Assert bus grant 2

I e r m i n a ~ respanse • ncgalt data tran~c~

1'

BG21N o r, BG2OU f (daisscham)

BG21N

• Assert bus bus~ • Negate bus requtsi 2

Figure 5. Sequence diagram I; protocol for D TB-read cycle (left) and sequence diagram 2; protocol for D TB-write

•

Negate bus grant 2 Drive bu~ grant 2 out high

cede (right)

I

Wail [or c~Jmpletiurl ot previous bus Cycle

• D ] B slave

u , J ~ . , 'e,~i h

\.,Lrt bu. ~quLq 2

I

J.

~trobes

DT B master

•

Pk,dom3in~,d,Ha hanste1~

I

,1~ cycle qermlnate

receive data remove address from the bus negate address and data

•

1

I Ter~minate cycle

IRaLIaC%L, Ue ;u, .n k,d 2

Asserl bus clea¢ (culrent bus mastel bevel I i

rcceivcdata assert data transter acknowledge

• •

De~io 2

!Requesh thL' bu~ on IcvD H

$

Respond to ma~ter

placedataontbebus assert data transfer ac kno~cledge

• •

Device [

Perform data transfer~

DTB slave

DTB master

•

Iniuatecycie

End read, ~tart wr~te

• Place address on the bus • Assertaddressanddata str~)bes

• •

Place data on the bus Assertdatastrobes

•

I

Respond'to master Respond to master

Place data on tbe bus Assert data uansfm acknowledge

I

Term,nate read Receive data N e~,ate data strobes

•

Remove address and data from the bus

•

Negate address and data strobes I

Terminate r~lrcsponsc •

) BSIOUT

•

Negate data transfer

acgn;w,edgc'

,I, Initiate next cycle

Intelrupter

Negate bus grant I I •

Initiate interr upl un line g

IrfiPale interlupl on Ime ;

•

•

Asserlinter[upt4

Asscrtintcrrupt4

i

Sense interrupt 4 asserted Place address=4 on bus Assert address and data strobes

I

J.

&

Respond

Respond

• •

• ~.ail h)r a~knowlcdge in daiq~ lhai

Sense acknowledge-in asselted Place interrupt message on data bus Negate interrup~ 4 Assert data transter acknowledge

• •

I

J.

I

Terminate cycle i •

•

Store message Removeaddress from bus Negate address and data strobes

I

4,

4,

Terminate response

[erminate cyde

• •

•

Remove message from data bus Negate data transfer acknowledge

I

,1,

(interrupt will not be processed this cycle)

I

Start next interrupt acknowledge cycle • • • •

BGIlN o u BGIOUf (daisychaini

BDHN [

j~ Negate bus grant 10Lll

•

Negate bus request I

•

Wait lot ct)mplcli~n o~ the previous c~cle Pelfurm data transfers When done with data translulS, negate bu~ DU5~

• !

I

$

Interrupter

Start interrupt acknowledge cycle •

)BG1OU[

• A%crt bus Dus~

•

•

,L

Deleclbusgram I Assert busgrant 1 out I

Figure 6. Sequence diagram 3; protocol for DTB-read/ modify/write cycle Interrupthandler

BGIlN • •

Termin~c response

Remnve data from the bus Negate data transfer acknowledge

I

Assert bus grant I

I

•

I

When done with da~L u ansfers, negate bu~ bes~

J

Receive data Assert data Uansfel acknowledge

,,I, Terminate c~clc

Assert bus t).quc~t I

%air for a bus request

Figure 8. Sequencediagram 5; DTBAB arbitration protocol for two devices requesting the bus on level one and requesting on level two one device Figure 7 shows the interrupt protocol. In this particular case, two interrupters request processor time on the same interrupt line. Their relative position in the daisychain then determines the service order. Any device that generates an interrupt on the VERSAbus or VMEbus must pass a byte to the interrupt handler via the data transfer bus when its active interrupt is acknowledged by the interrupt handler. The bus arbitration protocol is shown in sequence Figure 8. In this case, device 1 requests the bus on level 1, and device 2 requests the bus on level 2. Device 3 also requests the bus on level 1. An liB protocol has been proposed but is still being reviewed at the time of writing.

CompLete current inter rupl task Sense interrupt 4 asserted Place address=4 on bus

Assert address and data strobes

BUS DRIVERS

I Respond

Respond

• Sense acknowledge-in asserted • Asset t acknowledge out

•

Wait for acknowledge in

• Sense acknowledge-in asserted • • •

Place interrupt messaga on data bus Negate interrupt d Assert data transfer acknowledge

I

& Terminate cycle • Store messaga • Remove address from bus • Negate address and data strobes

Term~inate cycle

Term~mate response

•

:

Negate acknowledge-oul

I

Remove message N~gate data transfer acknowb, dga

Wait for next interrupt

Figure Z Sequence diagram 4; interrupt protocol for two interrupting devices interrupting on the same level

4 78

TTL family devices are used to interface to both the VMEbus and the VERSAbus. All bus timing is specified at the bus connections to the printed circuit board. A TTL buffer driving the normal specification test load is very different from the same part driving a bus. A bus acts as a transmission line to signal transitions. The transmission line characteristics of the VMEbus and VERSAbus provide a driver load that is an order of magnitude greater than the typical test load. The timing specifications for many buffers in the TTL family are not valid for these heavy loads. Therefore, both bus specifications recommend certain types of bus drivers, and include design guidelines so that the board designer need not study transmission line theory in order to interface his particular design to these buses.

microprocessors and microsystems

i---

I

I i-"

F

System I controller I I I I i- --

I

II II II -

'I

. . . .

-41-

--r'--

--!-,iSystem defined by specification

',,,er

I

.O,er I

B

I

z"

z"

ii I

", I

,,,

ii E

II

li] I

ii iI

,7

]1

II

II

J

"~,

_

,,,

II

<~'11

ii JI . . . . .

,J'

[ controller

l

II II II ii II

I

I

I JI

_

Ill

II

J

/I

'L.

Datatransferb u s \

,\

~,2

J I>Priority i.nterrup

I~>DTBarbitration /

>ut,ity v/ <

ITB

in

New-protocoldefinition progress

Figure 9. Functional modules and buses contained within the VERSAbus and VMEbus specifications Odd pin

THE FUTURE Figure 9 shows the basic building blocks of a VMEbus/ VERSAbus system. Implementing these functional blocks in discrete logic uses up a significant amount of board real estate. This fact was noted in the beginning of the specification definition stages. Rather than compromise bus performance, it was decided that much of the required logic could be integrated into a few integrated circuits. The specifications provide the necessary information for this next major step, and several functions have already been integrated or are in design (as of this writing, Motorola is currently offering the MC68452 bus arbitration module, and is developing a bus interrupter module). As more manufacturers c o m m i t to using the VMEbus and V E R S A b u s for their board level

interconnect structure, the list of integrated functions will increase. The result will be a collection of standardized bus interface parts which greatly simplify the design of high performance boards. Copies of the complete VE RSAbus specifications can be obtained from Motorola. Latest VME specification (REV B - August 1982) can be obtained from Motorola, Mostek or Signetics.

APPENDIX A VERSAboard edge connector P1 Odd pin number (P1

Signal mnemonic

component side)

-

Even pin number (P1

pin assignments Signal mnemonic

solder side)

1

+5 V

2

+5 V

3

GND

4

GND

5 7 9 11 13

D00* D02* D04* D06* D08*

6 8 10 12 14

D01* D03* D05* D07* D09*

vol 6 no 9 november 1982.

number (P1 component side) 15

17 19

21 23 25

27 29 31 33 35 -37 39 41

43 45 47 49 51

53 55 57 59

61 63

6s 67 69 71 73 75 77 79 81

83 85 87

Signal mnemonic

DI 0* D12" D14" DPARITY0* GND DS0* GND DTAC K* GND APARITY0* LWORD* A02* A04*

A06* A08* A10* A12" A14" A16" A18" A20* A22" AM4* GND AM3* TEST0* GND ACCLK GND [RESERVED] [RESERVED] [RESERVED] TESTI* BERR* AM0* AM2* IRQI*

Even pin number (P1 solder side)

16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88

Signal mnemonic

D11" D13" D15" DPARITYI* GND DSI* GND AS* GND WRITE* A01* A03*

AOS* A07* A09* Al1" A13" A15" A17" A19" A21" A23"

AM7* GND [RESERVED] [RESERVED] GND SYSCLK GND SYSRESET* [RESERVED] ACFAIL* SYSFAIL* [RESERVED] AM1* AM6* IRQ2*

continued

479

APPENDIX A (cont.) Odd pin number (P1 component side]

Signal mnemonic

89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127

IRQ3* I RQ5* IRQ7* ACKIN* BG01N* BGIlN* BG21N* BG31N* BG41N* BR0* BR2*

BR4* BCLR* [RESERVED] APVAL* GND -12 V GND

+12V +12 V

Even pin number (P1 solder side)

90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128

Signal mnemonic

IRQ4* I RQ6* AM5* ACKOUT* BGOUT* BG1OUT* BG2OUT* BG3OUT* BG4OUT* BR1 * BR3* BBSY* BREL* [RESERVED] DPVAL* GND -12 V GND

+12 V +12 V

1 29

+5 V

130

+5 V

131 133 135 137 139

+5 V +5 V STDBY GND GND GND

132 134 136 138 140

+5 V +5 V STDBY GND GND GND

APPENDIX B VERSAboard edge connector P2 - pin assignments for the expanded bus option Odd pin number (P2 component side) 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53

55 57 59 61 63 65 67 69

480

Signal mnemonic

GND GND GND +5 V +S V +12V GND (± 15 V) -12V [IIO PIN] [1/O PIN] [1/O PIN] [I/O PIN] [I/O PIN] [IIO PIN] [IIO PIN] [1/O PIN] [1/O PIN] [1/O PIN] [1/O PIN] [1/O PIN] [1/O PIN] [I/O PIN] [1/O PIN] [1/O PIN] [1/O PIN] [1/O PIN] [IIO PIN] [l/O PIN] [I/O PIN] [110 PIN] [110 PIN] [I/O PIN] [110 PIN] -I 5 V +15 V

Even pin number (P2 solder side) 2 4 6 8 10 12 14 16 18

20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56

58 60 62 64 66 68 70

Signal mnemonic

GND GND GND +5 V +5 V +12V GND (_+ 15 V) -12V [IIO PIN] [1/O PIN] [1/O PIN] [1/O PIN] [I/O PIN] [IIO PIN] [IIO PIN] [1/O PIN] [I/O PIN] [I/O PIN] [1/O PIN] [I/O PIN] [I/O PIN] [I/O PIN] [I/O PIN] [1/O PIN] [1/O PIN] [I/O PIN] [IIO PIN] [I/O PIN] [I/O PIN] [1/O PIN] [I/O PIN] [I/O PIN] [110 PIN] -15 V +15 V

Odd pin number (P2 component side) 71 73 75 77

79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119

Signal mnemonic

[RESERVED[ [RESERVED[ [RESERVED] [RESERVED] [RESERVED] [RESERVED] [RESERVED] [RESERVED] [RESERVED] A24" A26" A28" A30*

Even pin number (P2 solder side) 72 74 76 78 80 82 84 86 88 90 92 94 96

Signal mnemonic

[RESERVED] [RESERVED] [RESERVED] ]RESERVED] [RESERVED] [RESERVED] [RESERVED] [RESERVED] APARITYI* A25" A27. A29. A31"

GND [RESERVED]

98 100

GND [RESERVED]

GND DPARITY2* D16" D18" D20* D22" D24" D26" D28" D20*

102 104 106 108 110 112 114 116 118 120

GND DPARITY3* D17" D19" D21" D23" D25' D27" D29" D31"

Note: pins 17-66 are not bussed together by the backplane

APPENDIX C VE RSAboard P2 pin assignments for the nonexl~nded bus option Odd pin number (P2 component side] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 5s 57 59 61 63 65 67 69 71

Signal mnemonic

Even pin number (P2 solder side)

GND GND GND +5 V +5 V +12 V GND(± 15V) -12V [I/O PIN] [I/O PIN] [I/O PIN] [I/O PIN] [1/O PIN] [IIO PIN] [IIO PIN] [IIO PIN] [IIO PIN] [I/O PiN] [I/O PIN] [I/O PIN] [I/O PIN] [I/O PIN] [1/O PIN] [1/O PIN] [1/O PIN] [IIO PIN] [I/O PIN] [tlO PIN] [l/O PIN] [I/O PIN] [IIO PIN] [IIO PIN] [IIO PIN] -15 V +I 5 V [110 PIN]

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 S6 58 60 62 64 66 68 70 72

Signal mnemonic

GND GND GND +5 V +5 V +12V

GND (_+ 15 V) -12V [IIO PIN] [IIO PIN] [IIO PIN] [IIO PIN] [IIO PIN] [IIO PIN] [IIO PIN] [IIO PIN] [110 PIN] [IIO PIN] [ l / o PIN] [110 PIN] [1/O PIN]

[1/0 PIN] [IIO PIN] [1/O PIN] [I/O PIN] [1/O PIN] [I/O PIN] [1/O PIN] [I/O PIN] [I/O PIN] [I/O PIN] [I/O PIN] [IIO PIN] -15 V +ISV

[IIO PIN]

microprocessors and microsystems

APPENDIX

C (cont.)

Odd pin number (P2 component side)

Signal mnemonic

73 75 77 79 81 83 85 87 89 91 93 95

[IIO [1/O [I/O [I/O [I/O [IIO [I/O [I/O [I/O [I/O [I/O [I/O

APPENDIX

D

VMEboard

PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN]

Even pin number (P2 solder side)

(

C ( C. (

C. (

8 C 9 (

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

( ( ( ( ~ ( ( ( ( (. ( ( ( (. C ( ( C._ ( (.. ( C (

Signal mnemonic

[I/O [llO [I/O [1/O [I/O [1/0 [I/O [I/O [I/O [I/O [I/O [I/O

74 76 78

80 82 84 86 88 90 92 94 96

PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN] PIN]

VMEboard

b j ) ) ) )

) ) ~ ) ) )

BBSY*

/

( C ( ( C (" ~" ( ( (

BCLR* ACFAIL* BGOIN* BGOOUT*

BGIIN* BGIOUT* BG21N* BG2OUT* BG3IN* BG3OUT* BRO* BRI* BR2*

) ) ") )

(

BR3*

) )

( ( (

AMO AM1 AM2

) ) "~ J ) ) "~ ") )

c

(

AM3 (

( ( ( ( ( (. (

) ) C ) ( ( ) ) (

C

1 ~-

) ( ) C ) ( ) ( ) ( '~ ( ~ ~ C ( ~__. ( ( ~

Dog ) DIO "~ Dll ) D'2 ) O13 ) m4 ) D15 ~ GND ..~ SYSFAIL* ) BERR* "~ SYSRESE'r* ) LWORD* ~ AM5* ..~

2 ( 3 C 4 ( 5

(. ( C C .) ("

.~.3 ,~.2

) )

A21 ~.o

..) )

A,9 A18 A17 A16 A15 A14 A13 A12 All

6 7 8 9

10 11 12 13

~) ) )

A28 A29 A3O

) ) ) )

( ( ( (-

A31 GNO

) )

C C

+5 V D16 D17 o18 D19 020 D21 022 023

(

GND

( ( C ((

( C ( ( (" ( (.

~-~ . ( ; )

( (

14

User I/0

"--~

useruo

~

UserI/O UserI/O UserI/O

) C ,) (" ) C

)

15 16 17 ( 18 C 19 (

)

20 C

) )

21 (

~ )

IRO3*

)

(

Ale

)

IRO2*

) )

( (

A09 A08

) )

) )

C (

+12v +sv

~ )

31 ( 32 <

+sv

UserI/O UserI/O t.JserI/O UserI/O UserI/O UserI/O

( ( ( ( ( (

userI/o UserWO

( ( ( ( (

IRQI*

) ) ) ) )

) ) ) )

)

user,/o

)

UserI/O use, I/o UserI/O User1/0 UserI/O user,;o user,/o user,/O Userl/O userl/o Userl/O Userl/O

~ __~ ~'~ ~ ) ) ) )

Userl/O

)

~"

(

(

~) ( ) ) ~

b +sv ~-ND RESERVED A24 A25 A26 A27

, ) ) ) ) =;

.J

UserI/O UserI/O User,/O userWo UserI/0

(

22 C 23 (, 24 ( 25 ( 26 ( 27 ( 28 C 29 ( 30 (

+SVSTDBY

- P2 pin assignments

)

GNO SERCLKt SERDATI" GND IRO7* IRO6* IRQS* IRQ4*

C (

Signal mnemonic

E

a ~

(

D0a

Even pin number (P2 solder side)

97 [I/O PIN] 98 [1/O PIN] 99 [I/O PIN] 100 [1/O PIN] 102 [1/O PIN] 101 [I/O PIN] 104 [1/O PIN] 103 [I/O PIN] 106 [I/O PIN] 105 [I/O PIN] 108 [I/O PIN] 107 [I/O PIN] 110 [I/O PIN] 109 [I/O PIN] 112 [1/O PIN] 111 [1/0 PIN] 114 [I/0 PIN] 113 [I/O PIN] 116 [I/0 PIN] 115 [I/O PIN] 118 [I/O PIN] 117 [I/O PIN] 120 [IIO PIN] 119 [1/0 PIN] Note: pins 17-66 and pins 71--120 are not bussed together by the backplane

- P1 pin assignments

DOe DO1 DO2 DO3 Do4 DO5 Do6 DOT GND SYSCLK GND DSI* DSO* WRITE* GND DTACK* GND AS* GND lACK* IACKIN* IACKOUT* AM4 AO7 A06 A0S A04 A03 AO2 AO, q2v +sv

Signal mnemonic

APPENDIX

a 1 2 3 4 5 6 7

Odd pin number (P2 component side)

( C

( (

c Userl/O U,,rUO UlmrI/O UserI/O UserI/O UserI/O UserI/O

) ) ) ) ) )

User II0 UNr I/O

)

C (

u.., ,/o User,/O U..r I/O

) ) )

~( C

UserI/O UserI/0 UserI/O

) ) )

C

us..,/o

)

( (( C

UserI/O UserI/O UserI/O UserI/O

) ) ) )

D24 D25 026

) ) ) .) "~ ) ) ") "; ) ) ) "~

027

)

~2e o2g D3O o3, GND +~ v

) ) ) .~ ) ~

C

User,/O

)

( C (

UserI/O UserI/O UserI/0

) "~ )

C C

u,,,,/o Ueer]/O

(~ (

UserVO UserI/O

) ) )

(

UserI/O

) )

(

Use,,/O

)

( <

UserIiO User,,O

"~

~SERCLK and SERDAT represent provision for a special serial communication bus protocol still being finalized

vol 6 no 9 november 1982

481