Very thin oxides in vlsi technology: Properties and device implications

Very thin oxides in VLSI technology: properties and device implications B. Majkusiak and A. Jakubowski Institute of Microelectronics and Optoelectronics, Technical University of Warsaw, Koszykowa 75, 00-662 Warsaw, Poland The trend existing in MOS VLSI technologyto reduce the oxide thickness is discussed. The basic reasons for the trend, further implications concerning the physical properties of the oxide layer and the performance of the MOS devices, as well as physical limitations, are considered. 1. Introduction When the first 64 kb MOS DRAMs were announced in 1979, integration of the most complex circuits exceeded the level of l0 s components per chip, corresponding to the VLSI class. In currently produced circuits the number of components per chip exceeds 106(e.g. 1 Mb DRAMs) and in experimental chips of 16 Mb DRAMs it exceeds 107 corresponding to the Ultra-Large Scale Integration (ULSI) class [1]. Progress in this direction has been accomplished by increasing chip area and, more efficiently, by increasing the packing density of circuit elements. The increase of packing density has in turn been the result of feature size reduction, and changes in technology resulting from optimization of circuit topology and new technological ideas (e.g. three-dimensional technologies). Recently, several detailed reviews concerning trends in the technology of MOS memories have been published [2,3]. At present, owing to the development of lithography techniques [4], progress in increasing the packing density is limited by yield and reliability problems [5] rather than by technical possibilities of reducing device di.mensions and feature sizes. Some of the reliability limitations result from the increase of electric field in the MOS devices when the supply voltage is not reduced proportionally with the scaling of the device dimensions. These are hot carrier related degradation and breakdown of the very thin gate oxide of a thickness which results from being scaled down together with the planar dimensions. Therefore, properties of the oxide layer and their changes with oxide thickness are of increasing interest at present. This problem will be discussed in Section 2. A decrease in the miniaturization rate can also result from physical limits of the classical scaling theory [6,7]. The scaling rules giving concise design criteria for small dimension MOS circuits do not include some physical phenomena affecting the behavior of MOS devices with very small planar dimensions and a very thin gate oxide layer. Discussion of the device implications of the gate oxide thickness reduction is the main aim of this work, this being one of the most characteristic trends in MOS VLSI technology. The basic reasons for this trend and its further implications concerning the performance of MOS devices, as well as physical limitations, will be considered in Sections 3 and 4.

MICROELECTRONICS JOURNAL Vol. 21 No. 2 © 1990 Elsevier Science Publishers Ltd., England

21

B. Majkusiak and A. Jakubowski

22

In general, the very thin oxide layer can be applied in a VLSI circuit as: (1) (2) (3)

(4)

a gate oxide in the MOS transistor; a capacitor oxide, i.e. a dielectric layer in the capacitor of the MOS DRAM cell; a gate oxide in the MOS transistor of the EPROM or EEPROM cell, where the write/erase operations are based on Fowler-Nordheim tunneling or hot carrier mject~on; an ultrathin tunnel oxide in the EEPROM cell based on the MNOS or SNOS structure.

Attention will mainly be focused on the first two applications due to the fact that further scaling of the tunnel oxide thickness in EEPROM cells is difficult because of retention requirements [8].

2. Physical properties It follows from the previous section that oxide layers ranging in thickness from a few to several tens ofnanometers (depending on the application case) can be found in today's VLSI circuits. Tunnel currents determining both write/erase operation times in some types of EEPROM cells and the minimum oxide thickness in MOS devices are determined by such parameters as the SiO2-Si potential barrier height and the electron effective mass in the oxide m~. The barrier height also determines the efficiency of the hot electron injection mechanism used in the write operation in EEPROM cells and is simultaneously responsible for reliability degradation. Electro-physical parameters of the SiO2-Si system are well determined for the case of a "thick" oxide, i.e. when the thickness of the SiO2 layer is many times 2.10 lz mi mo

"X.c[eV]

,

0.6-

,3.U

O

X

•

o

0.5

Qeff/q

[cm "z] •

1012

2.0 x

o m;/ITI 0

0.4

0.3 0

1.0

•

'X. C

x

O, e f f / / q

i 1.0

o

i 2.0

L 3.0

x o

I 4.0

5.00

tl [nm] Fig. 1 The decrease of the SiOz-Si barrier height Xc for t~ < 3 . 5 nm and the increase of the electron effective mass m~ with the oxide thickness reduction t~ [15]

Very thin oxides in VLSI technology: properties and device implications

23

greater than the thickness of the SiO2-Si transition region, with composition and properties different from the bulk SiO> Due to the existence of this region, parameters of the MOS system with oxide thickness only a little thicker, are expected to be dependent on the thickness of the oxide. According to internal photoemission measurements the barrier height for oxides thicker than 4.3 nm is the same as for "thick" oxides [9]. However, experimental works based on analysis of tunnel current suggest that Xcdecreases with decreasing oxide thickness [10-15]. Figure 1 shows parameters of the ultrathin SiO2-Si system obtained from fitting theoretical current-voltage characteristics of the AI-SiO2-Si tunnel diode to experimental ones [15]. The SiO2-Si barrier height decreases with decreasing the oxide thickness provided t~ < 3.4 nm. The effective potential barrier height is also dependent on the substrate doping concentration. Its lowering was observed for oxides grown on heavily doped substrates [8] or after high dose arsenic implantation [16]. As shown in Fig. 1, the increase of the electron effective mass m~in the ultrathin oxide with its thickness decreasing was obtained by Majkusiak et al. [15], in a similar manner to Waiters and Peck [14]. Since the oxide thickness in MOS devices in VLSI circuits is reduced virtually without any proportional reduction of supply voltage, the oxides work under conditions of increased electric field. Fowler-Nordheim tunneling and hot carrier injection of electrons into the oxide conduction band causes generation and charging of bulk and interface oxide traps, which in turn leads [17,18] to the MOSFET's threshold voltage shift, subthreshold swing increase and the channel carrier mobility degradation resulting in the transconductance decrease [17]. The physical mechanism of electron injection induced oxide trap generation and positive charge trapping is quite well understood (see recent works reviewed by Fischetti et al. [19]), but there are still some unanswered questions. These works show that hot electrons reaching the SiO2-anode interface with sufficiently large kinetic energy (above about 2 eV) [20] are directly responsible for the generation of oxide traps. The average kinetic energy of electrons is dependent on the oxide field strength [20], provided they are not thermalized at the bottom oi'the oxide conduction band by polar scattering when the oxide electric field is too small (below about 1.5 MV cm -~) [21,22]. Electrons losing their energy at the SiO2-anode interface release some mobile species (holes from the poly-Si gate or hydrogen atoms from Si-H bonds at the interface -- although it is not known which -- which in turn migrate toward the SiO2-cathode interface and react near it to generate oxide traps. The probability of hole generation in the oxide by impact ionization is expected to be very small because of the large gap of S i O 2 in comparison with the average kinetic energy of electrons in the oxide conduction band. Therefore, according to this model, reduction of oxide thickness can affect the rate of generation of oxide traps by reducing the distance required for injected electrons to reach the steady state energy at a given oxide field and by reducing the distance for the species generated at the SiO2-anode interface to travel to the opposite interface. The first influence could be effective for oxides less than 10 nm thick, i.e. comparable to the sum of the electron energy relaxation distance in SiO2 (about 3 nm [23]) and the FowlerNordheim tunneling distance (about 3 nm depending on the oxide electric field), and should cause a decrease of the oxide degeneration rate. Experimentally, a decrease of the rate of generation of bulk oxide or interface traps with oxide thickness

B. Majkusiak and ,4. Jakubowski

24

reduction has been observed [24-29] for very thin oxides. However, a weak influence of oxide thickness has been observed [20,23,30], especially for "thick" oxides. Electron injection is one of the phenomena which accelerate the time-dependent breakdown mechanism; therefore, thinning the oxide should cause an increase of its time-to-breakdown tBDprovided the generation of oxide traps and their positive charging is really reduced in very thin oxides. Yamabe and co-worker [31,32] have distinguished three types of oxide breakdown. (1) Low-field breakdown. This type has a short-term character. Pinhole defects induced by substrate surface contaminations before the oxidation process are mainly responsible. The density of these defects increases with decreasing the oxide thickness [28,32,33], but it can be significantly reduced [32] by an improvement of the cleanliness conditions in the technological environment. (2) Medium-field breakdown. This limits the lifetime of MOS devices, since it appears after some work time tao, which is exponentially dependent on the oxide electric field [34,35]. This breakdown may be induced by metallic contamination of the substrate. The contaminations are transported to the oxide during high temperature processes and create the so-called weak spots [32]. However, the density of the defects of this type decreases with decreasing oxide thickness [28,32,33,36], and in the thickness range of about a few nanometers this type of breakdown should not dominate. Since the lower voltage limit of this type of breakdown, determined by the efficiency of thermal breakdown mechanism, increases with oxide thickness reduction, it is difficult to distinguish this mode of breakdown from intrinsic breakdown in oxides less than 15 nm thick [31]. (3) Intrinsic breakdown occuring in non-defected oxide. This also has a timedependent character. By applying the model of oxide degradation caused by electron injection described above, the mechanism of intrinsic breakdown may be explained by positive feedback in a loop created by Fowler-Nordheim injection of electrons into the oxide conduction band, accelerating them by the oxide electric field, the generation of some positive species by the heated electrons, transport of the generated species toward the SiO2-substrate interface, and generation of oxide traps and their positive charging near the injecting interface, which makes the electron injection process more effective due to the modification of the electric field. Experimentally, an increase of taD with oxide thickness reduction has been observed [25,28], which supports this model as far as the oxide thickness dependence of the generation of oxide traps and positive charge trapping in the very thin oxides is concerned. However, the independence of tBo of the oxide thickness, and even its decrease with oxide thinning in the range of large oxide electric fields, has been observed by Moazzami et al. [37] and Liang and Choi [35] respectively. Charge-tobreakdown QBo, i.e. the electron charge injected into the oxide conduction band before breakdown occurs, is independent of the oxide thickness for "thick" oxides (t~ > about 10 nm) [38,39]. QBD increases with oxide thinning for low electric fields and injected currents, and decreases for large fields and currents [27,38]. 3. Gate oxide in the M O S transistor

There are two main advantages in the reduction of the gate oxide thickness: the

Very thin oxides in VLSI technology: properties and device implications

25

increase of the transistor transconductance, which in turn improves the circuit speed, and preservation of the long-channel character of the transistor performance. Brews et al. [40] proposed an analytical formula relating the oxide thickness to the channel length to ensure the long-channel behaviour of the MOS transistor. The minimum channel length depends on the oxide thickness t~, the junction depth xj and the sum of the source and drain depletion layer widths (Ws+WD) in the following way: Lmin

=

A[xjti(Ws+WD)2]

v'

where A is a constant. Figure 2 shows the minimum channel length obtained from this formula for given values of the MOSFET's parameters as a function of gate oxide thickness t+ Reduction of the gate oxide thickness can ensure the longchannel performance of the MOSFET even with deep submicron channels. The long-channel behaviour of the MOSFET with a 0.15 pm channel and a 2.5 nm thick oxide has been reported [41]. The threshold voltage shift from the corresponding long-channel value due to short-channel and drain induced barrier lowering (DIBL) effects decreases with the reduction in oxide thickness [42].

5

xl "', 0.35/.sm

1

N~;o = 102oera-3

NB [

4 Vos.lV

~

~

--

I

1 0

0

I

I

I

i

l

20

40

60

80

100

ti Inml Fig. 2 Minimal channel length for long-channel performance of MOSFET according to the formula proposed in ref. 40

The reduction in gate oxide thickness seems to be the most effective way to avoid short-channel effects with the simultaneous increase of transistor transconductance. Reduction of the junction depth causes increases in the source and drain parasitic resistances, which in turn reduce the transconductance. The increase of the substrate doping concentration reduces depletion regions but also causes an undesirable increase of the body factor. According to the simplest model of the

26

B. Majkusiak and A. Jakubowski

MOS transistor, its transconductance should be proportional to the oxide capacitance C~ = e~/t~, i.e. reversely proportional to its thickness t~: gmo =

(W/L) ~CiVos

Here gm0 is the transconductance for low drain-source voltages resulting from the simplest model, ~ is the channel cartier mobility for low values of transverse and lateral components of the electric field in the channel. However, practically, the oxide thickness dependence of the transconductance is weaker than suggested by the simplest theory. There are two reasons for the degradation of the transconductance: the degradation of the cartier mobility due to the increase of the transverse electric field in the channel, and the finite inversion layer capacitance. The real transconductance gm for the low drain-source voltages can be expressed [43] as the product of the field-effect mobility ~tvE,which is lower than Po, and the gate channel capacitance Cg~, which is lower than the gate oxide capacitance C~: gm =

(W/L) ~FECgcVDS

Figure 3 shows the relation between gm and t~resulting from theoretical simulation. The dashed line represents the ideal case, i.e. ~t~E = ~0 and Cgc -- C~. t~ I n m l 700

100 50 ,

20

,

10 /

o

5 t

/

800 g-E

/ / / /

500

400

/

3oo " ~ .,,,,r

,ook 0 ~

0

/

/po

I

I

I

I

I

I

100

200

300

400

SO0

600

Ci

Fig. 3

700

[nF/cm 2 ]

Reasons for the MOSFET's transconductance degradation: the mobility degradation and the gate channel capacitance influence

The surface carrier mobility is affected by the transverse electric field in the channel. We assumed in calculations leading to Fig. 3 that: ~rt = Luo/(1 + eEort)

Very thin oxides in VLSI technology: properties and device implications

27

where Eerr is the effective transverse field in the channel and 0 is a constant. We assumed the value 0 = 3× 10-6 cm V -I close to the experimental one obtained for electrons by Wong et al. [44]. Reduction of the oxide thickness causes an increase of the transverse field in the channel if the supply voltage is the same and, in consequence, the decrease of the mobility. It is worth noticing that the effective mobility is independent of the oxide thickness at the same value of E~, [25,45,46]. The effect of the finite inversion layer capacitance implies that the gate oxide capacitance Ci = e~/t~becomes comparable with the large but finite inversion layer capacitance Ci,v = -dQ~.v/dp~ for the strong inversion state when the gate oxide is reduced, and then the gate channel capacitance Cgc becomes considerably lower than the oxide capacitance. Figure 4 shows the comparison of the influence of both the effects mentioned above on the transconductance. As it can be seen, the mobility degradation is the main reason for the transconductance degradation when the oxide thickness is reduced from 100 to 10 nm. 1.0

"~-&

0.8

~.~

0.6

z/

~Jo

.............

I

"",...

(1.4 o E

"~E

0.2 NA = 2"101scrrf~ o

-1

J

0

9 == 3" 10"~cm/V I

I

I

I

1

2

3

/*

V~s -

Vr

5

[VI

Fig. 4 Comparison of the influences of mobility degradation and finite inversion layer capacitance on the MOSFET's transconductance in dependence on gate source voltage and gate oxide thickness

Reduction of the gate oxide thickness also causes strong modulation of the effective mobility along the channel due to its influence on the distribution of the effective transverse electric field E~rf. Figure 5 shows the behavior of the transverse electric field in the channel Eou with the electron quasi-Fermi level split V,(y) along the channel as the result of calculations for various gate oxide thicknesses [47]. Assuming that in the strong inversion region Vo(y) = V(y), where V(y) is the position-dependent part of the semiconductor surface potential Ps(Y) = Ps0 + Vn(y), and that the depletion layer charge is QB(Y) = -C~y [2~+VsB+V(y)] '~, the effective transverse field distribution can be expressed in the following way: Eeu(Y) = I 1/2Qi"v+QB ] es = _ C_i I VGB -- V~u - Ps0 - V(y)+y [2~F+VB+V(y)I'~[ es 2es where g = (2esqNA)'a/Ci is the "'body factor".

B. Majkusiak and A. Jakubowski

28

6 ~tl

Ves=0

=Snm

v~s -vr =Z.0 v %

3

ti =10nm

0

ti = 10Ohm ,

0

l

I

I

I

2

V.(y) [Vl

Fig. 5 The effective transverse electric field vs. the electron quasi-Fermi level split V, along the channel for M O S transistors with various gate oxide thicknesses

It can be seen in Fig. 5 that Eeff,the carrier mobility, is almost constant along the channel for thick oxides (Eeffcan increase with V, for large values of the body factor), but E,n-becomes a strong, nearly linear function of Vn for transistors with a very thin gate oxide. The modulation of the effective transverse field and the carrier mobility along the channel could not be neglected in analytical modeling of MOS transistors with a very thin gate oxide. Another effect which becomes important in the modeling of MOS transistors with a very thin gate oxide is the surface potential increase in the strong inversion state. Many simple models assume that Ps0 = 2 ~ v , when the gate source voltage exceeds the threshold voltage; in fact, Ps still increases. Figure 6 shows the increment of the surface potential Ps in the strong inversion state over the doubled Fermi potential 25F as a function of the gate voltage. When the oxide thickness is very thin, e.g. I0 nm, the increment of the surface potential reaches the level of about 400 mV for Vos - VT = 5 V. This value is comparable with the surface potential at the onset of the strong inversion state 25v: therefore, neglect of this increment in modeling must be a source of significant errors. Calculations leading to Fig. 6 were performed using Fermi-Dirac statistics. The semiconductor surface region of a transistor with a very thin gate oxide or with a high substrate doping concentration becomes degenerate at quite small gate voltages. For example, the voltage difference VGS -- VT needed to bring the electron Fermi level at the interface to a position of 3 kT below the silicon conduction band edge is equal to 0.2 V for oxide thickness of 10 nm and doping concentration of 1017 cm -3. This fact casts doubts as to whether these models of the MOS transistor, which are based on Maxwell-Boltzmann statistics, can be used in the case of a transistor with a very thin gate oxide. However, it has been shown theoretically [48] that errors of drain current modeling resulting from the use of MaxwellBoltzmann statistics are small (see Fig. 7).

29

Very thin oxides in VLSI technology: properties and device implications

0.5

lO;Scn~3

N A =" 2"

_; 04~ •

"

z%-

o.6~3v

9e o.2~- / / /

/t;=,

j

5nm

/

~

0.1~ 0 I 0

I 2

I

1

J 3

i 4

5

Vc,s - Vt [Vl Fig. 6 Error of the drain current in saturation with the use of MaxwelI-Boltzmann statistics as a function of gate source voltage with oxide thickness as a parameter [48]

4 NA = 1 0 1 7 c r n

-3

x

': 3

~- 2

II

Jo

I

0

I

1

l

I

I

2

I

3

l

4

VGs- v,r [v] Fig. 7 The increment of the surface potential above its threshold value versus the gate voltage with gate oxide thickness as a parameter

One of the advantages of the reduction of the gate oxide thickness is the limitation of the influence of effective oxide charge on the threshold voltage. If we assume, for example, that Qeff is controlled on a given technological line with accuracy -T-2Xl01°cm -2, the threshold voltage is controlled in the range of T- 100 mV for an oxide 100 nm thick and only T-10 mV for an oxide l0 nm thick. Therefore, in the case of very thin oxides, greater attention should be paid to the control of the work function difference, which becomes the main source of threshold voltage instability. Another problem connected with threshold voltage control appears when parameters of the MOS transistor are changed in accordance with existing trends

B. Majkusiak and ,4. Jakubowsld

30

and scaling rules. The long-channel behavior of a transistor with a channel length o f 0.15 lam, an oxide thickness of 2.5 n m and a substrate doping concentration of over l018 cm -3 has been presented by Horiguchi et al. [41]. If we want to control the threshold voltage with an accuracy 50 mV in a transistor with a substrate doping concentration of l018 cm -3, we must ensure that the control o f the oxide thickness is better than e i A V x / [ 4 e s q N a O F ] ~ ~ 0.3 nm (see Fig. 8). This is the magnitude of the 200

Na [cm-3] =

06

0.2

0.4

0.6

0.8

1.0

& h [nml Fig. 8 Inaccuracy of the threshold voltage control as a function of the inaccuracy of the oxide thickness control for different substrate doping concentrations

10

• experiment theory

II

si <100>

-F--i

~=

"

"lL

2, 0 0

I

,o.=3min

II

20

40

60

80

100

OXIOATION TIME to~ [mini

Fig. 9 Thermal oxide growth cane for oxidation temperature T = 800°C [49]

order of one SiO2 m o n o l a y e r thickness. As shown in the experimental oxide growth curve presented in Fig. 9 [49], if we want to control the oxide thickness to 5 n m with an accuracy o f 0.3 nm, the time o f the oxidation process should be controlled with

Very thin oxides in VLSI technology: properties and device implications

31

an accuracy better than about 3 min even at a rather low process temperature (i.e. 800°C). The time needed for the ambient gas exchange and for stabilization of oxidation conditions is longer. Therefore, in the case of technology with very thin oxides and very large doping concentrations other techniques of thermal oxidation, e.g. the RTO process, should be considered. The threshold voltage of the MOS transistor in future VLSI circuits working at reduced supply voltage will be very small. In this case the slope of the subthreshold characteristic will become a very important parameter. A steep subthreshold characteristic is required for the reduction of the transition voltage range between states of conduction and non-conduction of the transistor. Figure 10 shows the 100,

-- 80

.

.

.

.

~

°t o

40~-

"0

N 9 =,k. 2 • 101Scrn-3

ul

=" ( 100 nrn/tl ]

ii (,/1

0

o

r

I

x

i

2o

40

60

80

tl

100

[nml

Fig. 10 Scaling of the subthreshold swing S

theoretical dependence of the subthreshold swing S as a function of the oxide thickness. The subthreshold swing is defined as the gate voltage change required for the reduction of the subthreshold drain current by a decade. When the doping concentration is maintained, reduction of the oxide thickness causes a linear decrease of this voltage. However, when the doping concentration increases with the square of the oxide thickness reduction, as it follows from the scaling rules with a constant supply voltage, the subthreshold swing is constant. Figure 10 shows the results of calculations for the case of an ideal transistor, i.e. they are based on a theoretical expression [50] neglecting the short-channel effects mentioned above; additionally, zero density of interface traps was assumed. Interface traps cause an increase of the subthreshold swing and the degradation of the mobility of the channel carriers; therefore, hot electron injection may degrade the MOS transistor performance. Reduction of gate oxide thickness affects the lateral electric field distribution near the drain junction, accelerating channel carriers toward the drain region. The increase of the peak substrate current and the hot electron injection gate current with oxide thinning was observed by Yoshida et al. [51]. Theoretical simulation shows that the lateral electric field peak increases but the field beyond it decreases and, therefore, the field distribution for thinner oxides can be less effective in carrier heating in some cases, as was observed

32

B. Majkusiak and A. Jakubowski

experimentally [52]. However, even in the case of increased hot electron injection into the thinner oxide, the MOSFET's performance degradation measured as the drain current reduction was weaker, probably due to mobility degradation by generated interface traps [42,51]. Therefore, it can be generally stated that thin oxide MOS transistors are more resistant to hot carrier induced degradation. In the case of very thin gate oxides the subthreshold characteristic can be additionally affected by both the gate induced drain leakage (GIDL) current and the punchthrough current. Figure ll illustrates the physical mechanism of the

V~s =0

Vos>0

v°sl P

~

(a)

\ [b)

Fig. 11 Illustration of the physical mechanism of the gate induced drain leakage current

GIDL current [53]. Due to the strong electric field in the depletion layer at the surface of the n + drain region, electrons in the semiconductor valence band can effectively tunnel to the conduction band giving the flow of the drain current when the transistor should be in the off state. The gate induced drain leakage current may limit the trend to reduce gate oxide thickness. Therefore, it must be minimized by means of proper design solutions. The punchthrough current in the subthreshold region decreases with oxide thinning [42], which means that the punchthrough breakdown voltage increases. A natural limitation of the trend to decrease gate oxide thickness in MOS transistors in VLSI circuits may result from tunneling of carriers through this oxide. However, although the gate tunnel current increases exponentially with decreasing oxide thickness, the ratio of this current to the drain current is low even for extremely thin oxides. Figure 12 shows the oxide thickness dependence of the electron tunnel current and the drain current for two channel lengths as a result of theoretical modeling [54]. When the channel length is reduced, the drain current (which is reversely proportional to it) increases while the gate tunnel current (which is proportional to the gate area) decreases. Therefore, the ratio IG,u,nJIo decreases in proportion to the square of the channel length when it is reduced in accordance with the trend towards miniaturization. Although the model [54] for the gate tunnel current neglects the heating of electrons in the channel near the drain region, it gives results which are in good agreement with experimental data. The comparison between theoretical [54] and experimental [41] results for a MOS transistor with a 2.5 nm thick oxide is shown in Fig. 13. In order to obtain the experimental gate tunnel current level, the SiO2-Si barrier height L: was assumed to be 2.9 eV.

Very thin oxides in VLSI technology: properties and device implications

10"zI . . . . . .

Io _

-.r

I-o_

',,,3

10/am

,•

-- 10-6

VGS - V r = 2V

[~ ~.~

Vos

IV

'\\\\

%8

0

i0-e

_I hl Z

LLL ---

'

I0"

E

33

lo"'°

Z

ua 10,41

t.) I 1

10-l+

0

I 2

~ 3

I 4

OXlOE THICKNESS [nm ] Fig. 12 A theoretical comparison of oxide thickness dependence of the drain current ID and electron tunnel current l~c for two different channel lengths L [54]

,i 10" ~

/

?

--exoor+m+ !'-lJ ---theory

Io")

N, -- ~.s-d'm -~ N.

~J

nIu~ 10-9L

L = 0.1S,~m W -- 50.xJm Vos

: lV

VSB:O

10"I+! 10-1:!1

[541

~ S " "

olz

t [o

0.6 0.8 1.0 1.2 %s [Vl Fig. 13 The drain current and the gate tunnel current as a function of the gate voltage - experiment [41] and theory [54] 0

0.4

Therefore, concluding, one may state that provided proper design solutions eliminate undesirable effects such as hot electron injection into the gate oxide or GIDL current, the minimum gate oxide thickness in MOS VLSI circuits will probably result from knowledge of how to manufacture very good quality ultrathin oxides in a controllable way rather than from the flow of a gate tunnel current which is too large. This current can limit the m i n i m u m oxide thickness only in some MOS transistor circuit applications, where the problem o f input leakage current is particularly important.

B. Majkusiak and A. Jakubowski

34

4. Capacitor oxide in the MOS DRAM cell In this case of thin oxide application the need to reduce thickness simultaneously with increasing the packing density results from the necessity to store sufficiently high charge on a reduced planar area occupied by the capacitor of the MOS DRAM cell. It must be sufficiently high to ensure a measurable signal voltage when information in the memory capacitor is read and a low soft error rate caused by radiation. Reducing the stored charge causes an exponential increase in the soft error rate [55]. That is why the stored charge should not be less than about 150 fC if the silicon surface region is to serve as the storage electrode [56]. However, the reduction of the oxide thickness with the supply voltage maintained means that the electric field in the oxide increases. This, in turn, implicates a decrease of the lifetime of the oxide due to the time-dependent breakdown and the increase of the leakage of the charge stored in the capacitor. The problem of breakdown resistance of the oxide was discussed above. If this resistance is sufficiently high, the reduction of the oxide thickness can be limited by tunnel outflow of the electron charge stored in the logical zero state. Let us consider the case of the double polysilicon DRAM cell typically used in DRAMs of capacity up to 1 Mb. In this type of cell the information (the electron charge) is stored in the silicon substrate of the MOS capacitor. Figure 14 shows the 10"z

E

10-3

t=[n:l=~

.<

10-~

u

10-5

<

10"s Z Z

10"~

I,,-

3,5 ~0-8 0

I

10-6

2.10"6

3.10"e

4.10"s

Q~T A¢ -'£1Fi [C/cmz] Fig. 14 Tunnel leakage current and critical leakage current densities in MOS DRAM cell

density of the electron tunnel current from the silicon conduction band to the gate electrode vs. the density of the electron charge stored in the substrate Qsv/Ac, which, in turn, determines the electric field in the oxide F~ (Ac is the area occupied by the capacitor). In calculations an SiO2-Si potential barrier height ~ = 3.2 eV and a one-band barrier model with an oxide effective mass m~ = 0.5 mo have been assumed. The dashed line in Fig. 14 represents the critical density of the gate

Very thin oxides in VLSI technology: properties and device implications

35

leakage current causing 1% loss o f the electron charge Qsx during one refresh interval (e.g. ta = 4 ms): Jcrit. = 0.01 (QsT/Ac) / trr

Intersection points o f the solid lines with the dashed line determine maximum stored charge density for a given oxide thickness or the m i n i m u m capacitor area A~. for the m i n i m u m possible value of the total stored charge QST (e.g. 150 fC). Figure 15 shows the critical oxide thickness below which the tunnel leakage current at a given value of the stored charge density is too large. The capacitor oxide thickness is limited to about 4 nm by direct tunneling of electrons from the silicon conduction band to the gate electrode for charge densities below 3.1×10 -6 C cm -2 and by F o w l e r - N o r d h e i m tunneling for greater charge densities. In the latter case the tunnel leakage current is too large, independent of the oxide thickness. Therefore, the density of the stored charge should not be greater than 3.1 ~tC cm -2 or the electric field in the oxide should not be greater than 9 MV cm-L

12 I0

i ~\ \ \ ~Mb \

~ 4Mb'~ne," ~,

\ (y') c/') clJ Z

8

\

\ Voo=3.3v\

'\ 5v' \

\

-= ,iz

4,,~b' "'x

..J
'=2 (.J

2

00

iFr.9 n.~.l 10 -6

,

2"10 ~

,/

3"10 -6

|

4"I0 "6

CIsr =£,F~ [C/cmZl Ae

Fig. 15 Critical capacitor oxide thickness vs. the stored charge density QsT/Ac The dashed lines in Fig. 15 illustrate the relation between the capacitor oxide thickness and the stored charge density. In order to induce a greater charge density at a given gate plate voltage V m the oxide thickness must be reduced. Assuming Vr = VDD, where VDD is the supply voltage, we have:

QsT/Ac = VDDei/ti A typical capacitor oxide thickness in 1 Mb memories is 10 nm and the point corresponding to it is situated in the field of a tolerable leakage. However, if we wanted to make a 4 Mb m e m o r y conventionally, i.e. to store the m i n i m u m possible charge o f 150 fC on a planar area o f about 5 pm 2 (as it follows from evaluation of the exist-

B. Majkusiak and A. Jakubowski

36

ing trend), the stored charge density would be close to the critical value (see Fig. 15). Therefore, DRAMs beyond 4 Mb cannot be manufactured with conventional technology, in which the electron charge is stored in the silicon surface region of the planar MOS capacitor. In order to solve the problem of further miniaturization, three-dimensional structures represented by stacked capacitor cells (STC) [57] and cells with trench capacitors [58,59] have been introduced. Trench technology enables us to keep the stored charge density in spite of the reduction of the planar area occupied by a capacitor owing to the additional dimension toward the interior of the substrate. The point corresponding to experimental 4 Mb DRAMs [60] with a trench capacitor of capacitance 40 fF and oxide thickness 10 nm is also shown in Fig. 15.

5. Conclusions

As shown in this paper, reduction of the oxide thickness in MOS VLSI circuits gives many advantages with regard to the performance of the MOS devices. Therefore, this trend will be continued until the minimum thickness resulting from the reliability requirements or some fundamental limitations is reached. Reliability properties of a very thin oxide layer can be improved by cleaner and more advanced technology, or by some design solutions decreasing hot carrier injection into the oxide. The tunneling of channel carriers through the very thin gate oxide layer may then become the most important obstacle for reducing oxide thickness. This is the case with the MOS DRAM cell, where any further decrease of the planar area occupied by the cell capacitor, whilst maintaining its capacitance, is accomplished not by a simultaneous reduction of the oxide thickness but mainly by increasing the trench depth in trench cells or by unfolding the capacitor plate geometry in stacked cells. However, the minimum gate oxide thickness in the MOS transistor of MOS VLSI circuits will result from the ability to manufacture very good quality ultrathin oxides in a controllable way rather than from the flow of too large a gate tunnel current. 6. References

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