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VHDL and synthesis tools provide a generic design entry platform into FPGAs, PLDs and ASICs
VHDL and synthesis tools provide a generic design entry platform into FPGAs, PLDs and ASICs Chris Jay
Field programmable gate arrays,programmable logic devices and application specific devices such as masked programmable gate arrays have now reached such a degree of complexity that it is impossible for a designer to effect a design in silicon without the support of computer aided design tools. Much of the software available is target device specific, in other words the designer must use tools that are specifically tailored toward the architecture and technology into which the design will finally be realized. The development of VHDL as a general design entry tool was sponsored by the US Department of Defence (DoD) to overcome the problem of a design becoming target dependent. In this way a design may be created in VHDL and the target technology chosen after the fact. The design may then be synthesized into a target technology by the application of synthesistools. However, if that technology became obsolescent or impossible to procure a new target technology may be chosen and the synthesistool re-applied to migrate the same design into the new device, thus forgoing the task of a complete logic redesign. This paper was written by Chris Jay as a consultant to Exemplar Logic, a California based supplier of synthesis tools to FPGA, PLD and ASlC manufacturers. The design example of a FIFO SRAM controller was completed and synthesized into a Xilinx FPGAdevice. Resultingsimulation in the target technology confirmed functionality of the specific application. Keywords: VH DL, synthesis tools, FPGA, PLD
The introduction of programmable logic in the 1970s generated a need for a design entry mechanism in the form of support software. In those early days, digital systems designers had access to a Boolean entry system BAT PCTechnology, Milpitas, CA, USA Paper received: July 1992
called PALASM®, offered by MMI in support of its PAL® devices. The PAL ASeMbler (PALASM) permitted the designer to enter a programmable logic design in the form of equations, ultimately assembled into JEDEC fuse plots. The plot could be used by a device programmer to remove internal fuses and create the desired logic function in the target device. Although this support software could be considered crude by today's standards it was adequate as a design entry vehicle for those early device architectures. PALASM was continually updated to keep pace with the new features found in the later PAL architectures and evolved along with programmable logic devices (PLDs), which it was designed to support. Other design entry packages like PALASM emerged during the 1980s; ABEL~Mand CUPL 'M were developed and supplied by third party vendors to support a wide range of general PLD architectures. All are available today and still used by many systems designers. The use of alternative forms of design entry was spurred on by the development of more complex, higher density PLDs, and by the introduction of field programmable gate arrays (FPGAs) in the mid 1980s. This made it essential for the designer to have access to complex design entry tools; if tools were not available then designs could not be created in new high density architectures. Schematic capture and device specific design editors became the preferred level of entry to suit larger complex devices. Altera® and Xilinx '~ are two companies that pioneered the use of schematic entry and design editors for their families of programmable logic and field programmable gate arrays. Toward the end of the 1980s many CAE support tools for programmable logic devices and FPGAs became available; most are specific to the target device because tools were developed by the FPGA/PLD vendors. The arrival of new FPGA vendors in the early 1990s, offering different architectures, technologies and new design entry tools, could cause future systems designers
0141-9331/93/070391-08 © 1993 Butterworth-Heinemann Ltd Microprocessors and Microsystems Volume 17 Number 7 September 1993
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VHDL and synthesis tools: C Jay many headaches. While endeavouring to fulfil a need with a better device, the FPGA vendor could interrupt any 'time to market' advantage with yet another learning curve of yet another FPGA CAE support tool. Different kinds of FPGAs will be better suited to some applications than to others, but should the designer be expected to become an expert in the use of every design tool available as one design cycle proceeds to the next? This problem could be resolved if every systems designer used a single design entry package supported by every FPGA, PLD and ASIC vendor. Unfortunately, as the latter day entrants to the FPGA and PLD arena scramble to get their new silicon offerings into the market, the broad coverage of CAE tool support could suffer.
VHDLDesignentry
TargetTechnology Libraries
FPGA netlists
UserConstraints
• ~, ,~ Schematics ASIC PLD Performance netlists netlists Reports
VHDL DESIGN ENTRY
Figure 1
Fortunately a solution exists in a design entry vehicle that is not target specific and is sufficiently generic for a wide range of devices: FPGAs, high density, PLDs and, for ultimate volume production, mask programmed gate array. The VHSIC (very high speed integrated circuit) hardware description language or (VHDL), is an abstract design entry that permits the designer to create a design as a series of verbose statements describing the functionality of the system. Once a VHDL file has been created, it can be synthesized into the target device. In fact, a design can be completed even before the target technology is chosen. The quality of synthesis tools then becomes a key factor in creating an efficient design. Applying VH DL entry and synthesis software the designer can switch effortlessly between target technologies, referred to as retargetting. The need to learn new tools, features of the support libraries and different device architectures can therefore be avoided. An example of retargetting might be found in a design that will not route in one FPGA technology but will route easily in a competitive device. The same VHDL entry can be resynthesized for the second FPGA product without having to redesign. Synthesis tools apply gate level translation and optimization algorithms most suited to the second target technology. The output becomes a netlist that can be routed into the new FPGA device. After the design has been released to market, and if production increases to sufficient volumes, the same VH DL entry can be synthesized into a gate array. Synthesis tools can also provide a netlist to schematic output, so a schematic record of a design can be kept along with the VHDL specification. The resulting benefit to the user is a dramatic reduction in time to market by saving on learning curve time, redesign time and design entry time.
generated for assessment in a design review. The target technology and architecture may then be chosen by analysis of results generated by the report output. Figure 1 also shows a constraints file input that can be created to support the route into the target technology. For example, input/output pads may be defined and critical path specification added. At this stage the constraints file will imply target technology dependency. Before running the synthesis program, support libraries for the target are selected. An example may be a VHDL file to be synthesized into a Xilinx FPGA 3000 series. The synthesis program may then be run with the support of the 3000 series logic libraries. An optimization strategy, which is target dependent, is automatically chosen by the synthesis tools. The choice is not without significance, because there is a wide diversity in logic architectures. This fact validates choosing the most appropriate optimization strategy to suit the specific target architecture. Figure 2 shows a variety FPGA, PLD and gate array devices from which one optimization strategy is selected. The limited fan in optimization algorithm suits Xilinx, while optimization based on multiplexer design suits the Actel technology. PLD designs use a cubelimited optimization technique, while gate structures of gate arrays benefit from an algebraic optimization.
SYNTHESIS TOOLS
Figure 1 shows the fundamental concept of synthesis tools. The designer creates a VHDL design specification of a system; at this point the design can end up in any technology. If the designer is not sure which is the best target architecture, or whether a design will fit in a specific part, then performance reports can be created from a number of different targets. Performance details may be
392
SynthesizingVHDL entry to the targettechnology
SIMULATION
To check functional integrity after the design phase, it is necessary to apply simulation cycles. Iterations of design XILINX" 2000 ~"~" 3000
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Figure2
Optimizationtechnologiesand libraries
Microprocessors and Microsystems Volume 17 Number 7 September 1993
VHDL and synthesis tools: C Jay and simulation can be used to track any bugs in logic networks. Figure 3 shows a flow chart from a VHDL entry through to the final completion of the design. A VHDL
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1
VHDL DESIGN EXAMPLE OF A FIFO RAM CONTROLLER
VHDL Simulation
no
yes Design Synthesis: Gate Translation & Optimization
ld
Auto Place and Route
simulator can be used to verify functionality prior to synthesis, place and route into the target architecture. At the synthesis stage the Exemplar Logic synthesis system tools can apply timing in the form of AC gate-delay parameters. These are based on known logic timing parameters of cells in the target architecture. Net delay information cannot be provided until the design is placed and routed in the target device. However, in the software a reporting feature exists that can be used to determine how much tolerance or slack is available for net delays. This is achieved by subtracting individual gate delays from the delay of an overall path.
F
First-in first-out (FIFO) memories are used as temporary buffers to store data. A typical application would be an interface between two systems that function at different speeds. Data sent from one system output can reside in a temporary buffer until the receiver is ready to accept the data. A FIFO could be used in interfacing a parallel bus to a serial interface, for example a parallel byte/word wide IBM PC port to a serial local area network (LAN), such as Ethernet. This interface might benefit from intermediate storage because data rates differ by a factor of eight/ sixteen and the faster peripheral could be tied up by the slower data rate of the serial LAN. Large FIFOs are usually RAM based. Smaller FIFOs of fewer than 256 bytes are generally configured around register files. These days, fast high-density FIFO buffers can be realized from large, highspeed static RAMs that are readily available from a number of vendors. A complete high-density FIFO may be constructed from a RAM controller device, an SRAM and a couple of low-cost bus driver chips included to provide bus isolation. The block diagram in Figure 4 shows a FIFO SRAM controller designed to control 64 kbyte/word wide SRAM array as a FIFO. A VHDL description of the controller will be generated and can be synthesized into the desired target technology. Inputs and outputs to and from the controller device should be defined first. The clock input
Timing Simulation
INPUT BUFFER
DATA IN
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OUTPUT BUFFER
INTERNAL DATA PATH
CLOCK
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DATA
REQRD RDRDY • WRREQ 4 WRRDY RST _!
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SRAMand FIFORAM controllerblock diagram
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VHDL and synthesis tools: C Jay 'CLK' is derived from a high frequency crystal-controlled oscillator and designed to synchronize all timing events in the SRAM FIFO controller device. Handshake signals responsible for controlling data input are the 'WRREQ' input and 'WRRDY' output, defined as 'write request' and 'write ready'. Data read operations use 'REQRD' and 'RDRDY' are 'request to read' and 'read ready' handshake controls. A general 'RST' input can be used at any time to reset the entire system, to clear all flags and internal counters and to initialize the controller to a restart state. To supply status information to transmitter and receiver systems, 'EMPTY', 'FULL' and ' H A L F F U L L ' flags exist. If the 'EMPTY' flag is active SRAM read operations are prevented because there is no valid data in the SRAM. An active 'FULL' signal indicates that all SRAM locations contain data that has not been read. This signal will prevent any further write operations. The 'HALF_FULL' output becomes set when half or more of the SRAM contains unread data. It can be used as an indicator of how fast the SRAM is being filled. The FIFO SRAM controller supplies data location information on a 16 bit address bus. Control is supplied through 'NOE' and 'NWR' outputs; NOT Output Enable and NOT WRite commands. These control outputs can also be used to enable data bus input and output buffers. These buffers perform an isolation function for input and output data. Figure 5 shows the internal structure of the FIFO RAM controller as a block diagram with four basic sections. A small state counter driven from the clock input is designed to provide synchronous control of events occurring in the control and interface section of the system. This section decodes interface handshake signals and provides read and write control inputs to the SRAM. Internal read and write address counters are enabled to increment after SRAM read and write operations; these are held off from incrementing when memory is not being accessed. An output register with a multiplexed input is designed to accept either a write address or a read address information. Finally, a status counter is employed to track
T H E O R Y OF C O N T R O L L E R O P E R A T I O N Reset and initialization Waveforms in Figure 6a show the state of the controller after an active reset 'RST'. A HIGH reset input is synchronized to the rising clock edge and causes the 'RDRDY', 'FULL' and 'HALF__FULL' status lines to go LOW. After a reset, the FIFO will be empty. The 'RDRDY' output must be inactive. The 'WRRDY' is driven active HIGH to indicate that the SRAM is ready to receive data. Also, the 'EMPTY' line is HIGH to indicate that the FIFO configuration contains no valid data. The 'NOE' (Not Output Enable) and 'NWR' (Not WRite) lines go to HIGH after a reset. For most commercially available SRAM devices, this is an inactive state. Finally, the address lines are all cleared to access location zero in the memory.
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RST
NOE
CLK
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the reading and writing of data. Decoded outputs from this counter supply 'FULL', 'EMPTY' and ' H A L F F U L L ' information. The transmitting device can monitor the 'FULL' flag to hold off on SRAM write cycle. This prevents writing over unread data residing in the SRAM. An 'EMPTY' flag indicates to the receiving device that there is no data currently available in the memory.
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394
Block diagram of FiFO RAM controller
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Figure6 a, Resettiming waveforms; b, waveforms showingwrrdy/ reqwr handshakeand memoryaddressing;e, waveformsshowingrdrdy/ reqrd handshakeand memory addressing
Microprocessors and Microsystems Volume 17 Number 7 September 1993
VHDL and synthesis tools: C Jay
Address and status counters The FIFO SRAM controller contains a read address counter and a write address counter which are both cleared by a reset input. These counters are designed to increment after each memory access cycle and remain in a hold condition when no data read/write operations are taking place. Counters can be regarded as pointers to the next sequential location in the SRAM. During a write cycle, the write counter is multiplexed onto the SRAM's address bus. A memory write cycle takes place as the SRAM's write control input is taken LOW. Internally, the write counter is incremented to point to the next write location and an UP/DOWN status counter is incremented. This procedure takes place on each write cycle. When data is taken from the FIFO configuration, the read counter is routed to the SRAM's address input then a read cycle takes place. The internal read counter is incremented to point to the next read location. The status counter is decremented after each read cycle. At any time, this counter will contain a value equivalent to the number of data bytes/words of information residing in the FIFO buffer. Boolean decoding of this counter's output can provide FIFO status information such as 'FULL' or 'EMPTY'; the former flag is essential to prevent overwriting valid data in a full FIFO buffer. The latter flag can prevent the reading of old data still residing in the SRAM.
Handshake and control: the write cycle
Figure 6b shows waveforms generated when data is written to the FIFO. The 'WRRDY' line goes HIGH to indicate that the system is ready to receive data. The transmitting device presents data to the input buffer, as shown in Figure 4. The request to write line 'REQWR' is taken HIGH. The 'WRRDY' line acknowledges by going LOW as the next write address becomes valid. One cycle later, the 'NWR' line is driven active LOW and remains LOW for one clock cycle, as data is written into the SRAM. After one complete write cycle, the 'WRRDY' line goes active to indicate that a new write cycle may take place.
Read cycle Read cycle waveforms shown in Figure 6c are similar to those shown for the write cycle. A logic HIGH read ready 'RDRDY' output indicates that the system is ready to accept a read cycle. In response to an active 'RDRDY', a request to read, 'REQRD' may be applied. One read cycle will result. The current read address counter will be registered to the output and the 'NOE' (Not Output Enable) will be driven LOW to enable the SRAM's data output buffers. This signal will stay LOW for two clock cycles. 'RDRDY' and 'NOE' will go HIGH on the completion of one read cycle. If a read and write operation is pending, then both read and write cycles are concatenated, providing an uninterrupted read and write cycle. In generating a VH DL design of the FIFO controller, the designer needs only a conceptual understanding of the design. The gate translation and gate optimization
process are part of the synthesis tools that create the final system design. The VHDL listing is given in Listing 1 with a comment section. It was synthesized to provide a netlist output from which read and write waveforms, given in Figures 6a, 6b and 6c were generated.
THE DESIGN ENCODED INTO V H D L
Listing 1 shows the complete description of the design. Between keywords PORT and END is a list of the design's inputs and outputs. These are defined as BITs and BIT__VECTORs. A B I T V E C T O R (0 to 15) here defines a 16 bit wide bus. These correspond to input and output lines and buses shown in Figure 4. Any internal SIGNALs used in the design architecture are listed under the keyword ARCH ITECTURE and correspond to internal nets used in the system. Two examples are 'rdflg' and 'wrtflg'. These internal signals will become set during read and write operations. The range of large integer values has been entered in exponent form, (0 TO 2"'16); the upper limit being two raised to the power of 16. VHDL supports exponentiation to avoid entering larger integer values. After the keyword BEGIN is a description of three counters: 'statein c', 'readinc' and 'writinc'. These describe the action of an internal state machine, read and write counters. When used inside the PROCESS, the 'state' counter will be synthesized into a small state machine. It is designed to increment through one complete read or write cycle, then return to zero before the next cycle commences. Starting at zero prior to a memory access, this counter will count through three states controlling memory access cycles. Counters 'readinc' and 'writinc' will be synthesized as read and write counters of 16 bits in length. Between keywords BEGIN PROCESSand END PROCESS is the description of the behaviour of the FIFO SRAM controller. All events in the PROCESSwill be synchronized to a 'clk' rising edge. WAIT UNTIL clk -- '1 '; - - synchronizing clock If the rst (RESET) input is HIGH, then internal counters and flags will be initialized to a known reset state. The 'IF < statement1 > T H E N ' . . . will be synthesized into logic that will test input conditions specified by the statement section. Alternative actions will be specified by 'ELSIF < statement... > THEN'. A number of these may be enclosed between ' I F . . . END IF' in the PROCESS. An example given is: ELSIF (reqwr = '0') AND (reqrd = '0') AND (state = 0) THEN wrrdy < = '1'; rdrdy < = '1 '; This will be synthesized into circuitry that asserts read and write ready handshake signals when both requests are inactive. Further, an internal 'state' condition must be zero. If 'state' is non zero, the FIFO controller is currently accessing the SRAM. An example of using an internal state machine to control awrite cycle is shown in Figure 7, along with a section of VHDL code. This same state machine is
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VHDL and synthesis tools: C Jay L i s t i n g i. -- A n e x a m p l e o f a V H D L F I F O SPJ%M c o n t r o l l e r designed to c o n t r o l 6 4 R o f SRJ%M a s a F i r s t I n F i r s t O u t b u f f e r . T h e -- d e s i g n c o n s i s t s o f h a n d s h a k e i n t e r f a c e logic, read and -- w r i t e c o u n t e r s , a state machine to control read and write -- o p e r a t i o n s and a status counter to provide FIFO status
rdrdy state addout noe
--
--
'0'; statinc; rdcount; '0';
------
s r a m is n o t e m p t y ~h(~n a s s e r t t h e internal read flag add set the read/write ready outputs inactive. Increment the state counter and output the read counter. Set the sram ouput enable act}re.
information.
E N T I T Y f i f o c n t l IS PORT (clk,reqrd,req~4r,rst:IN BIT; rdrdy,wrrdy,noe,nwr,empty,full,halffull:OUT addout:OUT BIT VECTOR(15 DOWNTO 0)]; END fifocntl; ARCHITECTURE E X E M P I J t R O F f i f o c n t l IS SIGNAL state : I N T E G E R R A N G E 0 T O 4; SIGNAL statinc : I N T E G E R R A N G E 0 T O 4; SIGNAL wrtflg :BIT; SIGNAL rdflg :BIT; SIGNAL rdwr :BIT; SIGNAL wrcount : B I T V E C T O R (15 D O W N T O SIGNAL writinc :BIT-VECTOR (15 D O W N T O SIGNAL rdcount : B I T - - V E C T O R (15 D O W N T O SIGNAL readinc : B I T - - V E C T O R (15 D O W N T O SIGNAL status : B I T - - V E C T O R (16 D O W N T O
ELSIF
ELSIF
statiNc readinc writinc
< = s t a t e + l; <= rdcount + X"0001"; <= w r c o u n t + X " 0 0 0 1 " ;
PROCESS BEGIN W A I T D-NTIL c l k -- A c t i v e
reset
IF
=
'i';
and
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-- s y n c h r o n i z i n g state.
ELSIE ( r e q w r = '0') wrrdy <= 'i'; rdrdy < = 'I';
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-- W i t h t h e i n t e r n a l s t a t e c o u n t e r a t -- s t a t e 2 c l e a r t h e w r i t e f l a g s e t -- r e a d a n d w r i t e r e a d y o u t p u t s a c t i v e -- a n d r e s e t t h e c y c l e s t a t e c o u n t e r t o -- z e r o .
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--
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rdwr rdrdy wrrdy nwr state
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the
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<=
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At state 4 one read/write cycle has been completed. Clear the read/write flag, set read/write ready and drive the sram write signal inactive, reset the sram access state counter.
IF;
To create status information, sram FULL, EMPTY and HALF FULL the status counter is tested. If the status counter contains zero the sram is empty. If the contents of the counter is 2,,15 the sram is half full. If the counter contains 2"*16-1 the sram is full. IF
(status empty ELSE empty END IF;
= 0) T H E N <= 'i'; rdrdy <= '0';
<=
'0';
(status(l) = 'I') AND (status(0) = '0') THEN half full <= 'I'; ELSE half full <= '0'; END IF;
----
Set the empty flag prevent any read operations.
and
----
Set the half full flag when the counter bit(l] becomes set.
-----
When the counter bit(0) becomes set the full flag is set and write operations are prevented.
IF
IF (status(0) = 'i') THEN full <= 'i'; wrrdy <= '0'; ELSE full <= '0'; wrrdy <= 'i'; END IF; END PROCESS; END;
THEN
if a r e q u e s t t o r e a d is p e n d i n g a n d t h e s y s t e m is p a s s i v e a n d t h e
FIFO SRAM controller
used for read cycles, but a read flag 'rdflg' instead of 'wrtflg' is used to distinguish between read and write cycles. State zero can be considered as a passive state in the controller where no SRAM access is taking place. If 'reqwr' is driven active, current contents of the address counter drives the address output register as STATE 0 transitions to STATE I, and the 'wrtflg' becomes set. At state I values of 'reqrd' and 'reqwr' are ignored until the write cycle is completed by returning to STATE 0 through
396
IF
active reset clear write flag clear read flag clear read and write flag set sram ouput enable inactive set sram write input inactive set state counter to zero clear status counter initalize read counter to zero initalize write counter to zero clear address output register set empty flag active high full and half full to inactive low
<=
'i')
increment
IF;
and
clock
or write
wrtflg rdrdy wrrdy state nwr
rdflg wrrdy
Listing I
---------------
(reqrd ---
wrtflq < = 'i'; w r r d y < = "0'; r d r d y < = '0'; state <= statinc; addout <= wrcount;
END
read
state cycle increment increment read pointer increment write pointer
AND
:
--
IF; cycle
IF
-- R e a d
No
( r s t = 'i') T H E N wrtflg < = '0'; rdflg < = '0'; rdwr < = '0'; hoe < = 'i'; nwr < = 'I'; state <= 0; status < = "0' & " 0 0 0 0 " ; rdcount <= X"0000"; wrcount <= X"0000"; addout <= X"0000"; empty <= 'i'; full < = '0'; h a l f f u l l <= '0';
END
----
(rdf]g
- - A t s t a t e 2 t h e r e a d c y c l e is -- c o m p l e t e d c l e a r t h e r e a d f l a g -- and set read/write ready outputs active. Reset the state counter -- a n d s e t t h e s r a m e n a b l e i n p u t -- i n a c t i v e . <= status - int2evec(1) ; -- D e c r e m e n t t h e s t a t u s c o u n t e r <= readinc; and increment the read counter.
rdcount
-- R e a d
i) A N D statinc;
( s t a t e = 2)
status
END
=
<=
rdflg rdrdy wrrdy state hoe
-- i n t e r n a l s t a t e c o u n t e r -- for read~write cycles -- internal write flag -- internal read flag -- r e a d a n d w r i t e f l a g -- w r i t e c o u n t e r -- w r i t e i n c r e m e n t -- r e a d c o u n t e r -- r e a d i n c r e m e n t -- f i f o s t a t u s
0) 0) 0) 0) O)
(state
state
BIT;
BEGIN
--
<= <= <= <=
STATES I and 2. In transitioning from STATE I to STATE 2, the 'nwr' output is driven LOW. The final phase of the write cycle is from STATE 2 to STATE 0. All flags and signals return to a passive state. System status and write counters are incremented. Read cycles are performed in a similar manner following a state diagram of three states like the one shown in Figure 7b. To distinguish between a read and write operation, internal flags 'rdflg' and 'wrtflg' are employed.
Microprocessors and Microsystems Volume 17 Number 7 September 1993
VHDL and synthesis tools: C Jay rdrdy =0
reqwr = 1 wrtflg = 0 nwr = 1
IF (status = 0) THEN empty <= ! 1,J, rdrdy <= t 0,I, ELSE empty <= '0'; END IF;
wrrdy = 0 reqrd = X reqwr = X wrttlg = 1
register addout rdrcly = 1 with the write wrrdy = 1 counter contents reqrd = 0 ~
~
nwr = 0 full = 0
IF (status <= 2"15) THEN half_full <=' 0,'" ELSE half_full <= '1'; END IF;
rdrdy = 1 wrrdy = 1 reqrd = 0
r--o wrt~ = 0
=status and write counters
nwr = 1 furl = 0
IF (status <= 2"16 -1) THEN full <= I 0,Jo ELSE full <= '1'; wrrdy <= 0, END IF;
wrtflg = 0 nwr = 1 full = 0
a
Listing2
Description
of decoding
FULL, EMPTY
and
HALFFULL
ELSIF (reqwr='l') A N D {reqrd='0') A N D (stste=0) A N D (full='0') T H E N wrfflg wrrdy
<= '1'; <= '0'; rdrdy <= '0';
state <= staUnc; addout <= wrcount; ELSIF (state = 1) A N D (wrtffg = '1') T H E N
state <= ststinc; nwr
<= '0';
ELSIF (state = 2) A N D (wrtflg = '1') T H E N wrtflg
<= '0';
rdrdy <= '1'; wrrdy <= '1'; state <= 0 ; nwr <='1';
status <= status + 1; wrcount <= writinc;
b Figure 7
a, One SRAMwrite cycle;b, descriptionof one SRAMwrite
cycle
FLAGS The status of the FIFO SRAM controller is kept in a 17 bit status counter. If the contents of this counter is zero then the SRAM contains no data and the 'EMPTY' flag is set. When successive write operations fill the SRAM status counter increments, and all SRAM locations contain valid data, then only the 16th bit becomes set. Bits (0-15) are all LOW. When this occurs, the FULL flag becomes set. When the FIFO is full 'wrrdy' is held LOW, preventing the external transmitter from writing to the FIFO configuration. When the contents of the status counter is greater or equal to 2"'15, then the HALF__FULL flag becomes set. Listing 2 highlights the description of the status decoding and how it is implemented in VHDL.
realized for the systems designer, and highlight the generic nature of VHDL and synthesis tools. In terms of the FIFO SRAM controller, VHDL entry allows the designer to think of counters, state machines and handshake logic at a conceptual level. Detailed development of the system at the gate and transistor level can be avoided, hence enhancing overall time to market and making the designer's time more efficient. Other advantages are apparent in terms of product development. Taking a 6 4 k FIFO design to a 128k or 256 k buffer size becomes an almost trivial task. BIT__VECTORS can be enlarged to account for deeper address counters, status counters and address output buffers. The design can then be resynthesized to accommodate larger buffer memories of 128 k or 256k. Additional features may be quickly added to the VHDL design to suit different handshake techniques, or different parameters to suit other SRAM devices. Performing these modifications at the gate or transistor level would virtually constitute a completely new layout and design. The VHDL design entry shown in Listing 1 was synthesized using Exemplar Logic tools into a Xilinx LCA netlist format. To establish logic functionality, a gate-delay simulator can be applied to the design. The Exemplar Logic Synthesis System provides gate-delay information and 'slack' data. The latter is a figure of tolerance that can be encroached on by net timing delays. For example, if a critical signal path is 40 ns and a gate delay is 8 ns, then a 32 ns margin is available for net or interconnect delay. This is called 'slack'. In a general design, iterations of VHDL entry and simulation can be applied until functional integrity is established. After synthesis, final autoplace and route can be applied into the target architecture. Once placed and routed, final simulation with gate and net timing delays can be applied. The process of conception of the SRAM FIFO controller through to a fully functional design becomes reduced to only a few days.
SUMMARY
H I S T O R Y OF V H D L
The design of the FIFO SRAM controller can be synthesized into a number of target architectures using the Exemplar Logic synthesis system. Many advantages are
VHDL emerged from the Very High Speed Integrated Circuit (VHSIC) programme sponsored by the Department of Defense (DoD) in the late 1970s. A problem
Microprocessors and Microsystems Volume 17 Number 7 September 1993
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VHDL and synthesis tools: C Jay associated with some military contracts was the time taken from conception through to the final commissioning. Integrated circuit technologies can change dramatically and quickly so military projects could not take full advantage of new technologies. Creating designs at a high level of abstraction could shorten this cycle, and translation into a new technology becomes a simpler and quicker task. In addition, a method of standardization was required so that design contractors and subcontractors could exchange designs in a standard format. To solve these problems, development of VHDL was started in 1983 under a DoD contract. Three years later VHDL was proposed as an IEEE standard. Following a number of revisions, it became ratified as IEEE Standard 1076 in late 1987. Since the signing of MILSTD 454L, it is a requirement that all DoD ASIC designs be completed in VHDL. Although spurred on by military contracts VHDL is quickly becominga general standard throughout industry. It now provides those same benefits as a design entry vehicle to commercial industry.
398
REFERENCES 1 2
Carlson,SIntroduction to HDL-BASED Design Using VHDL Synopsys (1990) Perry,D L VHDL McGraw-Hill, New York (1991) ................
Christopher Jay is a consultant specializing in the area of FPGA, PLD applications and software support tools. He is or has been a consultant to a number of companies such as AT&T Microelectronics, National .Semiconductor Corporation, Viewlogic, VLSI Technology Inc. and Exemplar Logic. This paper was written while Chris was a consultant to Exemplar Logic. After graduating from Essex University in _ 1977 with a BSc in electronic engineering he joined Texas Instruments in Bedford, UK as a digital design engineer. Exposure to the applications of programmable logic and FPGA devices was gained at Monolithic Memories, later merging with Advanced Micro Devices (AMD), where he became applications manager for the logic cell array (LCA) in the late 1980s. He is currently a partner in a design and manufacturing group, BAT PC Technology, based in Milpitas, California.
Microprocessors and Microsystems Volume 17 Number 7 September 1993
Field programmable gate arrays,programmable logic devices and application specific devices such as masked programmable gate arrays have now reached such a degree of complexity that it is impossible for a designer to effect a design in silicon without the support of computer aided design tools. Much of the software available is target device specific, in other words the designer must use tools that are specifically tailored toward the architecture and technology into which the design will finally be realized. The development of VHDL as a general design entry tool was sponsored by the US Department of Defence (DoD) to overcome the problem of a design becoming target dependent. In this way a design may be created in VHDL and the target technology chosen after the fact. The design may then be synthesized into a target technology by the application of synthesistools. However, if that technology became obsolescent or impossible to procure a new target technology may be chosen and the synthesistool re-applied to migrate the same design into the new device, thus forgoing the task of a complete logic redesign. This paper was written by Chris Jay as a consultant to Exemplar Logic, a California based supplier of synthesis tools to FPGA, PLD and ASlC manufacturers. The design example of a FIFO SRAM controller was completed and synthesized into a Xilinx FPGAdevice. Resultingsimulation in the target technology confirmed functionality of the specific application. Keywords: VH DL, synthesis tools, FPGA, PLD
The introduction of programmable logic in the 1970s generated a need for a design entry mechanism in the form of support software. In those early days, digital systems designers had access to a Boolean entry system BAT PCTechnology, Milpitas, CA, USA Paper received: July 1992
called PALASM®, offered by MMI in support of its PAL® devices. The PAL ASeMbler (PALASM) permitted the designer to enter a programmable logic design in the form of equations, ultimately assembled into JEDEC fuse plots. The plot could be used by a device programmer to remove internal fuses and create the desired logic function in the target device. Although this support software could be considered crude by today's standards it was adequate as a design entry vehicle for those early device architectures. PALASM was continually updated to keep pace with the new features found in the later PAL architectures and evolved along with programmable logic devices (PLDs), which it was designed to support. Other design entry packages like PALASM emerged during the 1980s; ABEL~Mand CUPL 'M were developed and supplied by third party vendors to support a wide range of general PLD architectures. All are available today and still used by many systems designers. The use of alternative forms of design entry was spurred on by the development of more complex, higher density PLDs, and by the introduction of field programmable gate arrays (FPGAs) in the mid 1980s. This made it essential for the designer to have access to complex design entry tools; if tools were not available then designs could not be created in new high density architectures. Schematic capture and device specific design editors became the preferred level of entry to suit larger complex devices. Altera® and Xilinx '~ are two companies that pioneered the use of schematic entry and design editors for their families of programmable logic and field programmable gate arrays. Toward the end of the 1980s many CAE support tools for programmable logic devices and FPGAs became available; most are specific to the target device because tools were developed by the FPGA/PLD vendors. The arrival of new FPGA vendors in the early 1990s, offering different architectures, technologies and new design entry tools, could cause future systems designers
0141-9331/93/070391-08 © 1993 Butterworth-Heinemann Ltd Microprocessors and Microsystems Volume 17 Number 7 September 1993
391
VHDL and synthesis tools: C Jay many headaches. While endeavouring to fulfil a need with a better device, the FPGA vendor could interrupt any 'time to market' advantage with yet another learning curve of yet another FPGA CAE support tool. Different kinds of FPGAs will be better suited to some applications than to others, but should the designer be expected to become an expert in the use of every design tool available as one design cycle proceeds to the next? This problem could be resolved if every systems designer used a single design entry package supported by every FPGA, PLD and ASIC vendor. Unfortunately, as the latter day entrants to the FPGA and PLD arena scramble to get their new silicon offerings into the market, the broad coverage of CAE tool support could suffer.
VHDLDesignentry
TargetTechnology Libraries
FPGA netlists
UserConstraints
• ~, ,~ Schematics ASIC PLD Performance netlists netlists Reports
VHDL DESIGN ENTRY
Figure 1
Fortunately a solution exists in a design entry vehicle that is not target specific and is sufficiently generic for a wide range of devices: FPGAs, high density, PLDs and, for ultimate volume production, mask programmed gate array. The VHSIC (very high speed integrated circuit) hardware description language or (VHDL), is an abstract design entry that permits the designer to create a design as a series of verbose statements describing the functionality of the system. Once a VHDL file has been created, it can be synthesized into the target device. In fact, a design can be completed even before the target technology is chosen. The quality of synthesis tools then becomes a key factor in creating an efficient design. Applying VH DL entry and synthesis software the designer can switch effortlessly between target technologies, referred to as retargetting. The need to learn new tools, features of the support libraries and different device architectures can therefore be avoided. An example of retargetting might be found in a design that will not route in one FPGA technology but will route easily in a competitive device. The same VHDL entry can be resynthesized for the second FPGA product without having to redesign. Synthesis tools apply gate level translation and optimization algorithms most suited to the second target technology. The output becomes a netlist that can be routed into the new FPGA device. After the design has been released to market, and if production increases to sufficient volumes, the same VH DL entry can be synthesized into a gate array. Synthesis tools can also provide a netlist to schematic output, so a schematic record of a design can be kept along with the VHDL specification. The resulting benefit to the user is a dramatic reduction in time to market by saving on learning curve time, redesign time and design entry time.
generated for assessment in a design review. The target technology and architecture may then be chosen by analysis of results generated by the report output. Figure 1 also shows a constraints file input that can be created to support the route into the target technology. For example, input/output pads may be defined and critical path specification added. At this stage the constraints file will imply target technology dependency. Before running the synthesis program, support libraries for the target are selected. An example may be a VHDL file to be synthesized into a Xilinx FPGA 3000 series. The synthesis program may then be run with the support of the 3000 series logic libraries. An optimization strategy, which is target dependent, is automatically chosen by the synthesis tools. The choice is not without significance, because there is a wide diversity in logic architectures. This fact validates choosing the most appropriate optimization strategy to suit the specific target architecture. Figure 2 shows a variety FPGA, PLD and gate array devices from which one optimization strategy is selected. The limited fan in optimization algorithm suits Xilinx, while optimization based on multiplexer design suits the Actel technology. PLD designs use a cubelimited optimization technique, while gate structures of gate arrays benefit from an algebraic optimization.
SYNTHESIS TOOLS
Figure 1 shows the fundamental concept of synthesis tools. The designer creates a VHDL design specification of a system; at this point the design can end up in any technology. If the designer is not sure which is the best target architecture, or whether a design will fit in a specific part, then performance reports can be created from a number of different targets. Performance details may be
392
SynthesizingVHDL entry to the targettechnology
SIMULATION
To check functional integrity after the design phase, it is necessary to apply simulation cycles. Iterations of design XILINX" 2000 ~"~" 3000
VHDk: --
~[
MULTIPLEXER BASED
CUBEALGEBRAcIUMT ,ED
I--- .-AcYgL [ ACT1/2i
-|
!-1~
--~: ALTERA LSI Logic NEC VLSI Toshiba Others
Figure2
Optimizationtechnologiesand libraries
Microprocessors and Microsystems Volume 17 Number 7 September 1993
VHDL and synthesis tools: C Jay and simulation can be used to track any bugs in logic networks. Figure 3 shows a flow chart from a VHDL entry through to the final completion of the design. A VHDL
v.o, oos,0o
II,
1
VHDL DESIGN EXAMPLE OF A FIFO RAM CONTROLLER
VHDL Simulation
no
yes Design Synthesis: Gate Translation & Optimization
ld
Auto Place and Route
simulator can be used to verify functionality prior to synthesis, place and route into the target architecture. At the synthesis stage the Exemplar Logic synthesis system tools can apply timing in the form of AC gate-delay parameters. These are based on known logic timing parameters of cells in the target architecture. Net delay information cannot be provided until the design is placed and routed in the target device. However, in the software a reporting feature exists that can be used to determine how much tolerance or slack is available for net delays. This is achieved by subtracting individual gate delays from the delay of an overall path.
F
First-in first-out (FIFO) memories are used as temporary buffers to store data. A typical application would be an interface between two systems that function at different speeds. Data sent from one system output can reside in a temporary buffer until the receiver is ready to accept the data. A FIFO could be used in interfacing a parallel bus to a serial interface, for example a parallel byte/word wide IBM PC port to a serial local area network (LAN), such as Ethernet. This interface might benefit from intermediate storage because data rates differ by a factor of eight/ sixteen and the faster peripheral could be tied up by the slower data rate of the serial LAN. Large FIFOs are usually RAM based. Smaller FIFOs of fewer than 256 bytes are generally configured around register files. These days, fast high-density FIFO buffers can be realized from large, highspeed static RAMs that are readily available from a number of vendors. A complete high-density FIFO may be constructed from a RAM controller device, an SRAM and a couple of low-cost bus driver chips included to provide bus isolation. The block diagram in Figure 4 shows a FIFO SRAM controller designed to control 64 kbyte/word wide SRAM array as a FIFO. A VHDL description of the controller will be generated and can be synthesized into the desired target technology. Inputs and outputs to and from the controller device should be defined first. The clock input
Timing Simulation
INPUT BUFFER
DATA IN
no
OUTPUT BUFFER
INTERNAL DATA PATH
CLOCK
1
L__
:
DATA OUT
.
!
DATA
REQRD RDRDY • WRREQ 4 WRRDY RST _!
CONTROL
I CONTROLLER FIFORAM
SRAM 64KX8
ADDRESS
HALFFU
/
•q EMPTY l
Design Completed Figure 3
VHDLdesignand simulation
• FULL Figure 4
m V
SRAMand FIFORAM controllerblock diagram
Microprocessors and Microsystems Volume 17 Number 7 September 1993
393
VHDL and synthesis tools: C Jay 'CLK' is derived from a high frequency crystal-controlled oscillator and designed to synchronize all timing events in the SRAM FIFO controller device. Handshake signals responsible for controlling data input are the 'WRREQ' input and 'WRRDY' output, defined as 'write request' and 'write ready'. Data read operations use 'REQRD' and 'RDRDY' are 'request to read' and 'read ready' handshake controls. A general 'RST' input can be used at any time to reset the entire system, to clear all flags and internal counters and to initialize the controller to a restart state. To supply status information to transmitter and receiver systems, 'EMPTY', 'FULL' and ' H A L F F U L L ' flags exist. If the 'EMPTY' flag is active SRAM read operations are prevented because there is no valid data in the SRAM. An active 'FULL' signal indicates that all SRAM locations contain data that has not been read. This signal will prevent any further write operations. The 'HALF_FULL' output becomes set when half or more of the SRAM contains unread data. It can be used as an indicator of how fast the SRAM is being filled. The FIFO SRAM controller supplies data location information on a 16 bit address bus. Control is supplied through 'NOE' and 'NWR' outputs; NOT Output Enable and NOT WRite commands. These control outputs can also be used to enable data bus input and output buffers. These buffers perform an isolation function for input and output data. Figure 5 shows the internal structure of the FIFO RAM controller as a block diagram with four basic sections. A small state counter driven from the clock input is designed to provide synchronous control of events occurring in the control and interface section of the system. This section decodes interface handshake signals and provides read and write control inputs to the SRAM. Internal read and write address counters are enabled to increment after SRAM read and write operations; these are held off from incrementing when memory is not being accessed. An output register with a multiplexed input is designed to accept either a write address or a read address information. Finally, a status counter is employed to track
T H E O R Y OF C O N T R O L L E R O P E R A T I O N Reset and initialization Waveforms in Figure 6a show the state of the controller after an active reset 'RST'. A HIGH reset input is synchronized to the rising clock edge and causes the 'RDRDY', 'FULL' and 'HALF__FULL' status lines to go LOW. After a reset, the FIFO will be empty. The 'RDRDY' output must be inactive. The 'WRRDY' is driven active HIGH to indicate that the SRAM is ready to receive data. Also, the 'EMPTY' line is HIGH to indicate that the FIFO configuration contains no valid data. The 'NOE' (Not Output Enable) and 'NWR' (Not WRite) lines go to HIGH after a reset. For most commercially available SRAM devices, this is an inactive state. Finally, the address lines are all cleared to access location zero in the memory.
CLK
-- -I
~ 1
COUNTERSTATE ~ .
ENABLE
ADDRESS 0 - 15
a CLK WRRDY REQWR
__
ADDRESS 0 - 15
WRRDY4 RST
C°N2;°'
h
. NWR--4"
RDRDYq - "
~,_J
WRRDY, NOE, NWR, EMPTY
READ/WRT 'E I ~ i ........ ~.................... J !
_
RDRDY, FULL, HALF_FULL
....
REQRD
__J
RST
NOE
CLK
WRRDY
the reading and writing of data. Decoded outputs from this counter supply 'FULL', 'EMPTY' and ' H A L F F U L L ' information. The transmitting device can monitor the 'FULL' flag to hold off on SRAM write cycle. This prevents writing over unread data residing in the SRAM. An 'EMPTY' flag indicates to the receiving device that there is no data currently available in the memory.
m - 1
~'
" ..................
X'
n
sX
m + 1
!\
NWR
INTERFACE
rn
b CLK RDRDY REQRD ADDRESS 0 - 15
n-1
i
n+ 1
NOE FUll
EMPTY
Figure5
394
Block diagram of FiFO RAM controller
C
Figure6 a, Resettiming waveforms; b, waveforms showingwrrdy/ reqwr handshakeand memoryaddressing;e, waveformsshowingrdrdy/ reqrd handshakeand memory addressing
Microprocessors and Microsystems Volume 17 Number 7 September 1993
VHDL and synthesis tools: C Jay
Address and status counters The FIFO SRAM controller contains a read address counter and a write address counter which are both cleared by a reset input. These counters are designed to increment after each memory access cycle and remain in a hold condition when no data read/write operations are taking place. Counters can be regarded as pointers to the next sequential location in the SRAM. During a write cycle, the write counter is multiplexed onto the SRAM's address bus. A memory write cycle takes place as the SRAM's write control input is taken LOW. Internally, the write counter is incremented to point to the next write location and an UP/DOWN status counter is incremented. This procedure takes place on each write cycle. When data is taken from the FIFO configuration, the read counter is routed to the SRAM's address input then a read cycle takes place. The internal read counter is incremented to point to the next read location. The status counter is decremented after each read cycle. At any time, this counter will contain a value equivalent to the number of data bytes/words of information residing in the FIFO buffer. Boolean decoding of this counter's output can provide FIFO status information such as 'FULL' or 'EMPTY'; the former flag is essential to prevent overwriting valid data in a full FIFO buffer. The latter flag can prevent the reading of old data still residing in the SRAM.
Handshake and control: the write cycle
Figure 6b shows waveforms generated when data is written to the FIFO. The 'WRRDY' line goes HIGH to indicate that the system is ready to receive data. The transmitting device presents data to the input buffer, as shown in Figure 4. The request to write line 'REQWR' is taken HIGH. The 'WRRDY' line acknowledges by going LOW as the next write address becomes valid. One cycle later, the 'NWR' line is driven active LOW and remains LOW for one clock cycle, as data is written into the SRAM. After one complete write cycle, the 'WRRDY' line goes active to indicate that a new write cycle may take place.
Read cycle Read cycle waveforms shown in Figure 6c are similar to those shown for the write cycle. A logic HIGH read ready 'RDRDY' output indicates that the system is ready to accept a read cycle. In response to an active 'RDRDY', a request to read, 'REQRD' may be applied. One read cycle will result. The current read address counter will be registered to the output and the 'NOE' (Not Output Enable) will be driven LOW to enable the SRAM's data output buffers. This signal will stay LOW for two clock cycles. 'RDRDY' and 'NOE' will go HIGH on the completion of one read cycle. If a read and write operation is pending, then both read and write cycles are concatenated, providing an uninterrupted read and write cycle. In generating a VH DL design of the FIFO controller, the designer needs only a conceptual understanding of the design. The gate translation and gate optimization
process are part of the synthesis tools that create the final system design. The VHDL listing is given in Listing 1 with a comment section. It was synthesized to provide a netlist output from which read and write waveforms, given in Figures 6a, 6b and 6c were generated.
THE DESIGN ENCODED INTO V H D L
Listing 1 shows the complete description of the design. Between keywords PORT and END is a list of the design's inputs and outputs. These are defined as BITs and BIT__VECTORs. A B I T V E C T O R (0 to 15) here defines a 16 bit wide bus. These correspond to input and output lines and buses shown in Figure 4. Any internal SIGNALs used in the design architecture are listed under the keyword ARCH ITECTURE and correspond to internal nets used in the system. Two examples are 'rdflg' and 'wrtflg'. These internal signals will become set during read and write operations. The range of large integer values has been entered in exponent form, (0 TO 2"'16); the upper limit being two raised to the power of 16. VHDL supports exponentiation to avoid entering larger integer values. After the keyword BEGIN is a description of three counters: 'statein c', 'readinc' and 'writinc'. These describe the action of an internal state machine, read and write counters. When used inside the PROCESS, the 'state' counter will be synthesized into a small state machine. It is designed to increment through one complete read or write cycle, then return to zero before the next cycle commences. Starting at zero prior to a memory access, this counter will count through three states controlling memory access cycles. Counters 'readinc' and 'writinc' will be synthesized as read and write counters of 16 bits in length. Between keywords BEGIN PROCESSand END PROCESS is the description of the behaviour of the FIFO SRAM controller. All events in the PROCESSwill be synchronized to a 'clk' rising edge. WAIT UNTIL clk -- '1 '; - - synchronizing clock If the rst (RESET) input is HIGH, then internal counters and flags will be initialized to a known reset state. The 'IF < statement1 > T H E N ' . . . will be synthesized into logic that will test input conditions specified by the statement section. Alternative actions will be specified by 'ELSIF < statement... > THEN'. A number of these may be enclosed between ' I F . . . END IF' in the PROCESS. An example given is: ELSIF (reqwr = '0') AND (reqrd = '0') AND (state = 0) THEN wrrdy < = '1'; rdrdy < = '1 '; This will be synthesized into circuitry that asserts read and write ready handshake signals when both requests are inactive. Further, an internal 'state' condition must be zero. If 'state' is non zero, the FIFO controller is currently accessing the SRAM. An example of using an internal state machine to control awrite cycle is shown in Figure 7, along with a section of VHDL code. This same state machine is
Microprocessors and Microsystems Volume 17 Number 7 September 1993
395
VHDL and synthesis tools: C Jay L i s t i n g i. -- A n e x a m p l e o f a V H D L F I F O SPJ%M c o n t r o l l e r designed to c o n t r o l 6 4 R o f SRJ%M a s a F i r s t I n F i r s t O u t b u f f e r . T h e -- d e s i g n c o n s i s t s o f h a n d s h a k e i n t e r f a c e logic, read and -- w r i t e c o u n t e r s , a state machine to control read and write -- o p e r a t i o n s and a status counter to provide FIFO status
rdrdy state addout noe
--
--
'0'; statinc; rdcount; '0';
------
s r a m is n o t e m p t y ~h(~n a s s e r t t h e internal read flag add set the read/write ready outputs inactive. Increment the state counter and output the read counter. Set the sram ouput enable act}re.
information.
E N T I T Y f i f o c n t l IS PORT (clk,reqrd,req~4r,rst:IN BIT; rdrdy,wrrdy,noe,nwr,empty,full,halffull:OUT addout:OUT BIT VECTOR(15 DOWNTO 0)]; END fifocntl; ARCHITECTURE E X E M P I J t R O F f i f o c n t l IS SIGNAL state : I N T E G E R R A N G E 0 T O 4; SIGNAL statinc : I N T E G E R R A N G E 0 T O 4; SIGNAL wrtflg :BIT; SIGNAL rdflg :BIT; SIGNAL rdwr :BIT; SIGNAL wrcount : B I T V E C T O R (15 D O W N T O SIGNAL writinc :BIT-VECTOR (15 D O W N T O SIGNAL rdcount : B I T - - V E C T O R (15 D O W N T O SIGNAL readinc : B I T - - V E C T O R (15 D O W N T O SIGNAL status : B I T - - V E C T O R (16 D O W N T O
ELSIF
ELSIF
statiNc readinc writinc
< = s t a t e + l; <= rdcount + X"0001"; <= w r c o u n t + X " 0 0 0 1 " ;
PROCESS BEGIN W A I T D-NTIL c l k -- A c t i v e
reset
IF
=
'i';
and
idle
-- s y n c h r o n i z i n g state.
ELSIE ( r e q w r = '0') wrrdy <= 'i'; rdrdy < = 'I';
Write
AND
in
(reqwr AND
ELSIF
response
= 'I') (state
(state
state nwr
ELSIF
IF
=
<= <=
(state
=
if n o ready
'0')
AND
(state
= 0)
read or write activity handshake to active
'0';
<=
"i';
<= <= <=
'i'; 0 ; 'I';
Write
(reqwr
ELSIF
to
I) A N D statinc; '0';
=
an
active
write
A N D ( r e q r d ~ '0') = 0) A N D ( f u l l = '0')
ELSIF
(state
set
in r e s p o n s e
AND
(reqrd
i) A N D
2) A N D
-----
=
'I')
THEN
A t s t a t e o n e in t h e w r i t e c y c l e s e t the not write output active and transition from state one to state two in the write cycle.
(wrtflg
=
'I')
THEN
<= <= <= <= <=
status wrcount
<= status + ict2evec(1) ; -- Increment the internal <= writinc; -- status counter -- and write counter to mark the -- end of one write cycle.
IF;
cycle
'0'; 'l'; 'I'; 0; 'I';
(wrtflg
in response
-- W i t h t h e i n t e r n a l s t a t e c o u n t e r a t -- s t a t e 2 c l e a r t h e w r i t e f l a g s e t -- r e a d a n d w r i t e r e a d y o u t p u t s a c t i v e -- a n d r e s e t t h e c y c l e s t a t e c o u n t e r t o -- z e r o .
to
an
active
read
( r e q w r = '0') A N D ( r e q r d = 'i') A N D ( s t a t e = 0) A N D ( e m p t y = '0') <= <=
'i'; '0';
Exampleof a VHDL
---
ELSIE
(state
request.
END ------
state
counter.
AND
(rdwr -----
<=
3) A N D
'0'; statinc;
(rdwr
<= <= <= <= <=
=
4)
AND
'I')
and write
requests.
( s t a t e = 0)
THEN
THEN
increment =
'i')
the
status
cycle
counter.
THEN
set the sram output enable inactive. increment the status cycle counter. output the current write address. Increment the write address. =
'I')
----(rdwr
'0'; 'I'; 'i'; 'i'; 0;
AND
If b o t h r e a d a n d w r i t e o p e r a t i o n s are pending drive read/w-rite ready signals inactive and set the interna~ read/write flag. Drive the sram o u t p u t e n a b l e low. I n c r e m e n t t h e state counter, ouput the current read count and increment the read counter.
--
<= <=
(state
rdwr rdrdy wrrdy nwr state
THEN
-- if a r e q u e s t t o w r i t e i s p e n d i n g , -- t h e s y s t e m is p a s s i v e a n d t h e s r a m -- is n o t f u l l t h e n a s s e r t t h e i n t e r n a l -- w r i t e f l a g s e t t h e r e a d / w r i t e outputs -- i n a c t i v e . O u t p u t t h e w r i t e c o u n t e r a n d -- increment the state counter from zero -- to one.
the
THEN
read
'i')
(rdwr =
statinc; = 2)
to
=
---------
< = 'i'; <= statinc; <= wrcount; <= writinc;
nwr state
request.
THEN
( r d f l g == 'i')
< = '0'; < = '0'; < = 'i'; < = '0'; <= statinc; <= rdcount; <= readinc;
<=
noe state addout wrcount
THEN
'l')
(state =
state ELSIF
cycles
=
rdrdy wrrdy rdwr hoe state addout rdcount
activity.
-------
THEN
With the status cycle counter at three set the sram write input low and transition to the next state. =
'i')
THEN
At state 4 one read/write cycle has been completed. Clear the read/write flag, set read/write ready and drive the sram write signal inactive, reset the sram access state counter.
IF;
To create status information, sram FULL, EMPTY and HALF FULL the status counter is tested. If the status counter contains zero the sram is empty. If the contents of the counter is 2,,15 the sram is half full. If the counter contains 2"*16-1 the sram is full. IF
(status empty ELSE empty END IF;
= 0) T H E N <= 'i'; rdrdy <= '0';
<=
'0';
(status(l) = 'I') AND (status(0) = '0') THEN half full <= 'I'; ELSE half full <= '0'; END IF;
----
Set the empty flag prevent any read operations.
and
----
Set the half full flag when the counter bit(l] becomes set.
-----
When the counter bit(0) becomes set the full flag is set and write operations are prevented.
IF
IF (status(0) = 'i') THEN full <= 'i'; wrrdy <= '0'; ELSE full <= '0'; wrrdy <= 'i'; END IF; END PROCESS; END;
THEN
if a r e q u e s t t o r e a d is p e n d i n g a n d t h e s y s t e m is p a s s i v e a n d t h e
FIFO SRAM controller
used for read cycles, but a read flag 'rdflg' instead of 'wrtflg' is used to distinguish between read and write cycles. State zero can be considered as a passive state in the controller where no SRAM access is taking place. If 'reqwr' is driven active, current contents of the address counter drives the address output register as STATE 0 transitions to STATE I, and the 'wrtflg' becomes set. At state I values of 'reqrd' and 'reqwr' are ignored until the write cycle is completed by returning to STATE 0 through
396
IF
active reset clear write flag clear read flag clear read and write flag set sram ouput enable inactive set sram write input inactive set state counter to zero clear status counter initalize read counter to zero initalize write counter to zero clear address output register set empty flag active high full and half full to inactive low
<=
'i')
increment
IF;
and
clock
or write
wrtflg rdrdy wrrdy state nwr
rdflg wrrdy
Listing I
---------------
(reqrd ---
wrtflq < = 'i'; w r r d y < = "0'; r d r d y < = '0'; state <= statinc; addout <= wrcount;
END
read
state cycle increment increment read pointer increment write pointer
AND
:
--
IF; cycle
IF
-- R e a d
No
( r s t = 'i') T H E N wrtflg < = '0'; rdflg < = '0'; rdwr < = '0'; hoe < = 'i'; nwr < = 'I'; state <= 0; status < = "0' & " 0 0 0 0 " ; rdcount <= X"0000"; wrcount <= X"0000"; addout <= X"0000"; empty <= 'i'; full < = '0'; h a l f f u l l <= '0';
END
----
(rdf]g
- - A t s t a t e 2 t h e r e a d c y c l e is -- c o m p l e t e d c l e a r t h e r e a d f l a g -- and set read/write ready outputs active. Reset the state counter -- a n d s e t t h e s r a m e n a b l e i n p u t -- i n a c t i v e . <= status - int2evec(1) ; -- D e c r e m e n t t h e s t a t u s c o u n t e r <= readinc; and increment the read counter.
rdcount
-- R e a d
i) A N D statinc;
( s t a t e = 2)
status
END
=
<=
rdflg rdrdy wrrdy state hoe
-- i n t e r n a l s t a t e c o u n t e r -- for read~write cycles -- internal write flag -- internal read flag -- r e a d a n d w r i t e f l a g -- w r i t e c o u n t e r -- w r i t e i n c r e m e n t -- r e a d c o u n t e r -- r e a d i n c r e m e n t -- f i f o s t a t u s
0) 0) 0) 0) O)
(state
state
BIT;
BEGIN
--
<= <= <= <=
STATES I and 2. In transitioning from STATE I to STATE 2, the 'nwr' output is driven LOW. The final phase of the write cycle is from STATE 2 to STATE 0. All flags and signals return to a passive state. System status and write counters are incremented. Read cycles are performed in a similar manner following a state diagram of three states like the one shown in Figure 7b. To distinguish between a read and write operation, internal flags 'rdflg' and 'wrtflg' are employed.
Microprocessors and Microsystems Volume 17 Number 7 September 1993
VHDL and synthesis tools: C Jay rdrdy =0
reqwr = 1 wrtflg = 0 nwr = 1
IF (status = 0) THEN empty <= ! 1,J, rdrdy <= t 0,I, ELSE empty <= '0'; END IF;
wrrdy = 0 reqrd = X reqwr = X wrttlg = 1
register addout rdrcly = 1 with the write wrrdy = 1 counter contents reqrd = 0 ~
~
nwr = 0 full = 0
IF (status <= 2"15) THEN half_full <=' 0,'" ELSE half_full <= '1'; END IF;
rdrdy = 1 wrrdy = 1 reqrd = 0
r--o wrt~ = 0
=status and write counters
nwr = 1 furl = 0
IF (status <= 2"16 -1) THEN full <= I 0,Jo ELSE full <= '1'; wrrdy <= 0, END IF;
wrtflg = 0 nwr = 1 full = 0
a
Listing2
Description
of decoding
FULL, EMPTY
and
HALFFULL
ELSIF (reqwr='l') A N D {reqrd='0') A N D (stste=0) A N D (full='0') T H E N wrfflg wrrdy
<= '1'; <= '0'; rdrdy <= '0';
state <= staUnc; addout <= wrcount; ELSIF (state = 1) A N D (wrtffg = '1') T H E N
state <= ststinc; nwr
<= '0';
ELSIF (state = 2) A N D (wrtflg = '1') T H E N wrtflg
<= '0';
rdrdy <= '1'; wrrdy <= '1'; state <= 0 ; nwr <='1';
status <= status + 1; wrcount <= writinc;
b Figure 7
a, One SRAMwrite cycle;b, descriptionof one SRAMwrite
cycle
FLAGS The status of the FIFO SRAM controller is kept in a 17 bit status counter. If the contents of this counter is zero then the SRAM contains no data and the 'EMPTY' flag is set. When successive write operations fill the SRAM status counter increments, and all SRAM locations contain valid data, then only the 16th bit becomes set. Bits (0-15) are all LOW. When this occurs, the FULL flag becomes set. When the FIFO is full 'wrrdy' is held LOW, preventing the external transmitter from writing to the FIFO configuration. When the contents of the status counter is greater or equal to 2"'15, then the HALF__FULL flag becomes set. Listing 2 highlights the description of the status decoding and how it is implemented in VHDL.
realized for the systems designer, and highlight the generic nature of VHDL and synthesis tools. In terms of the FIFO SRAM controller, VHDL entry allows the designer to think of counters, state machines and handshake logic at a conceptual level. Detailed development of the system at the gate and transistor level can be avoided, hence enhancing overall time to market and making the designer's time more efficient. Other advantages are apparent in terms of product development. Taking a 6 4 k FIFO design to a 128k or 256 k buffer size becomes an almost trivial task. BIT__VECTORS can be enlarged to account for deeper address counters, status counters and address output buffers. The design can then be resynthesized to accommodate larger buffer memories of 128 k or 256k. Additional features may be quickly added to the VHDL design to suit different handshake techniques, or different parameters to suit other SRAM devices. Performing these modifications at the gate or transistor level would virtually constitute a completely new layout and design. The VHDL design entry shown in Listing 1 was synthesized using Exemplar Logic tools into a Xilinx LCA netlist format. To establish logic functionality, a gate-delay simulator can be applied to the design. The Exemplar Logic Synthesis System provides gate-delay information and 'slack' data. The latter is a figure of tolerance that can be encroached on by net timing delays. For example, if a critical signal path is 40 ns and a gate delay is 8 ns, then a 32 ns margin is available for net or interconnect delay. This is called 'slack'. In a general design, iterations of VHDL entry and simulation can be applied until functional integrity is established. After synthesis, final autoplace and route can be applied into the target architecture. Once placed and routed, final simulation with gate and net timing delays can be applied. The process of conception of the SRAM FIFO controller through to a fully functional design becomes reduced to only a few days.
SUMMARY
H I S T O R Y OF V H D L
The design of the FIFO SRAM controller can be synthesized into a number of target architectures using the Exemplar Logic synthesis system. Many advantages are
VHDL emerged from the Very High Speed Integrated Circuit (VHSIC) programme sponsored by the Department of Defense (DoD) in the late 1970s. A problem
Microprocessors and Microsystems Volume 17 Number 7 September 1993
397
VHDL and synthesis tools: C Jay associated with some military contracts was the time taken from conception through to the final commissioning. Integrated circuit technologies can change dramatically and quickly so military projects could not take full advantage of new technologies. Creating designs at a high level of abstraction could shorten this cycle, and translation into a new technology becomes a simpler and quicker task. In addition, a method of standardization was required so that design contractors and subcontractors could exchange designs in a standard format. To solve these problems, development of VHDL was started in 1983 under a DoD contract. Three years later VHDL was proposed as an IEEE standard. Following a number of revisions, it became ratified as IEEE Standard 1076 in late 1987. Since the signing of MILSTD 454L, it is a requirement that all DoD ASIC designs be completed in VHDL. Although spurred on by military contracts VHDL is quickly becominga general standard throughout industry. It now provides those same benefits as a design entry vehicle to commercial industry.
398
REFERENCES 1 2
Carlson,SIntroduction to HDL-BASED Design Using VHDL Synopsys (1990) Perry,D L VHDL McGraw-Hill, New York (1991) ................
Christopher Jay is a consultant specializing in the area of FPGA, PLD applications and software support tools. He is or has been a consultant to a number of companies such as AT&T Microelectronics, National .Semiconductor Corporation, Viewlogic, VLSI Technology Inc. and Exemplar Logic. This paper was written while Chris was a consultant to Exemplar Logic. After graduating from Essex University in _ 1977 with a BSc in electronic engineering he joined Texas Instruments in Bedford, UK as a digital design engineer. Exposure to the applications of programmable logic and FPGA devices was gained at Monolithic Memories, later merging with Advanced Micro Devices (AMD), where he became applications manager for the logic cell array (LCA) in the late 1980s. He is currently a partner in a design and manufacturing group, BAT PC Technology, based in Milpitas, California.
Microprocessors and Microsystems Volume 17 Number 7 September 1993