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Wafer marking and reading
998
World Abstracts on Microelectronics and Reliability
connection and circuit packaging design. The technical fundamentals of these alternatives are presented in this tutorial review.
Controlling semiconductor processes. AARON D. WEISS. Semiconductor Int., 61 (December 1982). Precise and accurate control of input parameters in semiconductor fabrication processes is essential to obtaining high yields. One of the driving forces in the semiconductor equipment industry is automation.
Wafer marking and reading. PETER H. SINGER. Semiconductor Int., 35 (December 1982). Through lot tracking and tracing, which enable process modifications, marking a permanent code onto every silicon wafer processed could help raise yields and productivity for both silicon and device manufacturers.
Low temperature double-exposed polyimide/oxide dielectric for VLSI multilevel metal interconnection. THOMAS E. WADE. IEEE Trans. Components Hybrids mfg Technol. C H M T - 5 (4), 516 11982). By use of a double-exposed (double-etch) low temperature polyimide/oxide process, the packing density for both first and second level metal interconnection can be improved by some 35 per cent and 30 per cent, respectively, in the vicinity of the via. Moreover, the complete interconnect process may be realized at temperatures below 300°C. Since polyimide can be applied in thick layers having negligible (tensile) stress, a planar surface results and also parasitic lead capacitances m a y be considerably reduced. This process is also amenable to either wet chemical or dry plasma processing. A simple evaporation process for producing improved interlevel via resistance. D. A. GROSE, ROSEMARY LONGO, HORATIO S. WILDMAN and JOSEPH J. GAJDA. IEEE Trans. Components Hybrids m[~ Technol. C H M T - 5 (4), 419 (1982). Auger analysis, microsectioning techniques, and electrical measurements were used to isolate the cause of high electrical resistance between two levels of aluminium copper interconnection wiring in integrated circuits. Microsectioning and scanning electron microscopic (SUM) examination of high resistance interconnections (vias) after heat treatment illustrated the existence of a continuous, interfacial film which limited the diffusion of CuA12 intermetallics at 400°C and 450°C. This interracial film was attributed to oxide regrowth during substrate heating in vacuum prior to metallization. An easily adapted evaporation process was developed to minimize the oxide regrowth during the interval between sputter cleaning and electron-beam evaporation of the A1 Cu. This process, termed modified heat process (MHP), produces improved interlevel via resistance that falls typically within specification without sinter. Auger analysis was employed to characterize the lower A1 via hole surface after selected process steps in via formation. An Auger sputter profiling technique was used to measure the amount of interfacial oxide resulting from the M H P and the standard deposition process formerly used to form interlevel vias. This analysis showed the M H P reduced the interface oxide thick: Hess 30 to 50 per cent ( ~ 2 . 0 n m for the standard process versus ~ 1.4nm or less for the MHP). SUM examination of via cross sections produced by the M H P confirmed the reduction of the interfacial oxide thickness.
Prediction of component temperatures on circuit cards cooled by natural convection. WILLIAM A. CAMPO, G. KERJILIAN and H. SHAUKATULLAH.IEEE Trans. Components Hybrids mfY Technol. C H M T - 5 (4), 499 (1982). An empirical procedure to predict component temperatures on circuit cards cooled by natural convection is described. With this procedure, test results from cards populated with only one type of component can be used to predict temperatures on cards with a mix of components.
The role of CAD in semicustom IC design. D. BROSTER and A. SOUTH. Electron. Power, 42 (January 1983). The use of semicustom integrated circuits has greatly contributed to the economic availability of computing power. C A D techniques speed up and increase the efficiency of semicustom designs, and enable the production of more complex and costeffective ICs. The art of package sealing. AARON D. WEISS. Semiconductor Int., 99 (November 1982). Packaging technology is straining to keep pace with advances in device technology. Changing package design, more stringent moisture content standards, and demand for higher throughput are bringing about changes in package sealing systems. VLSI thermal management in cost driven systems. TERRENCE E. LEWIS and DAVID L. ADAMS. IEEE Trans. Components Hybrids Mr9 Technol. C H M T - 5 (4), 361 (1982). The issues involved in the thermal management of 2 - 5 - W very largescale integrated (VLSI) chips applied in cost driven systems is addressed. Applying presently available ceramic packages and metal heatsinks to form a new packaging scheme requires caution to avoid long-term reliability failures due to thermal stresses. This is especially true when using ceramic lids with frit seals. This problem and some possible solutions are discussed in detail. For lead counts over 84 a trend exists toward pin-grid package designs. The thermal performance test results for a couple of representative pin-grid package types will be reviewed. These results show that this style of package has good thermal characteristics. The effect on thermal performance of die size variations is also discussed.
Positive resist material requirements for VLSI device fabrication. Part II. DAVID J. ELLIOTT. Solid St. Technol., 91 (December 1982). The functional properties of positive photoresist systems that are needed in VLSI microlithography were reviewed in Part I. These properties include wide imaging process latitude, good adhesion, resistance to etching environment and good exposure throughput. Other types of imaging materials that are also used in VLSIC microlithography are discussed in Part II. Thermosonic gold wire bonding to copper conductors. VERNON A. PITT and CHRISTOPHER R. S. NEEDES. IEEE Trans. Components Hybrids mfq Technol. C H M T - 5 (4), 435 (1982). The use of thick film copper conductors in hybrid microcircuitry requires that wire bonding to their surfaces be demonstrated as a feasible and reliable interconnection technique. Previous work has shown that acceptable and reliable ultrasonic aluminium wire bonds can be made to copper. The conditions necessary to make successful thermosonic gold wire bonds to copper are described. Items covered are the types of tool to use, the influence of stage temperature, the m a x i m u m dwell time for the parts on the stage, and the bonding window that yields the best results. In addition, information is provided on the reliability of the bonds following aging at temperatures in the range 150°C to 350°C, in high temperature-humidity conditions such as 40°C, 90 per cent RH, and 85°C, 85 per cent RH and after 100 thermal cycles between - 5 5 ° C and 150°C.
A unified switching theory with applications to VLSI design. JOHN P. HAYES. Proc. IEEE 70 (10), 1140 (1982). Classical switching theory is shown to have deficiencies when applied to the analysis and design o f M O S VLSI circuits. A new logic design methodology called CSA theory is described here which overcomes many of these deficiencies. It is based on three primitive component types: connectors that perform wired-logic operations, switches representing controlled connectors, and attenuators representing resistive load devices. Four basic types of logic values are recognized: Boolean 0 and 1 values, u n k n o w n or indeterminate U values, and the high-impedance state Z. The number of logic values can be
World Abstracts on Microelectronics and Reliability
connection and circuit packaging design. The technical fundamentals of these alternatives are presented in this tutorial review.
Controlling semiconductor processes. AARON D. WEISS. Semiconductor Int., 61 (December 1982). Precise and accurate control of input parameters in semiconductor fabrication processes is essential to obtaining high yields. One of the driving forces in the semiconductor equipment industry is automation.
Wafer marking and reading. PETER H. SINGER. Semiconductor Int., 35 (December 1982). Through lot tracking and tracing, which enable process modifications, marking a permanent code onto every silicon wafer processed could help raise yields and productivity for both silicon and device manufacturers.
Low temperature double-exposed polyimide/oxide dielectric for VLSI multilevel metal interconnection. THOMAS E. WADE. IEEE Trans. Components Hybrids mfg Technol. C H M T - 5 (4), 516 11982). By use of a double-exposed (double-etch) low temperature polyimide/oxide process, the packing density for both first and second level metal interconnection can be improved by some 35 per cent and 30 per cent, respectively, in the vicinity of the via. Moreover, the complete interconnect process may be realized at temperatures below 300°C. Since polyimide can be applied in thick layers having negligible (tensile) stress, a planar surface results and also parasitic lead capacitances m a y be considerably reduced. This process is also amenable to either wet chemical or dry plasma processing. A simple evaporation process for producing improved interlevel via resistance. D. A. GROSE, ROSEMARY LONGO, HORATIO S. WILDMAN and JOSEPH J. GAJDA. IEEE Trans. Components Hybrids m[~ Technol. C H M T - 5 (4), 419 (1982). Auger analysis, microsectioning techniques, and electrical measurements were used to isolate the cause of high electrical resistance between two levels of aluminium copper interconnection wiring in integrated circuits. Microsectioning and scanning electron microscopic (SUM) examination of high resistance interconnections (vias) after heat treatment illustrated the existence of a continuous, interfacial film which limited the diffusion of CuA12 intermetallics at 400°C and 450°C. This interracial film was attributed to oxide regrowth during substrate heating in vacuum prior to metallization. An easily adapted evaporation process was developed to minimize the oxide regrowth during the interval between sputter cleaning and electron-beam evaporation of the A1 Cu. This process, termed modified heat process (MHP), produces improved interlevel via resistance that falls typically within specification without sinter. Auger analysis was employed to characterize the lower A1 via hole surface after selected process steps in via formation. An Auger sputter profiling technique was used to measure the amount of interfacial oxide resulting from the M H P and the standard deposition process formerly used to form interlevel vias. This analysis showed the M H P reduced the interface oxide thick: Hess 30 to 50 per cent ( ~ 2 . 0 n m for the standard process versus ~ 1.4nm or less for the MHP). SUM examination of via cross sections produced by the M H P confirmed the reduction of the interfacial oxide thickness.
Prediction of component temperatures on circuit cards cooled by natural convection. WILLIAM A. CAMPO, G. KERJILIAN and H. SHAUKATULLAH.IEEE Trans. Components Hybrids mfY Technol. C H M T - 5 (4), 499 (1982). An empirical procedure to predict component temperatures on circuit cards cooled by natural convection is described. With this procedure, test results from cards populated with only one type of component can be used to predict temperatures on cards with a mix of components.
The role of CAD in semicustom IC design. D. BROSTER and A. SOUTH. Electron. Power, 42 (January 1983). The use of semicustom integrated circuits has greatly contributed to the economic availability of computing power. C A D techniques speed up and increase the efficiency of semicustom designs, and enable the production of more complex and costeffective ICs. The art of package sealing. AARON D. WEISS. Semiconductor Int., 99 (November 1982). Packaging technology is straining to keep pace with advances in device technology. Changing package design, more stringent moisture content standards, and demand for higher throughput are bringing about changes in package sealing systems. VLSI thermal management in cost driven systems. TERRENCE E. LEWIS and DAVID L. ADAMS. IEEE Trans. Components Hybrids Mr9 Technol. C H M T - 5 (4), 361 (1982). The issues involved in the thermal management of 2 - 5 - W very largescale integrated (VLSI) chips applied in cost driven systems is addressed. Applying presently available ceramic packages and metal heatsinks to form a new packaging scheme requires caution to avoid long-term reliability failures due to thermal stresses. This is especially true when using ceramic lids with frit seals. This problem and some possible solutions are discussed in detail. For lead counts over 84 a trend exists toward pin-grid package designs. The thermal performance test results for a couple of representative pin-grid package types will be reviewed. These results show that this style of package has good thermal characteristics. The effect on thermal performance of die size variations is also discussed.
Positive resist material requirements for VLSI device fabrication. Part II. DAVID J. ELLIOTT. Solid St. Technol., 91 (December 1982). The functional properties of positive photoresist systems that are needed in VLSI microlithography were reviewed in Part I. These properties include wide imaging process latitude, good adhesion, resistance to etching environment and good exposure throughput. Other types of imaging materials that are also used in VLSIC microlithography are discussed in Part II. Thermosonic gold wire bonding to copper conductors. VERNON A. PITT and CHRISTOPHER R. S. NEEDES. IEEE Trans. Components Hybrids mfq Technol. C H M T - 5 (4), 435 (1982). The use of thick film copper conductors in hybrid microcircuitry requires that wire bonding to their surfaces be demonstrated as a feasible and reliable interconnection technique. Previous work has shown that acceptable and reliable ultrasonic aluminium wire bonds can be made to copper. The conditions necessary to make successful thermosonic gold wire bonds to copper are described. Items covered are the types of tool to use, the influence of stage temperature, the m a x i m u m dwell time for the parts on the stage, and the bonding window that yields the best results. In addition, information is provided on the reliability of the bonds following aging at temperatures in the range 150°C to 350°C, in high temperature-humidity conditions such as 40°C, 90 per cent RH, and 85°C, 85 per cent RH and after 100 thermal cycles between - 5 5 ° C and 150°C.
A unified switching theory with applications to VLSI design. JOHN P. HAYES. Proc. IEEE 70 (10), 1140 (1982). Classical switching theory is shown to have deficiencies when applied to the analysis and design o f M O S VLSI circuits. A new logic design methodology called CSA theory is described here which overcomes many of these deficiencies. It is based on three primitive component types: connectors that perform wired-logic operations, switches representing controlled connectors, and attenuators representing resistive load devices. Four basic types of logic values are recognized: Boolean 0 and 1 values, u n k n o w n or indeterminate U values, and the high-impedance state Z. The number of logic values can be