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Whole wafer assessment of electronic materials by scanning photoluminescence and surface photovoltage
186
Materials Science and Engineering B 20 ( 1993) 186-189
Whole wafer assessment of electronic materials by scanning photoluminescence and surface photovoltage Maciej Bugajski a, Piotr Edelman b, Jacek Ornoch a, Marek WesolowskP, Wojciech kewandowskP and Krzysztof Kucharski a ~Institute of Electron Technology, Al. Lotnikdw 32/46, 02 668 Warsaw (Poland) I'Centerfor Microelectronics Research, University of South Florida, Tampa, FL 33620-5350 (USA)
Abstract In this paper, we describe apparatus h>r measuring photoluminescence (PL) over the entire wafer and discuss specific examples related to the evaluation of compound semiconductor materials. The origin of PL contrast in different cases is discussed and some physics underlying the PL process is given, We also show how a combined use of a non-contact, surface photovoltage (SPV) technique and scanning PL (SPL) can contribute to our understanding of a variety of processing effects in silicon,
1. Introduction
The very tight material standards dictated by reliability, performance considerations and manufacturing yield of electronic devices impose increasing demands on wafer characterization. The average values of various materials parameters used so far to assess wafer quality are not sufficient. A strong and growing demand has developed for characterization techniques capable of giving a clear picture of wafer inhomogencities, before as well as during processing. Such techniques should be non-destructive and applicable to standard production-line wafers, regarding size and thickness. The final important factor is the speed of measurements and lack of special surface preparation. The ideal candidate which meets the above criteria is the scanning photoluminescence (SPL) technique [1-3]. Capable of being fully automated, photoluminescence (PL) spectroscopy also yields a variety of data unmatched by other methods. The information available via PL analysis includes impurity levels in a sample and the distribution of dopants or defects over the surface of the wafer. These data are fundamental in establishing optimum growth parameters and in judging whether or not specified parameters are being maintained. Another characterization technique which fulfils the requirement for fast wafer-scale measurements is the surface photovoltage (SPV) method, which is known as a standard technique for the determination of minority carrier diffusion length in semiconductors. Recently, a novel SPV approach, 0921-5107/93/$6.00
based on using a truly non-contact, capacitancecoupled photovoltage probe and a new constant photon flux, linear principle, has been proposed [411. The combination of SPL and SPV can lead to a better understanding of the physical phenomena taking place during growth and processing.
2. Experimental details
The PL mapping system developed in our laboratory includes the following: an optical scanning module (shown in Fig. 1), power drivers for stepping motors, an 8255 digital input-output card for stepping motors control, a 12 bit 60 ps analog-digital converter card for data acquisition and a PC AT computer with hard disk and EGA monitor. The rest of the system is conventional PL equipment. We used an argon laser, grating monochromator and photomultiplier or cooled germanium detector. The system is equipped with a large window, liquid helium cryostat, allowing for mapping in 2 in wafers. When operation of the system is restricted to room temperature, larger 6 in wafers can be analysed. The size of the map can be varied (typically, it is 100 x 100 points).
3. Results
To test the validity of the PL mapping technique, a large number of both monocrystalline and epitaxial © 1993 - Elsevier Sequoia. All rights reserved
M. Bugajski et al. 16,~ e"
/ SPVand SPL of electronic wafermaterials
187
Y
yoFig. 1. Optical scanning module. samples were studied. Here, we will show only a few typical appliations of the SPL method, demonstrating its great potential for research and production control. 3.1. Bridgman-grown GaAs:Si Samples used in this study were silicon-doped, dislocation-free GaAs(100) wafers grown by the gradientfreeze method. The sample dimensions were 25 mm x 40 mm and their parameters n = 1.41-2.48 x 1018 cm- 3, p = 1500-1980 cm 2 V- 1 s- 1 and etch pit density (EPD) < 8 0 0 cm -2. The PL measurements were carried out at room temperature. The maps of the band-edge PL intensity are illustrated in Fig. 2. Subsequent pictures were taken on wafers from the seed, central and tail parts of the ingot. All the samples show characteristic patterns of PL intensity, reflecting changes in the shape of the solid-liquid interface during crystal growth; from paraboloidal near the seed to almost plane-shaped in the tail region [5]. The lower PL intensity in the center of the wafers can be correlated with structural defects observed mainly in regions near the concave interface [6]. The increasing homogeneity of the wafers as we progress towards the tail of the crystal results from flattening of the crystallization front, accompanied by a reduction in the internal thermal stress in the crystal. The crystals grown by the gradient-freeze method are used as substrates for light-emitting diodes and lasers, because of their low dislocation density and uniformity. Therefore, it is very important to have a simple method to identify eventual defect-rich regions in the crystal and eliminate them from further processing. 3.2. Czochralski-grown silicon Samples used in this study were standard 3 in, p-type Czochralski-grown silicon wafers with resist-
Fig. 2. Room temperature maps of the band-edge PL intensity for GaAs:Si wafers cut from the (a) seed, (b) central and (c) tail parts of the crystal grown by the gradient-freeze method.
ivity p = 5 ff~ cm. They were subjected to different processing steps and subsequent surface photovoltage (SPV) and SPL measurements. The magnitude of the average diffusion length L reduction after certain processing steps indicates a degree of contamination, whereas the maps of L distribution shown in Fig. 3 tell
188
M. Bugajski et al.
/' .S'Pr and 57'L oJ elecmmic waler materia/~
o~sr~teurloN or QIrrustoN kENGTH
~52
r~
~54 ¢~xp
val~
~55
~56
~57 Fig. 3. Room temperature SPV maps of diffusion length distribution (left) and PL maps of Fe.ro transitions (right) for commercial silicon wafers subjected to various processing steps: A52, as received; A54, 720 °C (18 h)+ 1150 °C (3 h)+ oxidation 1000 °C (6 h); A55, t 150 °C (3 h); A56, 1150 °C (3 h) + oxidation 1000 °C (6 h): A57, oxidation t 000 °C (3 h).
M. Bugajski et al.
/
SP V and SPL of electronic wafer materials
us about the wafer uniformity. Evidently, field oxidation (A57) and processes involving oxidation as a final step (A54, A56) are the contaminating steps. All the wafers studied showed a characteristic "rainbow pattern", ie. they are heavily contaminated on one side and much less contaminated on the other side. This behavior suggests that contamination originates from the boat holding the wafer during the high temperature process. The decrease in the diffusion length is due to defects acting as recombination centers and decreasing the minority carrier lifetime. Fast diffusing metal impurities--most probably iron--are possible candidates for these centers [7]. In contrast, only the wafer (A55) subjected to high temperature annealing does not show any clear contamination pattern, except for an overall reduction in the diffusion length. The maps of the diffusion length are comparable with the PL maps showing room temperature distribution of the intensity of free exciton (FETo) transitions peaking at about 1140 nm. The maps show clear similarities, the regions of higher diffusion length correspond to the regions of higher PL intensity, since both parameters are related to the minority carrier lifetime. For the luminescence signal to be proportional to the bulk minority carrier lifetime, it is necessary for the occupation of exciton states to be in equilibrium with the electron population in the conduction band [8]. This means that the thermalization time of the excitons has to be short compared with the other time constants involved. For relatively shallow exciton states in silicon (E x = 17 meV) at room temperature, this condition is easily fulfilled. Therefore, we can state that the PL intensity variations in this case are exclusively due to
189
the changes in the minority carrier lifetime resulting from wafer contamination during processing.
4. Conclusions
This work demonstrates the feasibility of a room temperature, non-contact PL mapping technique to assess the quality of whole wafers of compound semiconductor materials. It also shows how the combined use of SPL and SPV allows the evaluation of processing effects in production-type silicon wafers. We also demonstrate, for the first time, the practical realization and usefulness of a room temperature PL mapping in silicon.
References
1 M. Bugajski, E Edelman and J. Ornoch, Acta Phys. Pol. A, 77 (1990) 145. 2 M. Bugajski and J. Ornoch, Am. Inst. Phys. ('onf Proc., 227 (1991)38. 3 E Edelman, W. Henley and J. Lagowski, Semicond. Sci. Technol., 7 (1992) 22. 4 J. Lagowski,P. Edelman, M. Dexter and W. Henley~Sernicond. Sci. Technol., 7(1992)A185. 5 P. Edelman, J. Ornoch and W. Lewandowski, C~st. Properties Prep. 19-20(1989) 91. 6 K. Fujii, M. Hirata, H. Fujita and S. Takeda, in K. Sumino (ed.), Defect Control in Serniconductors, North-Holland, Amsterdam, 1990, p. 667. 7 G. Zoth and W. Bergholtz, J. Appl. Phys., 67(1990) 6764. 8 R. Z. Bachrach and O. G. Lorimor, J. Appl. Phys., 43(1972) 500.
Materials Science and Engineering B 20 ( 1993) 186-189
Whole wafer assessment of electronic materials by scanning photoluminescence and surface photovoltage Maciej Bugajski a, Piotr Edelman b, Jacek Ornoch a, Marek WesolowskP, Wojciech kewandowskP and Krzysztof Kucharski a ~Institute of Electron Technology, Al. Lotnikdw 32/46, 02 668 Warsaw (Poland) I'Centerfor Microelectronics Research, University of South Florida, Tampa, FL 33620-5350 (USA)
Abstract In this paper, we describe apparatus h>r measuring photoluminescence (PL) over the entire wafer and discuss specific examples related to the evaluation of compound semiconductor materials. The origin of PL contrast in different cases is discussed and some physics underlying the PL process is given, We also show how a combined use of a non-contact, surface photovoltage (SPV) technique and scanning PL (SPL) can contribute to our understanding of a variety of processing effects in silicon,
1. Introduction
The very tight material standards dictated by reliability, performance considerations and manufacturing yield of electronic devices impose increasing demands on wafer characterization. The average values of various materials parameters used so far to assess wafer quality are not sufficient. A strong and growing demand has developed for characterization techniques capable of giving a clear picture of wafer inhomogencities, before as well as during processing. Such techniques should be non-destructive and applicable to standard production-line wafers, regarding size and thickness. The final important factor is the speed of measurements and lack of special surface preparation. The ideal candidate which meets the above criteria is the scanning photoluminescence (SPL) technique [1-3]. Capable of being fully automated, photoluminescence (PL) spectroscopy also yields a variety of data unmatched by other methods. The information available via PL analysis includes impurity levels in a sample and the distribution of dopants or defects over the surface of the wafer. These data are fundamental in establishing optimum growth parameters and in judging whether or not specified parameters are being maintained. Another characterization technique which fulfils the requirement for fast wafer-scale measurements is the surface photovoltage (SPV) method, which is known as a standard technique for the determination of minority carrier diffusion length in semiconductors. Recently, a novel SPV approach, 0921-5107/93/$6.00
based on using a truly non-contact, capacitancecoupled photovoltage probe and a new constant photon flux, linear principle, has been proposed [411. The combination of SPL and SPV can lead to a better understanding of the physical phenomena taking place during growth and processing.
2. Experimental details
The PL mapping system developed in our laboratory includes the following: an optical scanning module (shown in Fig. 1), power drivers for stepping motors, an 8255 digital input-output card for stepping motors control, a 12 bit 60 ps analog-digital converter card for data acquisition and a PC AT computer with hard disk and EGA monitor. The rest of the system is conventional PL equipment. We used an argon laser, grating monochromator and photomultiplier or cooled germanium detector. The system is equipped with a large window, liquid helium cryostat, allowing for mapping in 2 in wafers. When operation of the system is restricted to room temperature, larger 6 in wafers can be analysed. The size of the map can be varied (typically, it is 100 x 100 points).
3. Results
To test the validity of the PL mapping technique, a large number of both monocrystalline and epitaxial © 1993 - Elsevier Sequoia. All rights reserved
M. Bugajski et al. 16,~ e"
/ SPVand SPL of electronic wafermaterials
187
Y
yoFig. 1. Optical scanning module. samples were studied. Here, we will show only a few typical appliations of the SPL method, demonstrating its great potential for research and production control. 3.1. Bridgman-grown GaAs:Si Samples used in this study were silicon-doped, dislocation-free GaAs(100) wafers grown by the gradientfreeze method. The sample dimensions were 25 mm x 40 mm and their parameters n = 1.41-2.48 x 1018 cm- 3, p = 1500-1980 cm 2 V- 1 s- 1 and etch pit density (EPD) < 8 0 0 cm -2. The PL measurements were carried out at room temperature. The maps of the band-edge PL intensity are illustrated in Fig. 2. Subsequent pictures were taken on wafers from the seed, central and tail parts of the ingot. All the samples show characteristic patterns of PL intensity, reflecting changes in the shape of the solid-liquid interface during crystal growth; from paraboloidal near the seed to almost plane-shaped in the tail region [5]. The lower PL intensity in the center of the wafers can be correlated with structural defects observed mainly in regions near the concave interface [6]. The increasing homogeneity of the wafers as we progress towards the tail of the crystal results from flattening of the crystallization front, accompanied by a reduction in the internal thermal stress in the crystal. The crystals grown by the gradient-freeze method are used as substrates for light-emitting diodes and lasers, because of their low dislocation density and uniformity. Therefore, it is very important to have a simple method to identify eventual defect-rich regions in the crystal and eliminate them from further processing. 3.2. Czochralski-grown silicon Samples used in this study were standard 3 in, p-type Czochralski-grown silicon wafers with resist-
Fig. 2. Room temperature maps of the band-edge PL intensity for GaAs:Si wafers cut from the (a) seed, (b) central and (c) tail parts of the crystal grown by the gradient-freeze method.
ivity p = 5 ff~ cm. They were subjected to different processing steps and subsequent surface photovoltage (SPV) and SPL measurements. The magnitude of the average diffusion length L reduction after certain processing steps indicates a degree of contamination, whereas the maps of L distribution shown in Fig. 3 tell
188
M. Bugajski et al.
/' .S'Pr and 57'L oJ elecmmic waler materia/~
o~sr~teurloN or QIrrustoN kENGTH
~52
r~
~54 ¢~xp
val~
~55
~56
~57 Fig. 3. Room temperature SPV maps of diffusion length distribution (left) and PL maps of Fe.ro transitions (right) for commercial silicon wafers subjected to various processing steps: A52, as received; A54, 720 °C (18 h)+ 1150 °C (3 h)+ oxidation 1000 °C (6 h); A55, t 150 °C (3 h); A56, 1150 °C (3 h) + oxidation 1000 °C (6 h): A57, oxidation t 000 °C (3 h).
M. Bugajski et al.
/
SP V and SPL of electronic wafer materials
us about the wafer uniformity. Evidently, field oxidation (A57) and processes involving oxidation as a final step (A54, A56) are the contaminating steps. All the wafers studied showed a characteristic "rainbow pattern", ie. they are heavily contaminated on one side and much less contaminated on the other side. This behavior suggests that contamination originates from the boat holding the wafer during the high temperature process. The decrease in the diffusion length is due to defects acting as recombination centers and decreasing the minority carrier lifetime. Fast diffusing metal impurities--most probably iron--are possible candidates for these centers [7]. In contrast, only the wafer (A55) subjected to high temperature annealing does not show any clear contamination pattern, except for an overall reduction in the diffusion length. The maps of the diffusion length are comparable with the PL maps showing room temperature distribution of the intensity of free exciton (FETo) transitions peaking at about 1140 nm. The maps show clear similarities, the regions of higher diffusion length correspond to the regions of higher PL intensity, since both parameters are related to the minority carrier lifetime. For the luminescence signal to be proportional to the bulk minority carrier lifetime, it is necessary for the occupation of exciton states to be in equilibrium with the electron population in the conduction band [8]. This means that the thermalization time of the excitons has to be short compared with the other time constants involved. For relatively shallow exciton states in silicon (E x = 17 meV) at room temperature, this condition is easily fulfilled. Therefore, we can state that the PL intensity variations in this case are exclusively due to
189
the changes in the minority carrier lifetime resulting from wafer contamination during processing.
4. Conclusions
This work demonstrates the feasibility of a room temperature, non-contact PL mapping technique to assess the quality of whole wafers of compound semiconductor materials. It also shows how the combined use of SPL and SPV allows the evaluation of processing effects in production-type silicon wafers. We also demonstrate, for the first time, the practical realization and usefulness of a room temperature PL mapping in silicon.
References
1 M. Bugajski, E Edelman and J. Ornoch, Acta Phys. Pol. A, 77 (1990) 145. 2 M. Bugajski and J. Ornoch, Am. Inst. Phys. ('onf Proc., 227 (1991)38. 3 E Edelman, W. Henley and J. Lagowski, Semicond. Sci. Technol., 7 (1992) 22. 4 J. Lagowski,P. Edelman, M. Dexter and W. Henley~Sernicond. Sci. Technol., 7(1992)A185. 5 P. Edelman, J. Ornoch and W. Lewandowski, C~st. Properties Prep. 19-20(1989) 91. 6 K. Fujii, M. Hirata, H. Fujita and S. Takeda, in K. Sumino (ed.), Defect Control in Serniconductors, North-Holland, Amsterdam, 1990, p. 667. 7 G. Zoth and W. Bergholtz, J. Appl. Phys., 67(1990) 6764. 8 R. Z. Bachrach and O. G. Lorimor, J. Appl. Phys., 43(1972) 500.