X-ray experiment electronic instrumentation for high altitude balloon and rocket flights

NUCLEAR

INSTRUMENTS

AND METHODS

72 (I969)

I3-22;

© NORTH-HOLLAND

PUBLISHING

CO.

X-RAY E X P E R I M E N T E L E C T R O N I C I N S T R U M E N T A T I O N F O R H I G H A L T I T U D E B A L L O O N AND R O C K E T F L I G H T S C. A. CANCRO, W. R. CROCKETT*, N. M. G A R R A H A N and R. G. M c G O W A N

Flight Data Systems Branch, Spacecraft Technology Division, Goddard Space Flight Center, Greenbelt, Maryland, U.S.A.

Received 14 January 1969 An electronic instrumentation system, developed for use in X-ray experiments to be flown on high-altitude balloons and rockets, is described. The system selects and analyzes output pulses from X-ray detector proportional counters and scintillating crystals, arranges the desired data in a P C M format and feeds this digital

data at a 50 kHz to 100 kHz bit rate to the telemetry transmitter. The system is designed to minimize power drain, weight and volume, while maintaining a high degree of reliability. The system has operated successfully in a 1968 rocket flight. Additional rocket and balloon flights, making use of variations of this system, are planned for the near future.

1. Introduetion An electronic instrumentation system was developed for a series of high-altitude balloon and rocket X-ray experiments. The electronics selects and analyzes X-ray data obtained by the detector system, arranges the desired data in a P C M format and feeds this digital data at a 50 to 100 kHz bit rate to the telemetry transmitter. Because of payload limitations, the system was designed and developed to minimize power drain, weight and volume while operating over a temperature range of - 10°C to 55°C. D a t a selection is accomplished by circuitry devised through further development of the hybrid transistor tunnel diode pulse generator and logic decribed 1' 2). Pulse height analysis and threshold detection are accomplished by use of circuitry similar to that previously developed and described in 2). The digital data processing required for telemetry encoding is accomplished by use of low power drain digital integrated circuitry. This system operated successfully in an X-ray experiment flown on an Aerobee 150 rocket at White Sands, New Mexico, in March 1968. The results of this experiment are reported3). Additional rocket and balloon flights, making use of variations of this system, are planned for the near future.

electrical pulses are obtained for processing, with amplitude proportional to the energy lost by a charged particle or X-ray to ionization in the detection medium. The detector rise times vary from 0.05 #sec for the plastic scintillator to 1.5 #sec for the CsI. The argon and krypton counters have characteristic rise times of about 0.5 #sec. The primary events of interest are X-rays incident along the detector system axis (line of sight). Unlike an energetic charged particle that ionizes traversed matter continuously along its entire trajectory, an X-ray is characterized by the expenditure of all its energy in a

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2. Parameters measured Fig. 1 is a diagram showing a cross section of a typical detector system. This one is described briefly to indicate the characteristics of the input signals to the electronic instrumentation system. The detectors consist of 3 argon-gas proportional counter tubes, 3 krypton-gas proportional counter tubes, a CsI scintillating crystal and a plastic scintillator guard crystal in the arrangement shown. In all four types of detectors, * Presently with Naval Research Laboratory, Washington, D.C,

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13

14

C.A. CANCRO et al. TABLE 1 X-ray rocket experiment. Parameters measured and form of output. Parameter measured

Form of output

Pulse height of processed A~, K~ or B Identification of channel of processed pulse (At, Kt or B) Scaler II - sum of A¢ and K~ events meeting all non-coincidence requirements Scaler II' - sum of B events meeting all non-coincidence requirements Scaler I - sum of line of sight A~ and K~ events not meeting non-coincidence requirements Scaler I' - sum of line of sight B events C1 rate bit Ill - 100 kc or > C1 rate bit II - 50 kc or > C1 rate bit I - 25 kc or > C2 rate bit - 100 kc or > Mark bit-B1 received within 2.0 ffsec after processed A~ or K~, or C1 received within 2 ffsec before processed B

Seven bit binary word Three bit binary word Three bit binary word Two bit binary word. Six bit binary word Six bit binary word Single bit Single bit Single bit Single bit

3. Telemetry format

Single bit

single interaction, with the resulting ionization being well enough localized such that only one c o u n t e r will fire. Thus an X-ray event of interest occurs when an o u t p u t is obtained from only one of the Ai, K i or Csl

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Fig. 2 shows the telemetry r e a d o u t format. As indicated, a frame of 64 sixteen-bit words is repeated continuously. W o r d 1 is the 16-bit sync word. W o r d 33 consists of r e a d o u t of the Scaler I, Scaler I' a n d C rates (as described in table 1). Each of words 2 t h r o u g h 32 a n d 34 t h r o u g h 64 consists of the A D C ( A n a l o g to Digital Converted 7-bit X-ray energy amplitude), I.D. (detector identification), Mark, Scaler II a n d Scaler II' bits. The telemetry m a y be read out at rates up to 100 kHz. The timing shown in fig. 2 corresponds to a 100 kHz bit rate. A t this rate, r e a d o u t time for one bit is 10 #sec. Thus a 16-bit word r e a d o u t time is 160 ~tsec a n d a frame readout time is 10.240 msec.

34

THRU

64

READOUT EACH WORD CONSISTS OF SCALERS READOUT OF I D BITS, T, I ' a ADC, MARK BIT AND C BATE SCALERS1"r ANO ~ ' p.,~.~__

11 FRAME READOUT TIME 10,240 MILLISECONDS)

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(B channel) detectors with no o u t p u t from the plastic guard (C channel) detector. A further r e q u i r e m e n t for an X-ray event of interest is that the o u t p u t amplitude from any of the detectors lies between a prescribed lower level and a prescribed upper level. W h e n an X-ray event of interest is obtained, the outp u t pulse amplitude is converted into a 7-bit binary n u m b e r p r o p o r t i o n a l to the incident X-ray energy. Also a 3-bit b i n a r y word is generated indicating the detector in which the X-ray energy was expended. Various data rates are also measured a n d processed. Table 1 lists all the parameters measured, together with the form of the output.

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Fig. 3. X-ray experiment data flow diagram. 4. S y s t e m s d a t a flow

Fig. 3 is a data flow diagram of the X-ray experiment. This shows howthe electronics analyzes the detector output pulses to obtain the data of interest. It will be noted that the rise times of the detector output pulses are used to establish the coincident anti-coincident times. The At and K~ lower level inputs are inhibited for I).75/~sec following each C1 (lower level) actuation and when not inhibited are analyzed for non-coincidence within 0.75 #sec. If one A t or K~ lower level input occurs by itself, this event is processed (A to D con'version and I.D. word). Also if a B-input occurs within 2.0/~sec following this event a digital one is generated in the M a r k Bit. The B lower level input is inhibited for 2.0 #sec following each C2 (upper level) actuation and when :not inhibited is analyzed for non-coincidence with A t and K~ inputs from 2.0 #sec previous to and 0.75 #sec after its occurence. If the B lower level input occurs by :itself this event is processed (A to D conversion and I.D. word). Also, if a C1 actuation occurs in the 2.0 #sec preceding this B event a digital one is generated in the Mark Bit.

The C1 and C2 actuation rates are counted. Output bits are obtained when C1 rate exceeds 100 kHz, 50 kHz and 25 kHz and when C2 rate exceeds 100 kHz. It will be seen that should the C1 rate exceed 100 kHz, C2 replaces C1 as the signal used to inhibit the At and K i inputs, and also B events are inhibited. Further, if the C2 rate exceeds 100 kHz, C no longer inhibits Ai and K~ inputs. The A~ and K~ proportional counters and the CsI crystal have recovery times of approximately 10/~sec when actuated. Thus a second actuation received during this recovery time will give a biased output. If an A~, K~ or B event meeting all other coincident anti-coincident requirements should occur during a detector recovery time the event is processed but the A to D readout is made to read zero. Scaler I counts all A t and Ki events not meeting non-coincidence requirements. Scaler I' counts all B events which are not inhibited by C. Scalers II and II' count all A t and K~, and B events, respectively, meeting all coincidence anti-coincidence requirements. The readouts described above, summarized in table 1 are fed to the encoder. This data is telemetered in the

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X-RAY

EXPERIMENT

ELECTRONIC

format shown in fig. 2 as described previously.

5. System operation Fig. 4 is a system block diagram of the X-ray experiment. The detector is packaged separately as shown. The A1, A2, A3, K1, K2, K3, B and C outputs from the detector are fed into their respective channel cards. Since channel cards A1, A2, A3, K1, K2 and K3 are identical, a detailed block diagram is shown only for channel A1. The input to channel A1 is shaped and then branches into two separate circuits in the delay amplifier. In one branch the signal is delayed approximately 2.0 ~tsec before reaching the linear gate. This delay allows the logic circuitry time to determine whether the linear gate (which is normally blocking) should allow the signal to pass. The signal in the second branch (not delayed) goes to the logic circuitry. This signal is applied to a chain of two amplifiers. These amplifiers drive respective threshold detectors which yield an output spike for input signals exceeding the lower and upper levels. The spikes in turn trigger 0.75 #sec pulse generators, provided no inhibiting signal from channel C is applied. As will be described below, whenever a channel C input signal exceeding the C lower level is received, a 0.75 #sec inhibiting pulse is generated. Thus lower level and upper level 0.75 psec output pulses are generated only when these thresholds are exceeded and also no C1 signal was received within the previous 0.75 #sec. The upper level and lower level output pulses from A1, A2, A3, K1, K2 and K3 cards are fed to the upper level OR circuit and the lower level summing amplifier in card 10. The function of the circuits on card 10 is to determine whether a single A s or Ki lower level signal has occurred and also to provide outputs to Scaler I and Scaler II. The output of the summing amplifier drives two threshold detectors. One threshold detector yields a 0.75 #sec pulse for one or more coincident inputs and the other yields an output for two or more coincident inputs. The pulse output from the first threshold detector generates a spike at its trailing edge and this in turn triggers a 500 nsec pulse generator, provided it is not inhibited by a 1.25 psec inhibiting pulse. This inhibiting pulse may be generated by any of the A or K upper level inputs, or the output from the two-or-more coincident A-K lower level input threshold detector. Thus a 500 nsec output pulse is generated when a single lower-level A i or K, input signal is received. The inhibit pulse indicates A and K events not meeting level and/or non-coincident requirements. These inhibit pulses are fed to the input of

INSTRUMENTATION

17

Scaler I. The 500 nsec output pulse (indicating an X-ray event of interest) is fed to Scaler II and an A N D gate. As will be described below, if the ADC (Analog to Digital Converter) is not processing or waiting for readout, the system bistable in card 11 will be in the reset state. This allows the 500 nsec output pulse to pass through the A N D gate and trigger event enable pulse generators (0.75/tsec) in each of channel cards A1, A2, A3, K1, K2 and K3. In each of these cards this pulse is fed to one of two inputs of the event enable A N D gate. Only one of these gates will yield an output. This will be the gate in the A or K channel in which the single lower level non-coincident input signal was received. It will be noted that the 0.75 ~tsec pulse generated by the lower level threshold detector is delayed 0.75 #sec and fed to the second input of the event enable A N D gate. The output of the event enable A N D gate drives both an event out pulse generator and an inhibit gate. The event out pulse generator yields a 0.75/~sec pulse which is fed to the Event Identifying (I.D.) Matrix in card 12. The operation of this card will be described later. The signal to the inhibit gate, if not inhibited, will pass through and trigger the linear gate drive. The linear gate driver opens the linear gate for approximately 2.0 #sec allowing the delayed input signal to go through to the ADC card. However, if an inhibiting signal is applied, the linear gate will not be opened, and the ADC output will be zero. Inhibiting occurring at this time indicates a signal has been received in the channel detector in the 10 #sec prior to the receipt of the X-ray event. When a lower level threshold detector spike is generated, this spike is delayed 3.5#sec and then triggers a 13.5 #sec resettable memory. The resettable memory may be triggered at any time to restart. The output of this memory is the signal that inhibits the gate to the linear gate driver. Thus the linear gate will not open when an event enable signal is received if the resettable memory has been actuated within the previous 13.5 #sec. If an event has not been received in the previous 10 #sec, an event enable pulse will open the linear gate due to the 3.5 #sec delay in actuating the resettable memory. This 3.5 #sec assures sufficient time for the logic circuitry to determine whether an event of interest has occurred. A 13.5 #sec resettable memory time is used (rather than 10.0 #sec) since the 3.5 #see delay pulse generator will not retrigger if a second event occurs during a 3.5 #sec delay. It will be noted from fig. 4 that the operation of channel B card is very similar to that of the A and K channel cards. The only difference is in the timing and

18

C . A . C A N C R O et al.

Detector Spikers, respectively. Outputs from the C2 the mode of inhibiting the B outputs. Since B channel input signals have a rise time of approximately 1.5 ~sec and C1 Threshold Detectors are obtained when the C the signal delay to the linear gate is 2.5/~sec and the input signal exceeds C2 and C1 levels, respectively. resettable memory and its associated delay are 14.0 and Each threshold detector drives separate 2.0 #sec reset4.0 psec, respectively. The output of the B1 threshold table memories, normalizing amplifiers and gates. The detector spiker triggers a 300 nsec pulse generator if not output of the C2 resettable memory (2.0/tsec) is used inhibited by the C2 resettable memory. As will be to inhibit the B1 output, as was described earlier. The explained later, whenever the plastic or C channel input output of the C1 resettable memory (2.0/~sec) is used as exceeds the upper C2 level, the C2 two/tsec resettable an input to the Mark Bit logic, as will be described later. memory is actuated. The output of this resettable The normalizing amplifiers yield output pulses of fixed memory inhibits the 300 nsec B1 output pulse generator. width and amplitude which drive the C2 and C1 Rate Thus, a B1 output pulse is generated for a B input Circuits. The C2 Rate Circuit drives a Threshold exceeding the lower level only when a C2 signal has not Detector which yields a dc output level when the C2 input rate exceeds 100 kHz. This dc level is fed to the been received during the previous 2.0 ktsec. The B1 300 nsec output pulse drives Scaler I' in the encoder in card 13 as the C2 Rate Bit input and to the encoder (Card 13) and triggers two pulse generators C2 gate as an inhibiting signal. The C1 Rate Circuit (0.75 and 2.0/~sec) in Card 11. The trailing edge of the output drives three threshold detector output circuits. 0.75 psec pulse in turn triggers a 2.0/~sec pulse generator These three circuits yield dc level output signals when (B1 delayed) if not inhibited by the pulse from the the C1 rate exceeds 25 kHz, 50 kHz and 100 kHz, as 2.75 #sec pulse generator. This inhibiting pulse gener- shown. The dc output signals are fed to the encoder in ator is triggered by any one of the A1, A2, A3, K1, or card 13 as the C2 Bits I, II and III inputs, respectively. K3 low level output signals through an OR gate. Thus Also the 100 kHz rate dc output is fed to the CI gate the 2.0/~sec delayed B1 pulse is generated ifa B1 output as an inhibiting signal. The C1 and C2 threshold detector spiker outputs are is received and no A or K signal has occurred within fed to the respective C1 and C2 gates. If not inhibited, the previous 2.0/~sec or the following 0.75/~sec. The trailing edge of this delayed B1 output triggers these signals go through to the OR gate and trigger the the 500 nsec pulse generator if it is not inhibited by the 0.75/tsec pulse generator. This pulse is amplified and pulse from the 3.0/~sec B1 and B2 pulse generator. As applied as the C inhibiting signal to cards A1-A3, and, indicated this 3.0 #sec pulse is generated by the output K1-K3 as described earlier. If C1 rate exceeds 100 kHz, of the AND gate with the 2.0/tsec B1 pulse generator the C1 gate is inhibited and C2 signals through the C2 and B2 threshold spiker as inputs. Thus the 500 nsec gate generate the C inhibiting output pulse. Also when C1 rate exceeds 100 kHz, B events are inhibited by the pulse is obtained when a B signal between level B1 and B2 non-coincident with A or K signals (B channel gate in card 11. If C2 rate exceeds 100 kHz, the C2 gate is inhibited also and no C inhibiting output pulse is X-ray event) is received. The 500 nsec output pulse obtained for a B channel generated. As indicated in fig. 4, the outputs of the AI, A2, A3, X-ray event feeds both the input to Scaler II' in the encoder and a series of two A N D gates. If the system K1, K2, K3 and B linear gates are connected in parallel bistable (operation to be described later) is in the reset and feed the input to the Analog to Digital Converter state and not in the process of being reset and if C1 (ADC) card. An X-ray event yields an output pulse output rate does not exceed 100 kHz, the 500 nsec from one of the linear gates. The primary function of pulse is allowed to pass through to the event enable the ADC card is to convert the linear gate output pulse input in the B channel card. As in the A and K channels amplitude (which is proportional to the incident X-ray this event enable signal is processed and drives the B energy) to a pulse train containing a total number of input to the Identifying Matrix in Card 12 and also pulses proportional to the pulse amplitude. The input pulse to the ADC card charges a capacitor if no other B signal has been received in the previous 10/tsec (no resettable memory output) the B channel in the Height-to-Width Converter to the pulse peak linear gate is opened for 5.0/~sec allowing the delayed B voltage. The capacitor is allowed to discharge linearly so that its total time of discharge is proportional to the channel signal through to the ADC card. The C detector output signal feeding into the channel input pulse peak voltage. The output gate is allowed to C card is a spike with 40 nsec rise time. This signal is pass 1.6 MHz pulses during the condenser discharge fed to two series connected amplifiers. The outputs from time. Thus the output pulse train contains a total amplifiers 2 and 1 drive the C2 and C1 Threshold number of pulses proportional to the input pulse ampli-

X-RAY EXPERIMENT ELECTRONIC

tude. This output pulse train is fed to the ADC 7 bit scaler in the encoder (Card 13). Thus the total count in the ADC scaler is proportional to the incident X-ray energy. The accumulation of each count in the 7 bit ADC scaler requires 1/1.6 #see. Thus the maximum time of conversion is 127/1.6 = 79.3 #see. The system bistable in card 11 assures that subsequent X-ray events will not be processed during a conversion time. An X-ray event yielding output from card 10 (for A or K) or card 11 (for B) will pass through the OR gate and set the System Bistable. The System Bistable will remain in the set state until a reset signal is generated by the encoder. As will be explained later this reset signal will be generated after the data obtained from the processed X-ray event is transferred to the telemetry for transmission. As indicated earlier, with the System Bistable in the set state, subsequent Event Enable signals due to X-ray events will not be allowed through the Event Enable gate to the A, K or B channel cards to open any of the linear gates and thus the X-ray event will not be processed. However, these events are counted in Sealers II and II'. It will be noted that when the System Bistable is set, due to an X-ray event to be processed, a signal is sent to the ADC Bistable after a 2.5 psec delay. The ADC bistable is set at the rise time of the first 1.6 MHz oscillator pulse occurring after this delay. The setting of the ADC bistable starts the discharge of the capacitor in the sweep circuitry and opens the output gate allowing the 1.6 MHz oscillator pulses through. The 2.Spsec delay is provided to assure that the capacitor in the sweep circuitry has sufficient time to charge to the peak voltage of the pulse passed by the linear gate. The ADC bistable is set at the leading edge of a 1.6 MHz oscillator pulse to assure that the output pulse train starts at the same point in the pulse cycle. This eliminates jitter in the output pulse train. The ADC card also sends a data ready signal to the encoder (Card 13). This data ready signal indicates the data in the ADC 7 bit scaler is ready for transfer. For X-ray events received with an unbiased detector (no signal received within the previous 10/~sec) the data ready signal is generated at the end of the ADC pulse train. As indicated in fig. 4, the output gate generates an end of pulse train signal which goes through an OR gate to the encoder card as the data ready signal. For X-ray events received with a biased detector (zero ADC reading and no pulse train) the data ready signal is generated shortly after the ADC bistable is set. When the ADC bistable is set due to an X-ray event, it generates a signal which is delayed 2.5 #sec before

INSTRUMENTATION

19

being applied to an A N D inhibiting gate. If not inhibited, this signal is passed and goes through the OR gate to the encoder card as the data ready signal. The inhibit signal (3.0 #see) is generated only at the start of the pulse train out of the output gate. In this manner the data ready signal is also generated when an X-ray event occurs with no output from the output gate (biased detector). Card 12 is the identifying (ID) matrix card. The three output bits, fed to the encoder, as ID bits 1, 2, and 3 serve to identify the detector in which the processed X-ray event occurred. The code used for this identification is given in fig. 2. Referring to fig. 4, the A1, A2, A3, K1, K2, K3 or B Event Output is fed to the ID matrix in card 12. It will be recalled that only one of these outputs occurs during an X-ray event. When an X-ray event occurs, the output of the ID matrix sets the ID Bits 1, 2, and 3 to the appropriate states in accordance with the ID Code. The encoder (card 13) receives the data described above and arranges it into the format shown in fig. 2. The data in PCM form is then fed to the transmitter modulator. Fig. 5 is a system block diagram of the encoder. The encoder contains separate sealers for accumulating the ADC pulse train and the Scaler I, I', II and II' input pulses. The encoder count down clock is driven by the 1.6 MHz oscillator output from the ADC card. This count down clock generates the output shift register shift pulses, and at the appropriate times, the transfer, set and reset pulses. The 16-bit output shift register is continuously shifted at the end of each bit time. At the start of each word, the appropriate read out word is transferred (in parallel) into the 16-bit output shift register. An output buffer stage is provided to isolate the output during transfer time. The ADC word ready memory and logic gate assures that the ADC word will be transferred only after an event has been completely processed in the ADC card. An ADC reset signal is sent to the electronic system after the ADC transfer. Also unconditional set and reset signals are sent the electronics system during words I and 33 to assure that the system will not hang up. 6. Electronics system construction and power drain Each of the thirteen electronic cards measures 17.4 cm by 10.5 cm by 3.2 cm in height. The encoder card consists of 112 integrated low power D T L circuits (Fairchild 9040 series). Power drain for these units is 1.0 mW per gate and 4.0 mW per flip-flop. Total power drain of the encoder card is 480 mW. The integrated

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X-RAY EXPERIMENT ELECTRONIC INSTRUMENTATION

Fig. 6. Assembled encoder card.

circuits (flatpacks) are interconnected 8 to a 8.9 cm by 1.9 cm stick by welded interconnects and the sticks are mounted to the encoder card by a welded interconnect matrix. Fig. 6 shows the assembled encoder card. The weight of this card is approximately 300 g.

The remaining twelve cards consist primarily of discrete component circuitry. These are constructed of welded cordwood modules mounted on cards by means of a welded interconnect matrix. The average card weight is approximately 300 g. Total power drain

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Fig. 8. Compatible OR gate. of the twelve cards is 1.9 W. The shaper, delay, linear gate, linear gate driver, height to width converter, output gate, threshold detector spiker and associated amplifier circuits are similar to those developed previously for general satellite application and are described in detail2). It will be noted that wide use is made of the threshold detector and pulse generator circuits. The basic circuitry for these is described in 1,2). Some additions to this basic circuitry used in this system are described below.

7. Pulse generator with inhibit Fig. 7 is the schematic diagram of a pulse generator including provision for inhibit. This is similar to the pulse generator described1'2), except that the transformer T1 is placed in the emitter circuit of Q1 and Q2. A pulse applied to the primary ofT1 inhibits operation

8. Compatible OR gate Fig. 8 is the electrical schematic diagram of an O R gate which can be used in logic systems with the tunnel diode threshold detectors and pulse generators described above. With neither the A or B tunnel diodes in the high voltage state, the voltage at points 1 and 2 is approximately 0.5 V and therefore the output voltage is 0.0 V (due to the drop across CR3 and CR4). With either the A or B tunnel diodes in the high voltage state, the voltage at point 1 or 2 is approximately 1.0 V and therefore the output voltage is 0.5 V, sufficient to drive a succeeding tunnel diode stage. This type or O R gate was used throughout the system. The authors wish to express their appreciation to Dr. F. B. McDonald, Dr. E. A. Boldt and Dr. S. S. Holt of the Laboratory for Space Sciences at G S F C for the many helpful discussions and suggestions, to Mr. F. B. Birsa for his very able assistance in the testing, integration, and calibration of the system, and to Mr. C. R. Bayne of the Microelectronics and Applications Section of G S F C for his direction of the art work layouts and fabrication of the cordwood welded modules, integrated circuits and welded card assemblies.

References 1) C. A. Cancro and N. M. Garrahan, Proc. IEEE 56, no. 8 (1968) 1389. 2) C. A. Cancro and N. M. Garrahan, Nucl. Instr. and Meth. 70 (1969) 245. 3) E. A. Boldt, U. D. Desai and S. S. Holt, 2-20 keV spectrum of X-Rays from the Crab-Nebula and the diffuse background near galactic anticenter, NASA/Goddard publ. X-611-68-53 and Astroph. J. 156 (May, 1969).