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Yield and cost analysis of bubble devices on LPE garnets
Journal of Crystal Growth 27 (1974) 306-312 9 North-llolland Publishhtg Co.
YIELD AND COST ANALYSIS OF BUBBLE DEVICES ON LPE GARNETS R. B. CLOVER
Hewlett-Packard Laboratories, Palo Alto, California 94304, U.S.A. Received 18 March 1974 Existing data for wafer processing of magnetic bubble devices on LPE garnet substrates indicates that high production yields will be obtained for memory chips o f several thousand bits capacity. Conventional processing techniques can be used to obtain bit densities of 106-4 • 106 bits/in. 2 at a manufacturing cost o f under 50 millicents/bit. Several applications for bubble memories justify complete development o f the garnet film technology for transfer to production.
1. Introduction
The development of high quality liquid phase epitaxy (LPE) garnet films on Gd3GasO12 substrates is well documented in this special issue. We find that films with excellent thickness uniformity (_+270 over 9070 of the film area) and very few defects ( < 20 defects/in, z) can be grown routinely on 1.5 inch and 2 inch substrates using the horizontal rotation growth method~'2). Reproducibility of film properties from run to run is acceptable with today's methods for controlling the growth process 1'2). Our experience with fabricating bubble memory devices on LPE garnet wafers shows that device performance is not seriously affected by _+ 10 70 variations in garnet properties such as thickness, characteristic length and magnetization. Usually the properties of a series of films grown in sequence can be col~trolled within these limits. The reproducibility and low defect densities obtained for LPE garnet films result in little reduction in device yields compared to the effect on yield of defects in the thin film microcircuits fabricated on the garnet. 2. Thin film mierofabrication Bubble memory devices using the generally accepted field access approach 3,4) require a high resolution pattern of thin film magnetic permalloy to form bubble propagation channels; one or two thin film conductor metallization patterns overlaying the permalloy to form current actuated control circuits; and dielectric spacing layers, such as SiO 2 or AIzO 3. 306
In general there are a relatively large number of lam size permalloy elements in a periodic array and a relatively small number of lam size conductor loops. The loops are connected by wide segments of conductor that fan out into pads for lead attachment. For imaging the thin film patterns using photoresist, one can choose from among three basic approaches: (1) Conventional contact optical photolithography using masks with not worse than 2 lam resolution. This is adequate for bubbles larger than 6 lam and gives up to about 10 6 bits/in. 2 on a wafer. Alignment tolerances between mask levels are greater than ___1 pm and alignment yields are high. (In this paper, metric and English units are mixed, according to present common usage, for feature size and areal densities, respectively.) (2) Contact or projection optical lithography using masks with 1 lam resolution. This approach would allow work with 3 lam bubbles and could give about 4 x 10 6 bits/in. 2. However mask alignment at a tolerance of _+0.5 lam is difficult. To avoid this, single high resolution mask bubble circuit designs 5'6) can be.used that require only gross alignment of the high resolution mask with one or more low resolution masks. This reduces the flexibility in device design and may result in high power requirements for some circuit functionsS'6). (3) Electron beam microfabrication with less than 0.5 pm resolutionT). This again should make use of single high resolution mask circuit designs and potentially more than 10 7 bits/in, z can be realized. In the next section, we give results of our experience
307
YIELD AND COST ANALYSIS OF BUBBLE DEVICES ON LPE GARNETS
using the first approach for 6 lam bubble circuits. The data on chip yields show how to improve yields for 6 lam circuits, but tells us little about what to expect for the above two more advanced processing schemes. 3. Bubble device yields To study the causes of thin film processing defects, the distribution ofdefect sizes and their effect on bubble device performance, we have processed a number of arrays of bubble chips for 6 lam diameter bubbles, with a chip capacity of 1152 bits, a propagation period of 24 lam and an active area of about 0.0011 in. 2. All thin film metals are rf sputter-deposited and rf sputteretched using positive photoresist. Typical permalloy linewidth is 3 lam and gap width between permalloy elements is 21am. The LPE garnet films used were (SmxYa_x)(F%Gas_r)O12 1,2) subjected to ion implantation s) of 2 x l014 Ne/cm 2. We used films grown in both Pb-based and Ba-based fluxes9). In this section, we describe the failure analysis for bubble chips after successful wafer fabrication. We will not consider catastrophic causes of loss, such as wafer breakage and gross deposition/etching errors, which are typically less than 5 ~o. We note that wafers can be recycled to minimize these losses if measurement of LPE garnet properties and deposited film thicknesses are carried out at intermediate processing stages. Also, photoresist pattern quality and alignment with previous mask levels should be monitored before etching a layer since the resist step can be easily repeated. We have also found that laser scribing allows breaking of garnet wafers into separate chips with virtually no loss. We have successfully used an Electroglas N d Y A G system for scribing garnet using various values of laser power and table speed. Chips were tested by measuring the upper and lower limits of magnetic bias field (H u and HI) for reliable bubble propagation at 100 kHz. Chips with poor bias field margins were studied under a polarizing microscope to find the causes of failure. A useful technique is propagation of bubbles around the device at about 20 Hz allowing one to look for the location where propagation is disrupted by a defect. Usually, a visible imperfection in either the garnet film or the permalloy patterns can be observed and the details of the failure mode can be recorded. In many cases, defects of less than 10 I~m in size do
not affect device performance as long as they are not directly in the path of the bubble stream. Bubble streams on the permalloy pattern are separated by about four times the bubble diameter and interactions between defects and bubbles are usually short range, with negligible effect for defects more than a bubble diameter away from a bubble. Defects of the above type include small permalloy spots, fiat-bottom garnet etch pits 9) and small scratches in the garnet. Also, we have found that garnet mesa defects z~ in which there is an increase in garnet film thickness of usually less than 0.2 lam, almost never cause significant reductions in device margins. Defects that do cause failures include garnet scratches and pits directly intersecting the bubble propagation paths, although bubbles sometimes pass right through the pits with negligible interaction. Other failures are caused by permailoy defects that are under 5 ~tna in size and that intersect the propagation paths and by permalloy defects over 5 Itm in size that do not necessarily intersect the paths. TABLE.1 Bubble chip failures Cause Garnet defects
Unidentified Permalloy defects < 5 gm Permalloy defects > 5 ltm
Failures (%) 1.3%
6.0% 7.0% 16.0%
Table 1 shows the distribution of causes of device failure on a sample of 244 bubble chips fabricated on two I inch and two 1.5 inch garnet wafers. Figs. 1 and 2 show the spread in bias field margins on the two 1.5 inch wafers. For seven wafers processed and a total o f 342 chips, the spread in yields for acceptable bubble propagation ( > 10~o bias margin-at 100 kHz for any of the chips; lower margin within 3 Oe of the lowest observed for the chips on each wafer) was 63-77 ~o, with an average o f about 70 Yo. Note that over half of the failures are caused by large permalloy defects and almost none are caused by garnet defects. In almost all cases, the defects are excess permalloy rather than missing permalloy. In addition, only one defect was identified as a mask defect that appears on every wafer. Fig. 3 shows in more detail the size distribution of failure causing permalloy
308
R.B. CLOVER i
i
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~r
20-
FHu
H u _-,.
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50
60
80
90
I00
BIAS FIELD MARGINS (Oe)
Fig. 1. Distribution o f upper (H,) and l o w (Ht) bias field m a r g i n s f o r 1.15 K chips processed on two 1.5 inch garnet wafers. The LPE garnet films were 4.1 lain and 7.5 lain thick for the 53 Oe and 91 Oe chips, respectively. 30
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o H = 530e OH = 910e
25"
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/
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/
t..)
t~ 15" O
=
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Fig. 2.
~
o
I 5
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I I.. I0 15 BIAS FIELD HARGIN (Hu-Hz)/H (g)
I 20
25
Distribution of percentage bias field margins for 1.15 K chips on the two wafers of fig. i.
defects. A large number are in the range of 10-100 lain. Many of the large permalloy spots are fiat and uniform in thickness with a smooth, often nearly elliptical boundary. Others are roughly formed with many
small spots near one or two large permalloy particles. We identify the former large defects with smooth extra islands of positive photoresist. These spots do not appear to be due to dust particles; the~, may be due
Y I E L D A N D C O S T A N A L Y S I S OF B U B B L E D E V I C E S O N L P E G A R N E T S
to extra deposits that form on the wafer when the resist layer is being developed and washed. We identify the latter large defects with gelatinized resist particles that are applied to the wafer during spinning. These can be removed by proper filtering and/or centrifuging of the resist periodically. By improving the resist processing of the permalloy pattern to reduce the number of large resist defects, it appears that chip failures can be reduced by at least a factor of two. We base this on the knowledge that resist defects > 10 pm in size are rare in high yield semiconductor wafer processing tt). Resist defects of the above types also lead to failure of thin film conductors on the chips. However, the area of the high resolution sections of the conductors for kilobit size chips is typically less than 2 ~o of the high resolution permalloy active area. Thus, the reduction in yield from conductor defects is negligible. We conclude that visual observation of chip defects and their properties provides important feedback for improvement of wafer fabrication and that the integrity of the permalloy pattern on the wafer determines the yield, for all practical purposes.
o(.Xo) = fo
Y = e -ap,
(1)
where D = failure causing defects/area and A = chip active area. A model commonly used by semiconductor LSI groupsassumes a triangular distribution of defects to account for clustering, which gives ~2)
z.
(2)
This is identical with the Poisson result for small AD, but predicts a higher yield for large AD. The area A is simply the number of active device cells times the area per cell. Generally, the LSI industry is
p(x, xo) d(x)dx,
(3)
where x is the defect size, d(x) is the density of defects with size between x and x+dx and p(x,Xo) is the probability of device failure for given defect of size x. As the device cell size Xo is reduced, p(X,Xo) will increase for x < x 0 and will be approximately unity for x > Xo. Thus OD/Oxo is expected to be negative. For the Poisson distribution the number of usable bits/wafer is Wafer area
B
exp [ - N x ~ D(xo)],
(4)
and more bits per wafer are obtained for a reduction in Xo as long as -
One of the purposes of obtaining yield data on arrays of 1 K chips is to predict the yield of larger chips. For this, it is important to know if the distribution of wafer defects is random or if clustering of defects exists. In our case, there appears to be some clustering, but our sample of seven wafers is too small to warrant a statistical analysis of this. For random, independent, distinguishable defects, a Poisson model should be valid with yield
Y = [(1--e-a~
trying to develop higher resolution processes so the cell size Xo can be reduced and more devices can be packed into a given area, as in approaches (2) and (3) for bubble device processing. For this to pay off, more good bits per wafer should be obtained by the change in dimensions for a given number N of bits/chip. This will depen on how D changes for the higher resolution patterns. The quantity D may be represented by
aD
4. Yield models
309
- -
OXo
2 + 2x2ND(xo) <
lVx~
(5)
The point is, higher resolution may not be warranted for some LSI technologies and some processing procedures. The distribution of defects in size and their effect on circuit performance must be studied in detail in order to reasonably predict the outcome of an 'advance' in circuit processing. In particular, for 6 I-tm bubbles fig. 3 shows a plot ofp(x, xo)d(x) for Xo = 24 tam. We see a trend toward higher values for small x and we anticipate further increases if Xo is reduced. However, from the data of fig. 3 we cannot predict D(xo) or yields for 3 pm bubble devices using optical photolithography or for smaller bubbles using electron beam circuit fabrication. The processes required for the small bubbles will have their own characteristic defects and functional dependencies for p(x,xo) and d(x). Returning to 6 pm bubbles, we can approximately predict the yields for larger capacity chips than those tested. From 70 ~o yield at 1.15 K bits, we calculate D = 350/in. z and about 10~o yield at 8 K bits from equation ( 2 ) . Workers at Bell Telephone Laboratories also have
310
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i
i
30
-20 IE
25"
-15"-" ~"~ 20-
~7
% x ,._i M
x
,.'F is-
10-5
I
1
Fig, 3.
I
2
1
4
I
I
I
6 8 I0 DEFECT SIZE (~m)
I
20
I
40
--T""~ 60
0
80 I00
Total chip ~ilures versus de~ct size for a sample of 244 1.15 K chips. Also, the piecewise continuous differential,
p(x, xo) d(x), o f the number of ~ilure causing de~cts lsee eq. (3)].
experience with processing 6 lam bubbles on 1.5 inch garnet wafers13). They find about 1 6 ~ yield for a 16 K chip and Xo = 28 lam. These data used in eq. (2) give D = 120/in. 2 for their chips. Most of these .defects are permalloy imperfections 13) and thus we see that about a factor of three difference in D exists for the HP and BTL processes. We can compare this with commonly observed values of D of typically 100-1000/in. z for a 4 to 5 mask level process for semiconductor devices or, crudely, for one mask level 11).D ,-~ 20-200/in. z. One might expect that refinements in resist processing will result in bubble devices with D < 50/in. 2 since yields are determined primarily by the permalloy mask step. For the expected range of D, cost versus size tradeoffs are considered in the following section.
We can model the cost tradeoffs for 6 lam bubble circuits by assuming that chip complexity is independent of chip size N; that is, the number o f control functions and the number of pads/chip remains constant. For this case, we estimate a constant chip overhead cost o f about S2/chip for testing, mounting and bonding using automated techniques. We assume that the effective bit density is l 0 6 bits/in.Z; we ignore the 2-5 Yo loss in area for pads and dicing and loss due to catastrophic processing failures; and we assume a wafer processing cost of $15/in. 2. We will use the Poisson distribution for the yield, as this gives the worst case results. The manufacturing cost in cents per bit is then given by TABLE 2 Wafer processing costs
5. Cost analysis for bubble processing
Item
Table 2 shows an estimated manufacturing cost breakdown for the various steps in bubble wafer processing in volume production. The cost per usable square inch of about S 15 is relatively high compared to semiconductor LSI, but the cost per bit is predicted to be lower.
Substrates (1.5-2 inch) LPE film Ion implant Thin film microprocessing Wafer test, dice Total wafer cost Cost/in. 2
Cost $30-60 $ 4-8 S0.5-1 $ 7-15 $ 2-5 547-95 ~ $15
% 68 9 1 17 5 100
YIELD AND COST ANALYSIS OF BUBBLE DEVICES ON LPE GARNETS
Considering the low chip cost, one chip bubble memories of up to 50 kbits capacity are attractive for applications in which low power and nonvolatile memory are important. For small bubble memories the cost of packaging and control electronics far outweighs the chip cost. A small memory system design must use the minimum possible number of electronic circuit components. Bubble memories are compatible with this in that the simplest chip organizations require as few as four I/O lines, three for a differential detector and one write/erase line.
O.SO,
D = 300/In 2
u v 0.10-
D = 1201in 2
o
311
<-
6. Conclusion
t,. <
Fig. 4. Cost C versus chip size for three values o f the defect density D.
The development of higher resolution devices and/or the use of cheaper bubble material, such as the amorphous alloys 7) are important to the future growth of bubble technology, but we submit that it is equally important to push for the development and introduction of a product as early as possible. We conclude that the transfer to production of 6 pm bubble technology on garnet appears justified on the basis of cost/bit and the practicality of fabrication techniques.
C = 200/N+ 1500 x 10 - 6 exp [DN x 1 0 - 6 ] .
Acknowledgement
D = 50/in 2
.01 I 0
I
10
I
20
I
3D
I
40
I
50
I
60
CHIP SIZE (K BITS)
(6)
Fig. 4 shows C for 50, 120 and 300 defects/in. 2. For this spread in defects density, the minimum cost is in the range of 0.01-0.04cent/bit. This compare favorably with the manufacturing costs of various types of semiconductor memory chips, which are about 0.1 cent/bit for ROM, 0.2cent/bit for RAM and (estimated) 0.02-0.05 cent/bit for CCD (ChargeCoupled Device) 11). To the cost of the bubble chips must be added the cost of additional memory electronics, hardware and packaging, which will depend on the specific application. For multimegabit bubble memoriest4), it appears that memory costs of less than $500/Mbit (0.05 cent/ bit) can be realized with 6 lam bubbles. At this cost, bubbles are attractive as a fixed head disc replacement to achieve higher reliability at about the same cost/bit. A 1-10 Mbit bubble memory is also a candidate as a high performance peripheral for desk calculators or minicomputers to fill the cost/performance gap between digital cassettes and moving head discs. For these applications, CCD memories ~s) are also contenders, with CCD offering higher speed and bubbles offering nonvolatile storage.
The garnet films used in this study were prepared by R. Burmeister, R. Hiskes, F. Perlaki and L. Small and the thin film microcircuit fabrication was carried out by W. Ebert with the advice of F. Ura and S. Muto. R. Baugh, C. Bradshaw, W. Lacey, R. Waites and H. Wiersma contributed to the design of the bubble chips and the construction of test equipment. A number of helpful suggestions and critical reading of the manuscript were contributed by L. Cutler. The author gratefully appreciates the indispensable efforts of the above associates. References 1) R. Hiskes, J. Crystal Growth 27 (1974) 287. 2) B. S. Hewitt et al., IEEE Trans. Magnetics MAG-9 (1973) 366. 3) A. J. Perneski, 1EEE Trans. Magnetics MAG-5 (1969) 554. 4) P. I. Bonyhard et al., IEEE Trans. Magnetics MAG-9 (1973) 433. 5) A. H. Bobeck et ah, IEEE Trans. Magnetics MAG-9 (1973) 474. 6) T.J. Nelson, 19th Annual Conf. on Magnetics and Magnetic Materials, Boston (1973), to be published in the AIP Conf. Proc. 7) M. H. Kryder et al., presented at the 1974 lntermag. Conference, Toronto.
312
R. B. CLOVER
8) R. Wolfe et al., Appl. Phys. Letters 22 (1973) 683. 9) R. Hiskes, T. L. Felmlee and R. A. Burmeister, J. Electron Mater. 1 (1972) 458. 10) E. A. Giess, J. D. Kuptsis and E. A. D. White, J. Crystal Growth 16 (1972) 36. II) Private discussions with HP semiconductor processing personnel.
12) B.T. Murphy, Proc. IEEE 52 (1964) 1537. 13) A. J. Pcrneski et al., presented at the 1974 lntermag. Conference, Toronto. 14) P. C. Michaelis and P. 1. Bonyhard, IEEE Trans. Magnetics MAG-9 (1973) 436. 15) W. Anacker, IEEE Trans. Magnetics MAG-7 (1971) 410.
YIELD AND COST ANALYSIS OF BUBBLE DEVICES ON LPE GARNETS R. B. CLOVER
Hewlett-Packard Laboratories, Palo Alto, California 94304, U.S.A. Received 18 March 1974 Existing data for wafer processing of magnetic bubble devices on LPE garnet substrates indicates that high production yields will be obtained for memory chips o f several thousand bits capacity. Conventional processing techniques can be used to obtain bit densities of 106-4 • 106 bits/in. 2 at a manufacturing cost o f under 50 millicents/bit. Several applications for bubble memories justify complete development o f the garnet film technology for transfer to production.
1. Introduction
The development of high quality liquid phase epitaxy (LPE) garnet films on Gd3GasO12 substrates is well documented in this special issue. We find that films with excellent thickness uniformity (_+270 over 9070 of the film area) and very few defects ( < 20 defects/in, z) can be grown routinely on 1.5 inch and 2 inch substrates using the horizontal rotation growth method~'2). Reproducibility of film properties from run to run is acceptable with today's methods for controlling the growth process 1'2). Our experience with fabricating bubble memory devices on LPE garnet wafers shows that device performance is not seriously affected by _+ 10 70 variations in garnet properties such as thickness, characteristic length and magnetization. Usually the properties of a series of films grown in sequence can be col~trolled within these limits. The reproducibility and low defect densities obtained for LPE garnet films result in little reduction in device yields compared to the effect on yield of defects in the thin film microcircuits fabricated on the garnet. 2. Thin film mierofabrication Bubble memory devices using the generally accepted field access approach 3,4) require a high resolution pattern of thin film magnetic permalloy to form bubble propagation channels; one or two thin film conductor metallization patterns overlaying the permalloy to form current actuated control circuits; and dielectric spacing layers, such as SiO 2 or AIzO 3. 306
In general there are a relatively large number of lam size permalloy elements in a periodic array and a relatively small number of lam size conductor loops. The loops are connected by wide segments of conductor that fan out into pads for lead attachment. For imaging the thin film patterns using photoresist, one can choose from among three basic approaches: (1) Conventional contact optical photolithography using masks with not worse than 2 lam resolution. This is adequate for bubbles larger than 6 lam and gives up to about 10 6 bits/in. 2 on a wafer. Alignment tolerances between mask levels are greater than ___1 pm and alignment yields are high. (In this paper, metric and English units are mixed, according to present common usage, for feature size and areal densities, respectively.) (2) Contact or projection optical lithography using masks with 1 lam resolution. This approach would allow work with 3 lam bubbles and could give about 4 x 10 6 bits/in. 2. However mask alignment at a tolerance of _+0.5 lam is difficult. To avoid this, single high resolution mask bubble circuit designs 5'6) can be.used that require only gross alignment of the high resolution mask with one or more low resolution masks. This reduces the flexibility in device design and may result in high power requirements for some circuit functionsS'6). (3) Electron beam microfabrication with less than 0.5 pm resolutionT). This again should make use of single high resolution mask circuit designs and potentially more than 10 7 bits/in, z can be realized. In the next section, we give results of our experience
307
YIELD AND COST ANALYSIS OF BUBBLE DEVICES ON LPE GARNETS
using the first approach for 6 lam bubble circuits. The data on chip yields show how to improve yields for 6 lam circuits, but tells us little about what to expect for the above two more advanced processing schemes. 3. Bubble device yields To study the causes of thin film processing defects, the distribution ofdefect sizes and their effect on bubble device performance, we have processed a number of arrays of bubble chips for 6 lam diameter bubbles, with a chip capacity of 1152 bits, a propagation period of 24 lam and an active area of about 0.0011 in. 2. All thin film metals are rf sputter-deposited and rf sputteretched using positive photoresist. Typical permalloy linewidth is 3 lam and gap width between permalloy elements is 21am. The LPE garnet films used were (SmxYa_x)(F%Gas_r)O12 1,2) subjected to ion implantation s) of 2 x l014 Ne/cm 2. We used films grown in both Pb-based and Ba-based fluxes9). In this section, we describe the failure analysis for bubble chips after successful wafer fabrication. We will not consider catastrophic causes of loss, such as wafer breakage and gross deposition/etching errors, which are typically less than 5 ~o. We note that wafers can be recycled to minimize these losses if measurement of LPE garnet properties and deposited film thicknesses are carried out at intermediate processing stages. Also, photoresist pattern quality and alignment with previous mask levels should be monitored before etching a layer since the resist step can be easily repeated. We have also found that laser scribing allows breaking of garnet wafers into separate chips with virtually no loss. We have successfully used an Electroglas N d Y A G system for scribing garnet using various values of laser power and table speed. Chips were tested by measuring the upper and lower limits of magnetic bias field (H u and HI) for reliable bubble propagation at 100 kHz. Chips with poor bias field margins were studied under a polarizing microscope to find the causes of failure. A useful technique is propagation of bubbles around the device at about 20 Hz allowing one to look for the location where propagation is disrupted by a defect. Usually, a visible imperfection in either the garnet film or the permalloy patterns can be observed and the details of the failure mode can be recorded. In many cases, defects of less than 10 I~m in size do
not affect device performance as long as they are not directly in the path of the bubble stream. Bubble streams on the permalloy pattern are separated by about four times the bubble diameter and interactions between defects and bubbles are usually short range, with negligible effect for defects more than a bubble diameter away from a bubble. Defects of the above type include small permalloy spots, fiat-bottom garnet etch pits 9) and small scratches in the garnet. Also, we have found that garnet mesa defects z~ in which there is an increase in garnet film thickness of usually less than 0.2 lam, almost never cause significant reductions in device margins. Defects that do cause failures include garnet scratches and pits directly intersecting the bubble propagation paths, although bubbles sometimes pass right through the pits with negligible interaction. Other failures are caused by permailoy defects that are under 5 ~tna in size and that intersect the propagation paths and by permalloy defects over 5 Itm in size that do not necessarily intersect the paths. TABLE.1 Bubble chip failures Cause Garnet defects
Unidentified Permalloy defects < 5 gm Permalloy defects > 5 ltm
Failures (%) 1.3%
6.0% 7.0% 16.0%
Table 1 shows the distribution of causes of device failure on a sample of 244 bubble chips fabricated on two I inch and two 1.5 inch garnet wafers. Figs. 1 and 2 show the spread in bias field margins on the two 1.5 inch wafers. For seven wafers processed and a total o f 342 chips, the spread in yields for acceptable bubble propagation ( > 10~o bias margin-at 100 kHz for any of the chips; lower margin within 3 Oe of the lowest observed for the chips on each wafer) was 63-77 ~o, with an average o f about 70 Yo. Note that over half of the failures are caused by large permalloy defects and almost none are caused by garnet defects. In almost all cases, the defects are excess permalloy rather than missing permalloy. In addition, only one defect was identified as a mask defect that appears on every wafer. Fig. 3 shows in more detail the size distribution of failure causing permalloy
308
R.B. CLOVER i
i
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30-
P
cJ C~
c-~
~r
20-
FHu
H u _-,.
Ld C~
lO-
I
40
I--'"
50
60
80
90
I00
BIAS FIELD MARGINS (Oe)
Fig. 1. Distribution o f upper (H,) and l o w (Ht) bias field m a r g i n s f o r 1.15 K chips processed on two 1.5 inch garnet wafers. The LPE garnet films were 4.1 lain and 7.5 lain thick for the 53 Oe and 91 Oe chips, respectively. 30
I
I
o H = 530e OH = 910e
25"
I
/
I
20-
/
t..)
t~ 15" O
=
uJ
lO-
n 0
Fig. 2.
~
o
I 5
n
I I.. I0 15 BIAS FIELD HARGIN (Hu-Hz)/H (g)
I 20
25
Distribution of percentage bias field margins for 1.15 K chips on the two wafers of fig. i.
defects. A large number are in the range of 10-100 lain. Many of the large permalloy spots are fiat and uniform in thickness with a smooth, often nearly elliptical boundary. Others are roughly formed with many
small spots near one or two large permalloy particles. We identify the former large defects with smooth extra islands of positive photoresist. These spots do not appear to be due to dust particles; the~, may be due
Y I E L D A N D C O S T A N A L Y S I S OF B U B B L E D E V I C E S O N L P E G A R N E T S
to extra deposits that form on the wafer when the resist layer is being developed and washed. We identify the latter large defects with gelatinized resist particles that are applied to the wafer during spinning. These can be removed by proper filtering and/or centrifuging of the resist periodically. By improving the resist processing of the permalloy pattern to reduce the number of large resist defects, it appears that chip failures can be reduced by at least a factor of two. We base this on the knowledge that resist defects > 10 pm in size are rare in high yield semiconductor wafer processing tt). Resist defects of the above types also lead to failure of thin film conductors on the chips. However, the area of the high resolution sections of the conductors for kilobit size chips is typically less than 2 ~o of the high resolution permalloy active area. Thus, the reduction in yield from conductor defects is negligible. We conclude that visual observation of chip defects and their properties provides important feedback for improvement of wafer fabrication and that the integrity of the permalloy pattern on the wafer determines the yield, for all practical purposes.
o(.Xo) = fo
Y = e -ap,
(1)
where D = failure causing defects/area and A = chip active area. A model commonly used by semiconductor LSI groupsassumes a triangular distribution of defects to account for clustering, which gives ~2)
z.
(2)
This is identical with the Poisson result for small AD, but predicts a higher yield for large AD. The area A is simply the number of active device cells times the area per cell. Generally, the LSI industry is
p(x, xo) d(x)dx,
(3)
where x is the defect size, d(x) is the density of defects with size between x and x+dx and p(x,Xo) is the probability of device failure for given defect of size x. As the device cell size Xo is reduced, p(X,Xo) will increase for x < x 0 and will be approximately unity for x > Xo. Thus OD/Oxo is expected to be negative. For the Poisson distribution the number of usable bits/wafer is Wafer area
B
exp [ - N x ~ D(xo)],
(4)
and more bits per wafer are obtained for a reduction in Xo as long as -
One of the purposes of obtaining yield data on arrays of 1 K chips is to predict the yield of larger chips. For this, it is important to know if the distribution of wafer defects is random or if clustering of defects exists. In our case, there appears to be some clustering, but our sample of seven wafers is too small to warrant a statistical analysis of this. For random, independent, distinguishable defects, a Poisson model should be valid with yield
Y = [(1--e-a~
trying to develop higher resolution processes so the cell size Xo can be reduced and more devices can be packed into a given area, as in approaches (2) and (3) for bubble device processing. For this to pay off, more good bits per wafer should be obtained by the change in dimensions for a given number N of bits/chip. This will depen on how D changes for the higher resolution patterns. The quantity D may be represented by
aD
4. Yield models
309
- -
OXo
2 + 2x2ND(xo) <
lVx~
(5)
The point is, higher resolution may not be warranted for some LSI technologies and some processing procedures. The distribution of defects in size and their effect on circuit performance must be studied in detail in order to reasonably predict the outcome of an 'advance' in circuit processing. In particular, for 6 I-tm bubbles fig. 3 shows a plot ofp(x, xo)d(x) for Xo = 24 tam. We see a trend toward higher values for small x and we anticipate further increases if Xo is reduced. However, from the data of fig. 3 we cannot predict D(xo) or yields for 3 pm bubble devices using optical photolithography or for smaller bubbles using electron beam circuit fabrication. The processes required for the small bubbles will have their own characteristic defects and functional dependencies for p(x,xo) and d(x). Returning to 6 pm bubbles, we can approximately predict the yields for larger capacity chips than those tested. From 70 ~o yield at 1.15 K bits, we calculate D = 350/in. z and about 10~o yield at 8 K bits from equation ( 2 ) . Workers at Bell Telephone Laboratories also have
310
R . n . CLOVER i
i
i
i
30
-20 IE
25"
-15"-" ~"~ 20-
~7
% x ,._i M
x
,.'F is-
10-5
I
1
Fig, 3.
I
2
1
4
I
I
I
6 8 I0 DEFECT SIZE (~m)
I
20
I
40
--T""~ 60
0
80 I00
Total chip ~ilures versus de~ct size for a sample of 244 1.15 K chips. Also, the piecewise continuous differential,
p(x, xo) d(x), o f the number of ~ilure causing de~cts lsee eq. (3)].
experience with processing 6 lam bubbles on 1.5 inch garnet wafers13). They find about 1 6 ~ yield for a 16 K chip and Xo = 28 lam. These data used in eq. (2) give D = 120/in. 2 for their chips. Most of these .defects are permalloy imperfections 13) and thus we see that about a factor of three difference in D exists for the HP and BTL processes. We can compare this with commonly observed values of D of typically 100-1000/in. z for a 4 to 5 mask level process for semiconductor devices or, crudely, for one mask level 11).D ,-~ 20-200/in. z. One might expect that refinements in resist processing will result in bubble devices with D < 50/in. 2 since yields are determined primarily by the permalloy mask step. For the expected range of D, cost versus size tradeoffs are considered in the following section.
We can model the cost tradeoffs for 6 lam bubble circuits by assuming that chip complexity is independent of chip size N; that is, the number o f control functions and the number of pads/chip remains constant. For this case, we estimate a constant chip overhead cost o f about S2/chip for testing, mounting and bonding using automated techniques. We assume that the effective bit density is l 0 6 bits/in.Z; we ignore the 2-5 Yo loss in area for pads and dicing and loss due to catastrophic processing failures; and we assume a wafer processing cost of $15/in. 2. We will use the Poisson distribution for the yield, as this gives the worst case results. The manufacturing cost in cents per bit is then given by TABLE 2 Wafer processing costs
5. Cost analysis for bubble processing
Item
Table 2 shows an estimated manufacturing cost breakdown for the various steps in bubble wafer processing in volume production. The cost per usable square inch of about S 15 is relatively high compared to semiconductor LSI, but the cost per bit is predicted to be lower.
Substrates (1.5-2 inch) LPE film Ion implant Thin film microprocessing Wafer test, dice Total wafer cost Cost/in. 2
Cost $30-60 $ 4-8 S0.5-1 $ 7-15 $ 2-5 547-95 ~ $15
% 68 9 1 17 5 100
YIELD AND COST ANALYSIS OF BUBBLE DEVICES ON LPE GARNETS
Considering the low chip cost, one chip bubble memories of up to 50 kbits capacity are attractive for applications in which low power and nonvolatile memory are important. For small bubble memories the cost of packaging and control electronics far outweighs the chip cost. A small memory system design must use the minimum possible number of electronic circuit components. Bubble memories are compatible with this in that the simplest chip organizations require as few as four I/O lines, three for a differential detector and one write/erase line.
O.SO,
D = 300/In 2
u v 0.10-
D = 1201in 2
o
311
<-
6. Conclusion
t,. <
Fig. 4. Cost C versus chip size for three values o f the defect density D.
The development of higher resolution devices and/or the use of cheaper bubble material, such as the amorphous alloys 7) are important to the future growth of bubble technology, but we submit that it is equally important to push for the development and introduction of a product as early as possible. We conclude that the transfer to production of 6 pm bubble technology on garnet appears justified on the basis of cost/bit and the practicality of fabrication techniques.
C = 200/N+ 1500 x 10 - 6 exp [DN x 1 0 - 6 ] .
Acknowledgement
D = 50/in 2
.01 I 0
I
10
I
20
I
3D
I
40
I
50
I
60
CHIP SIZE (K BITS)
(6)
Fig. 4 shows C for 50, 120 and 300 defects/in. 2. For this spread in defects density, the minimum cost is in the range of 0.01-0.04cent/bit. This compare favorably with the manufacturing costs of various types of semiconductor memory chips, which are about 0.1 cent/bit for ROM, 0.2cent/bit for RAM and (estimated) 0.02-0.05 cent/bit for CCD (ChargeCoupled Device) 11). To the cost of the bubble chips must be added the cost of additional memory electronics, hardware and packaging, which will depend on the specific application. For multimegabit bubble memoriest4), it appears that memory costs of less than $500/Mbit (0.05 cent/ bit) can be realized with 6 lam bubbles. At this cost, bubbles are attractive as a fixed head disc replacement to achieve higher reliability at about the same cost/bit. A 1-10 Mbit bubble memory is also a candidate as a high performance peripheral for desk calculators or minicomputers to fill the cost/performance gap between digital cassettes and moving head discs. For these applications, CCD memories ~s) are also contenders, with CCD offering higher speed and bubbles offering nonvolatile storage.
The garnet films used in this study were prepared by R. Burmeister, R. Hiskes, F. Perlaki and L. Small and the thin film microcircuit fabrication was carried out by W. Ebert with the advice of F. Ura and S. Muto. R. Baugh, C. Bradshaw, W. Lacey, R. Waites and H. Wiersma contributed to the design of the bubble chips and the construction of test equipment. A number of helpful suggestions and critical reading of the manuscript were contributed by L. Cutler. The author gratefully appreciates the indispensable efforts of the above associates. References 1) R. Hiskes, J. Crystal Growth 27 (1974) 287. 2) B. S. Hewitt et al., IEEE Trans. Magnetics MAG-9 (1973) 366. 3) A. J. Perneski, 1EEE Trans. Magnetics MAG-5 (1969) 554. 4) P. I. Bonyhard et al., IEEE Trans. Magnetics MAG-9 (1973) 433. 5) A. H. Bobeck et ah, IEEE Trans. Magnetics MAG-9 (1973) 474. 6) T.J. Nelson, 19th Annual Conf. on Magnetics and Magnetic Materials, Boston (1973), to be published in the AIP Conf. Proc. 7) M. H. Kryder et al., presented at the 1974 lntermag. Conference, Toronto.
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R. B. CLOVER
8) R. Wolfe et al., Appl. Phys. Letters 22 (1973) 683. 9) R. Hiskes, T. L. Felmlee and R. A. Burmeister, J. Electron Mater. 1 (1972) 458. 10) E. A. Giess, J. D. Kuptsis and E. A. D. White, J. Crystal Growth 16 (1972) 36. II) Private discussions with HP semiconductor processing personnel.
12) B.T. Murphy, Proc. IEEE 52 (1964) 1537. 13) A. J. Pcrneski et al., presented at the 1974 lntermag. Conference, Toronto. 14) P. C. Michaelis and P. 1. Bonyhard, IEEE Trans. Magnetics MAG-9 (1973) 436. 15) W. Anacker, IEEE Trans. Magnetics MAG-7 (1971) 410.