ZnO as a dielectric for organic thin film transistor-based non-volatile memory

Microelectronic Engineering 86 (2009) 2127–2131

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ZnO as a dielectric for organic thin film transistor-based non-volatile memory N. Tjitra Salim a, K.C. Aw b,*, W. Gao a, Z.W. Li a, B. Wright c a b c

Department of Chemical and Materials Engineering, The University of Auckland, 20 Symond Street, Auckland 1001, New Zealand Department of Mechanical Engineering, The University of Auckland, 20 Symond Street, Auckland 1001, New Zealand Department of Chemistry, The University of Auckland, 23 Symond Street, Auckland 1001, New Zealand

a r t i c l e

i n f o

Article history: Received 13 October 2008 Received in revised form 15 January 2009 Accepted 20 February 2009 Available online 9 March 2009 Keywords: ZnO OTFT Non-volatile memory Pentacene

a b s t r a c t This paper demonstrates the novel application of d.c. sputtered zinc oxide (ZnO) as a charge trapping dielectric material for the application of an organic thin film transistor (OTFT) based non-volatile memory (NVM). The motivation of using ZnO as a dielectric is due to its chemical stability and optical transparency, enabling future development of transparent electronic devices. Unbalanced magnetron d.c. sputtering with Ar:O2 ratio of 80:20 was used to obtained a ZnO dielectric of 50 nm thick. The ZnO has an optical band gap of 3.23 eV, resistivity and k-value of 5  107 X-cm and 50, respectively. The ZnO sandwiched between two layers of low-k methyl-silsesquioxane (MSQ) sol–gel dielectric creates a triple layer dielectric structure for charge storage. A solution-processable pentacene, 13,6-N-Sulfinylacetamodipentacene, was used as an active layer of an OTFT-NVM. It has been successfully demonstrated that this OTFT-NVM can be electrically programmed and erased at a low voltage. Ó 2009 Elsevier B.V. All rights reserved.

1. Introduction Organic electronic has been widely studied due to its potentially novel applications, including non-volatile memory organic thin film transistor (OTFT) [1–7]. It possesses features that are not acquired by its inorganic counterparts, such as mechanical flexibility, low processing cost, biochemical sensitivity and large area products. It is well known that the interface between the organic semiconductor and its dielectric is important to the OTFT performance. An OTFT can be extended from a transistor to memory elements by smart architecture of the dielectrics to create floating gate-like effects [8,9]. Some studies have shown novel arrangement of dielectrics that had potential as charge storage system, by using poly(4-methylstyrene) and polyvinyl alcohol (PVA) as the charge trapping dielectric material which can be used for memory application [2,5]. However, many of these memory devices required high programming and erasing voltage, in a range of 50–200 V. Another arrangement of dielectrics for memory application is metal nanocrystals, such as Au or Al, as charge storage embedded in between a control dielectric and tunnelling dielectric [1,10]. These memory devices had low operating voltages, in a range of 5–10 V. Recently Chang et al. [17] has demonstrated the use of HfON on polyimide substrate as charge trapping dielectric able to be programmed at 12 V. However, the low optical transmittance may inhibit the development of transparent devices.

* Corresponding author. Tel.: +64 9 3737599; fax: +64 9 3737479. E-mail address: [email protected] (K.C. Aw). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.02.034

The ability of dielectrics for charge storage can be examined by studying the metal–insulator–semiconductor (MIS) structure. For a good charge storage system, the capacitance–voltage (C–V) measurement on the MIS structure, performed by employing a d.c. bias voltage with a small a.c. voltage, must have a large hysteresis in the capacitance when double sweeping the d.c. bias voltage [5]. In this paper, the application of d.c. sputtered ZnO as a dielectric sandwiched between two low-k sol–gel methyl-silsesquioxane (MSQ) layers as the main charge storage system of an organic thin film transistor (OTFT) based non-volatile memory (NVM) will be demonstrated. ZnO is a very unique material with wide band gap of about 3.4 eV [11]. Its optical and electrical properties can be easily altered by doping and modification on the deposition technique. d.c. Sputtering was used over r.f. sputtering as it would produce a thinner ZnO film with higher resistivity [12]. The motivation of using ZnO as a dielectric is due to its chemical stability and optical transparency, together with easy processing and optical transparency of MSQ, enabling future development of transparent electronic devices. The use of sputtered ZnO is not an ideal fabrication technique but the aim of this paper is to demonstrate the use of ZnO as a dielectric for non-volatile memory. 2. Experimental set-up Three arrangements of triple layer dielectric (NVM1, NVM2 and NVM3) were considered in this study, as shown in Fig. 1. The thickness of the MSQ labelled as ‘‘thick” and ‘‘thin” was 200 and 120 nm, respectively. The MSQ used was HSG 7000 from Hitachi Chemicals Ltd. In this paper, highly conductive n-type silicon was used as the

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S

Triple layer dielectric

D

S

S

D

D

Soluble pentacene thick MSQ

Soluble pentacene thin MSQ

Soluble pentacene thick MSQ

Zinc Oxide thick MSQ

Zinc Oxide thick MSQ

Zinc Oxide thin MSQ

Si gate

Si gate

Si gate

(a)

(b)

(c)

Fig. 1. The schematic diagram for: (a) NVM1, (b) NVM2 and (c) NVM3.

substrate and also gate of an OTFT. The spin coating rate for a ‘‘thick” and ‘‘thin” MSQ layer are 3000 and 6000 rpm, respectively. The fabrication began with the spin coating of the first MSQ layer on top of the gate substrate and then cured at 400 °C for 15 min on a hot plate. The ZnO was sputtered with a d.c. current of 0.25 A, a d.c. bias of 50 V, working gas (80%Ar:20%O2) pressure of 20 mTorr with a flow rate of 10 sccm, and a deposition time of 18 min. The average thickness of the sputtered ZnO was 50 nm. A very thin ZnO was used as the resistivity increased with reduction in film thickness [12,13]. Then, a second MSQ layer was spin coated and cured. A 65 nm thick soluble-pentacene was then spin coated at 2000 rpm for 100 s and converted at 200 °C for 2 min in N2 environment. The solution-processable pentacene was prepared with purified (via chromatography) 5 mg of 13,6-N-Sulfinylacetamodipentacene (from Sigma–Aldrich) into 1 mL of chloroform. Finally, the gold source and drain terminals of an OTFT-NVM were thermally evaporated with a shadow mask. Different OTFT-NVMs with channel width/length ratio of 4000/200, 1000/100 and 2000/200 lm were fabricated and characterized. All electrical characterizations were conducted in a N2 atmosphere. The output characteristics (ID–VD) of the OTFT-NVM were measured using a Keithley 2602 source-measure unit. The OTFTNVM was programmed with the source at 0 V, negative drain voltage (VD) and positive gate voltage (VG). The polarities at the drain and gate terminals were reversed during the erase cycle. In order to further comprehend the triple layer dielectric, similar metal–insulator–semiconductor (MIS) structures with those in Fig. 1 were fabricated and labelled as MIS1, MIS2 and MIS3 that structurally corresponded to NVM1, NVM2 and NVM3, respectively. The dielectrics were deposited on a p-type <1 0 0> Si wafer. Vacuum thermal evaporation was used to deposit the gold metal contact from a circular shadow mask with a diameter of 1 mm. The capacitance–voltage (C–V) characteristics of the MIS structures were obtained using an Agilent 4263B LCR system with Agilent E3649A DC power supply connected to an external bias adapter (Agilent 16065C) at a frequency of 100 kHz; and peak-to-peak amplitude of 500 mV was superimposed on the d.c. bias. The shift in flat-band (VFB) of the C–V plot after d.c. stress on the MIS structures were measured to comprehend the electrons injection mechanism. This was performed by subjecting the MIS structures to

a

Positive DC bias stress

+

C-V Meter -

Au MSQ Zinc Oxide MSQ p-Si

either positive or negative polarity of 15 V for 15 s and observing the shift in VFB after each stress. The configuration of this d.c. bias stress is illustrated in Fig. 2. A Perkin–Elmer–Lambda 900 UV/Vis/NIR spectrometer was used to determine the transmittance and absorption of the ZnO film deposited on quartz plate. Scanning electron microscopy (SEM) was used to determine the film thickness of each dielectric layer and an AMBIOS QScope 250 atomic force microscopy (AFM) was used to obtain the surface morphology of the sputtered ZnO. 3. Results and discussion The dielectric constants (k) of MSQ and ZnO were calculated from measured capacitance at 1 MHz on the MIS structures and range from 2.0 to 2.2 and 50 to 53.6, respectively. The high k-value of ZnO suggests its superb charge storage capability, allowing ZnO to be an excellent candidate as a charge trapping dielectric for nonvolatile memory application. The high k-value deviates from the mostly reported k-value of ZnO, which is 10 and is not understood during this writing. Its measured electrical resistivity (q) is 5  107 X-cm. The ZnO film’s q increases as the film become thinner. This can be explained by the quantum confinement effect, where split energy levels can appear inside nano-sized regions in ZnO film, in contrast to the continuous energy band in bulk materials [14]. The charge trap system within the ZnO was analysed using the C–V plots. Double sweep C–V plot performed on MIS1 is shown in Fig. 3. A large clockwise hysteresis of approximately 6 V is observed. This C–V hysteresis loop can be qualitatively explained using the semiconductor field-effect device. Large negative voltage is required for a p-type Si to be in the accumulation mode with a relatively large capacitance. Sharp decrease in capacitance indicates the flat-band as it switches from accumulation to inversion mode. Further increase in the positive gate voltage causes the capacitance to plateau at low value. Upon decreasing back to negative bias, the capacitance rise again as Si goes to accumulation. However, the flat-band voltage (VFB) shifts to be more negative due to the net hole trapping effect [15], proving the superb charge storage ability of this triple layer dielectric structure. Fig. 4a and b show that NVM1 can be programmed with VG = +15 and VD = 15 V for 46 s while NVM2 can be programmed

b

Negative DC bias stress

-

C-V Meter +

Au MSQ Zinc Oxide MSQ p-Si

Fig. 2. Electrical configurations for: (a) positive and (b) negative d.c. bias stress on MIS.

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2

Capacitance/Area (nF/cm )

2.5

2.4 Forward Reverse

2.3

2.2

that a thin MSQ adjacent to the gate terminal allows unwanted electrons tunnelling from the p-type Si into the ZnO instead of from the pentacene layer. Based on these results, the structure of NVM2 will be a suitable candidate as OTFT-NVM. The optical transmittance of the film is shown in Fig. 6, indicating that the film is transparent (P85%) in the visible region (k = 400–800 nm). From the optical spectrum, the average optical band gap determined from the photon energy based on the half height of the maximum absorption technique described in Ref. [16] is calculated to be 3.23 eV. Fig. 7 shows the SEM cross-section

a

-3.0E-08

Program (Vg=+15V, Vd=-15V) -2.5E-08

Electrical Erase (Vg=-15V, Vd=+15V)

2.1 -15

-10

-5

0

UV erase (20mW, 20 minutes)

5 -2.0E-08

Fig. 3. A forward and reverse C–V scan of MIS1 at 100 kHz.

I D, A

Gate Voltage (V)

-1.5E-08

-1.0E-08

-5.0E-09 Vg= - 5V

0.0E+00

-1

-3

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-9

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b

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Initial Program (Vg=+10V, Vd=-10V)

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Erase (Vg=-10V, Vd=+10V)

Id, A

-2.00E-08

-1.50E-08

-1.00E-08

-5.00E-09 Vg = -5V

0.00E+00

0

-2

-4

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-8

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Vd, V

c

-4.00E-07

Initial -3.50E-07

Program (Vg=+10 V, Vd=-10V) Erase (Vg=-10V, Vd =+10V)

-3.00E-07 -2.50E-07

ID, A

at a lower voltage of VG = +10 V and VD = 10 V with a similar effect. It is believed that during programming, the negative VD and positive VG cause electrons tunnelling from the pentacene through the MSQ and these electrons are trapped in ZnO. These trapped electrons will induce more holes in pentacene, hence increase the drain current (ID) at normal operation, e.g. VG = 5 and VD = 10 V. On the other hand, during the erase cycle, the reversed polarity at the drain and gate terminals cause the trapped electrons to be tunnelled back to the pentacene through the same MSQ layer, reaching equilibrium. NVM2 can be completely erased with VG = 10 and VD = +10 V but NVM1 can only be partially erased even with VG = 15 and VD = +15 V for 46 s. However, ID drops to the initial erased value with an additional exposure to a UV-source of 20 mW for 20 min and could be due to similar effect of UV erasing an electrically programmable read-only memory (EPROM) or could be due degradation of the pentacene film upon UV radiation. The later effect is highly possible as the ID of a reprogrammed NVM1 is much lower than before exposure to UV. The inability of NVM1 to be completely electrically erased is believed to be due to a thicker MSQ adjacent to the pentacene in NVM1 compared to NVM2 increases the probability of electrons trapping in the MSQ itself during programming, and will impede electrons returning to the pentacene layer during erasing. On the contrary, NVM2 can be completely erased and reprogrammed electrically as the MSQ adjacent to pentacene is thinner. NVM3 has a reverse effect, as the programmed ID–VD is similar to the erased ID–VD of NVM1 and NVM2, while, the erased ID–VD is similar to the programmed ID–VD of NVM1 and NVM2, as shown in Fig. 4c. This is believed to be due to the thin MSQ adjacent to the gate terminal, allowing unwanted electrons tunnelling from the silicon gate rather than from the pentacene. Therefore NVM1 and NVM3 configurations are not suitable. As shown in Fig. 5a and b, the VFB of MIS2 and MIS3 shifts towards the positive direction after each d.c. negative bias. The positive shift in the VFB indicates electrons trapped within the ZnO. On the other hand, the VFB of MIS2 remains unchanged after d.c. positive bias, indicating the absence of electrons tunnelling from the ptype Si and trapped in ZnO as shown in Fig. 5c. The VFB of MIS3 remains relatively unchanged for the initial three cycles but shifted towards the positive direction after the fourth cycle, as shown in Fig. 5d. It is believed that the MIS3’s thin MSQ adjacent to the ptype Si weakens after the fourth stress cycle, allowing a large amount of electron tunnelling from the p-Si substrate. Since MIS3 is structurally similar to NVM3, it has been demonstrated

-2.00E-07 -1.50E-07 -1.00E-07 -5.00E-08 Vg = -5V

0.00E+00

0

-2

-4

-6

-8

-10

VD, V Fig. 4. I–V plots at VG =

5 V of OTFT-NVM for: (a) NVM1, (b) NVM2 and (c) NVM3.

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1.05

1

(a)

1

(b)

0.98 0.96

C/Cmax

C/Cmax

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0.9 VFB shift

0.94 0.92

VFB Shift

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initial

0.85

after 2nd negative bias 0.8

initial

0.88

after 1st negative bias after 3rd negative bias

after 1st negative stress

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after 3rd negative stress

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after 4th negative stress

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Vg, V

0.85 0.8

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initial

after 1st positive stress

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after 2nd positive stress

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after 3rd positive stress

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initial

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after 1st positive stress

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after 2nd positive stress after 3rd positive stress

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after 4th positive stress

after 4th positive stress

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0.6

-10

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0

5

10

-8

-6

-4

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0

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4

Vg, V

Vg, V Fig. 5. C–V scan after negative d.c. bias for: (a) MIS2, (b) MIS3 and after positive d.c. bias for (c) MIS2 and (d) MIS3.

of the triple layer dielectric structure of MIS1. Fig. 8 shows an AFM micrograph of a 50 nm thick ZnO with an average roughness of 5 nm and a peak to trough of 30 nm. At the present, these OTFT-NVMs have a program/erase cycle of no more than 10 as the MSQ will breakdown after repeated cycles. 4. Conclusion

of 50 and high-resistivities (5  107 X-cm) can be achieved via d.c. magnetron sputtering with Ar:O2 ratio of 80:20. The film is reasonably transparent (P85%) in the visible region and the calculated optical band gap is 3.23 eV. The sandwiching low-k MSQ dielectric allows low programming and erasing voltage. Since the MSQ is a relatively weak dielectric, it is essential to ensure that the layer adjacent to the gate terminals has sufficient insulation to suppress the unwanted electrons tunnelling from the gate. We

We have demonstrated an OTFT-based non-volatile memory using ZnO as a dielectric. A very thin layer of ZnO with a k-value

100 90 80 70

%T

60 50 40 30 20 10 0 300

550

800

1050

1300

1550

1800

2050

2300

wavelength (nm) Fig. 6. Optical transmittance spectra of the ZnO dielectric.

Fig. 7. Cross-section of the triple layer dielectric structure of MIS1

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Gordon Rewcastle from Auckland Cancer Society Research Centre Faculty of Medical and Health Sciences, The University of Auckland for providing the chromatography support. Finally, we would like to thank Associate Professor Subodh Mhaisalkar from School of Materials Science and Engineering, Nanyang Technological University, Singapore for his assistance in UV–vis–NIR spectrometry and 4-point probing. References

Fig. 8. A 10 lm  10 lm AFM image of the ZnO film.

acknowledge that the use of sputtered ZnO is not economical but paved the route for the use of other technique such as sol–gel ZnO to replace the sputtering technique. Acknowledgements The authors would like to acknowledge the support from Marsden Fund from Royal Society of New Zealand and also UARC staff research fund. We would also like to thank Associate Professor

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