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4H-SiC superjunction trench MOSFET with reduced saturation current
Accepted Manuscript 4H-SiC superjunction trench MOSFET with reduced saturation current Qingyuan He, Xiaorong Luo, Tian Liao, Jie Wei, Gaoqiang Deng, Tao Sun, Jian Fang, Fei Yang PII:
S0749-6036(18)31665-3
DOI:
10.1016/j.spmi.2018.10.016
Reference:
YSPMI 5928
To appear in:
Superlattices and Microstructures
Received Date: 12 August 2018 Revised Date:
17 September 2018
Accepted Date: 16 October 2018
Please cite this article as: Q. He, X. Luo, T. Liao, J. Wei, G. Deng, T. Sun, J. Fang, F. Yang, 4H-SiC superjunction trench MOSFET with reduced saturation current, Superlattices and Microstructures (2018), doi: https://doi.org/10.1016/j.spmi.2018.10.016. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
ACCEPTED MANUSCRIPT
4H-SiC Superjunction Trench MOSFET With Reduced Saturation Current
Fanga, Fei Yangb a
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Qingyuan Hea, Xiaorong Luoa, Tian Liaoa, Jie Weia, Gaoqiang Denga, Tao Suna, Jian
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
Global Energy Interconnection Research Institute, Changping District, Beijing 102209, China
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b
Corresponding author. Tel: +86 28 83206788, Fax: +86 28 83207120, Email: [email protected]
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Abstract—A novel 4H-SiC superjunction trench metal oxide semiconductor field effect transistor (SJ-TMOS) is proposed in this paper. The device features a grounded P+ buried layer below the P-body, an oxide trench beneath the gate, and a P-region surrounding the oxide trench. The P-region, grounded P+ buried layer, and P-body serve as a three-level buffer (TLB) to lower the saturation current and thus improve the short-circuit ruggedness. Moreover, the P-region, P+ buried layer and N-drift form an SJ structure to decrease the
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specific on-resistance (Ron,sp) and increase the breakdown capability. Compared with conventional trench MOSFET (C-TMOS), the saturation current for SJ-TMOS is drastically lowered and thus the short-circuit time (tsc) extends by 175%. Meanwhile, the Ron,sp decreases by 45% and the breakdown voltage increases by 10%. In addition, the SJ-TMOS exhibits a
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low gate-to-drain charge (Qgd) due to the low permittivity of oxide trench and the nonlinearity in SJ capacitance characteristics.
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Keywords: 4H-SiC, superjunction (SJ), saturation current, on-resistance, breakdown capability.
INTRODUCTION
Silicon carbide MOSFETs, as a potential candidate for the next generation power switching device, are developing toward lower specific on-resistance (Ron,sp), lower switching loss, higher breakdown capability, and better short-circuit ruggedness [1], [2]. The trench technology and superjunction (SJ) structure are employed to reduce Ron,sp. The former optimizes the channel density and scalability, and some shielding structures are joined to overcome premature breakdown in oxide so as to keep the high breakdown voltage (BV)
ACCEPTED MANUSCRIPT [3]-[5]. The latter allows drift region heavily doped and modifies the electric field distribution, realizing high BV and low Ron,sp [6]-[8]. Reducing the Ron,sp often leads to higher saturation current and thus degrades the short-circuit ruggedness. To lower saturation current, one typical way is to increase the JFET resistance, while the Ron,sp inevitably increases [9], [10]. In terms of improving the high frequency characteristics, shrinking the gate-to-drain
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overlapped area and thickening the bottom oxide are common methods in [11]-[13]. The 4H-SiC superjunction trench MOSFET (SJ-TMOS) is proposed to optimize the
trade-off relationship between Ron,sp and short-circuit ruggedness, simultaneously improves
dynamic performance and BV. The three-level buffer (TLB) reduces the saturation current
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(Idsat). The SJ structure reduces Ron,sp and improves BV. The switching loss is decreased because of the reduced gate-to-drain capacitance (Cgd). Simulation based on Sentaurus TCAD is carried out to investigate the static and dynamic characteristics. Shockley-Read-Hall
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recombination, Auger recombination, Okuto avalanche, incomplete dopant ionization mobility, doping dependence mobility, and high field saturation mobility are used in simulation. The thermodynamic model is covered in simulation of short-circuit test and an appropriate heat resistance is attached to the drain contact.
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DEVICE STRUCTURE AND MECHANISM
Figure 1 shows the schematic cross-sectional structures of the proposed SJ-TMOS, the conventional trench MOS (C-TMOS) and the double-trench MOS (trench source and trench gate, DT-MOS). The gate structure of SJ-TMOS includes a shallow trench and a deep trench.
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The shallow trench is wider and filled with polysilicon. The gate oxide thickness is 50nm. The deep trench is filled with SiO2 to form an oxide trench. A P-region surrounding the oxide
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trench relieves the electric field (E-field) at its bottom and corner. A grounded P+ buried layer touches the shallow trench to reduce the high E-field at its corner. The P-region, the grounded P+ buried layer and the P-body make up the TLB to drastically lower the Idsat. The P-region assists in depleting the N-drift and thus the Nd is increased. The oxide trench can withstand high voltage and reduce the Cgd owing to the low permittivity. The nonlinearity in SJ capacitance characteristics further lowers Cgd. In simulation of this paper, the channel length is 0.3µm, and an electron mobility of 20cm2/V·s. The doping concentration of P-body is 2×1017cm-3. The doping profile of P+ buried layer for SJ-TMOS and C-TMOS exhibits Gauss distribution, with surface concentration of 1×1019cm-3 and junction depth of 0.3µm. The doping concentration of drift region and the P-region are represented by Nd and Np, respectively. The distance between
ACCEPTED MANUSCRIPT P-body and P+ buried (w1) and the distance from P+ buried to the central of JFET region (w2) influence the saturation current. 2.25µm
Source
1.75µm
N+ P
1.75µm
Source Gate
Gate Poly
1.2µm
w1 P+
N+ P CSL (2 ×1016cm-3)
Source Gate
Poly P 1µm
Metal
P+
N+ P Lm
Poly P
P+
w2 SiO2
SiO2
0.5µm
7µm
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0.4 µm
10µm
1µm N-drift
N-drift
N-drift
( 6.5× ×1015cm -3)
( 6.5× ×1015cm-3)
N+
N+
N+
Drain
Drain
Drain
(a) SJ-TMOS
(b) C-TMOS
(N d)
Fig.1.
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P (Np)
(c) DT-MOS
Schematic cross-sectional structures of (a) proposed superjunction trench MOSFET (SJ-TMOS), (b)
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the conventional trench MOSFET (C-TMOS) and (c) DT-MOS.
Figure 2 shows the off-state E-field contours. At the drain voltage of 1200V, the maximum E-field in oxide (Eox-max) of 1.77MV/cm for the SJ-TMOS is far below those of the other devices. Even though the breakdown occurs at 1633V, the Eox-max for the SJ-TMOS is in the safe area. Figure 3 (a) shows the depletion boundary of the three-level buffer (TLB) at the on-state. The depletion caused by TLB narrows the current and thus the out-put current is apt
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to saturate. Figure 3 (b) shows the assistant depletion effect of the P-region and the P+ buried layer on the N drift region and the JFET region at off-state, and thus the higher optimum Nd is
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allowed.
Fig.2.
Electric Field(MV/cm) 3.0
Oxide Trench
EOX=1.77MV/cm
(a)
EOX=3.07MV/cm
ESiC =3.88MV/cm
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ESiC=3.19MV/cm
EOX=2.74MV/cm
Oxide Trench
ESiC=3.87MV/cm
2.5
ESiC=3.7MV/cm 2.0 1.5 1.0 0.5
EOX=2.68MV/cm 0.0
(b)
(c)
(d)
OFF-state E-field contours for the (a) SJ-TMOS at Vds=1200V, (b) SJ-TMOS at Vds=BV=1633V (c)
C-TMOS at Vds=1200V and (d) DT-MOS at Vds=1200V.
ACCEPTED MANUSCRIPT N+ P-body
Poly
Poly
Poly
Poly
3rd 2nd
SiO SiO2
P+
SiO2 SiO 2
1st
2
P
SiO 2 SiO
SiO2 SiO 2
2
P
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N-drift
Depletion boundary
(a) Fig.3.
(b)
(a) In the on-state, the mechanism of three-level buffer to lower the saturation current. (b) In the
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OFF-state, the P-region and the P+ buried layer assist to deplete the N-drift.
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RESULTS AND DISCUSSION
Figure 4 (a) shows the breakdown characteristic curves. The SJ-TMOS has the highest BV of 1663V, and the equipotential lines distribution is more uniform than those of C-TMOS and DT-MOS. Figure 4 (b) shows the vertical electric field distributions. Because of the mutual depletion effect of the P- and N- pillar in the SJ, the E-field distribution for the SJ-TMOS at the P/N interface is uniform and thus its BV is higher than those of C-TMOS and DT-MOS.
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Figure 5 (a) shows the relationship between BV and Nd, Np for SJ-TMOS. For each Nd, there is an optimum Np correspondingly. As Nd increases, Np must be increased to realize the charge balance, while the BV will degrade owing to the increase in lateral electric field. Figure 5 (b) shows the impacts of Nd on the BV, Ron,sp and the figure of merit
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(FoM=BV2/Ron,sp). The proposed structure without the P-region of SJ is as a comparison with the proposed SJ-TMOS, the optimum Nd for the SJ-TMOS of 9.5×1016 cm-3 is far higher than
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1.2×1016 cm-3 for the comparison structure, and the FoM is 2× high. Figure 6 shows the trade-off relationship between Ron,sp and Eox-max for these three devices. The SJ-TMOS exhibits a great advantage in reducing Eox-max- and Ron,sp over the other two devices. For the DT-MOS, the Eox-max decreases and the Ron,sp increases as the length of mesa (Lm, see figure 1(c)) reduces.
ACCEPTED MANUSCRIPT 4 SJ-TMOS BV=1633V BV=1486V
DT-MOS
BV=1554V
SJ-TMOS Electric Potential (V)
3
1600 1200
10-2
400 0 SJ-TMOS
C-TMOS
Flat Electric Field
1
DT-MOS
10-4
0 0
400
800
1200
1600
0
2
4
6
8
y (µm)
Vds (V) (a) Fig.4.
DT-MOS
2
800
10-3
C-TMOS
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10-1
C-TMOS
E (MV/cm)
Ids (µ µ A/cm2)
100
10
(b)
(a) Blocking I-V curves, the breakdown voltages are 1633V, 1486V, 1554V, respectively. The inset
Nd= 9.5× ×1016cm-3
Nd= 11× ×1016cm-3
1600 1400 1200 1000 800 0.5
1.0
1.5
2.0
2.5
3.0
Np /1017 (cm-3)
2500
3.0
Optimum
FoM
2000
2.5
Optimum
2.0
1500
1.5
1000
500 0.5
3.5
1.0
1.5
1.0
2.0 6
8
10
12
14
Nd /1016 (cm-3) (b)
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(a) Fig.5.
with P-region w/o P-region BV Ron,sp
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BV (V)
1800
Nd= 8× ×1016cm-3
Ron,sp (mΩ Ω⋅cm2)
3000 Nd= 6.5× ×1016cm-3
BV (V) , FoM (MW/cm2)
2000
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figures are electric potential contours. (b) Electric field distributions in the vertical direction.
(a) Relationship between BV and Np with different Nd for the SJ-TMOS. (b) Relationship between FoM and the Ron,sp for the proposed SJ-TMOS and the proposed structure without the P-region of SJ. Lm(µm)=1
5
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Eox-max (MV/cm)
6
Fig.6.
0.9 DT-MOS
4
0.8 0.7
Ron,sp : 45%
3
0.6 C-TMOS
Eox-max : 42%
2 SJ-TMOS
1
1.2
1.4
1.6
1.8
Ron,sp (mΩ Ω⋅cm
2.0 2
2.2
2.4
)
Ron,sp verse Eox for SJ-TMOS, C-TMOS and DT-MOS. The Lmesa of DT-MOS is from 1µm to 0.6µm
with the step of 0.1µm.
Figure 7 shows the I-V characteristic curves of the three structures at different Vgs. The SJ-TMOS has the lowest both Ron,sp and Idsat among the three devices. It’s worth noting that the ST-TMOS works in the saturated state around Vds = 5V, but the output currents for the
ACCEPTED MANUSCRIPT C-TMOS and the DT-MOS are still unsaturated at Vds = 15V. The trade-off relationships between the Idsat and the Ron,sp for the SJ-TMOS are shown in figure 8. As w1 and w2 reduce, the Idsat decreases while the Ron,sp increases. If the value of w1 or w2 is too small (w1 = 0.4µm or w2 = 0.2µm), the current paths have pinched off owing to the depletion of PN junction, so the Ron,sp is large. When the value of w1 is too large (e.g. w1 =
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0.8µm), w2 pays a critical impact on Idsat. As w1 reduces, the impact of w2 on Idsat is decreased. When w1 ≥ 0.5µm, the change range of Ron,sp is relatively narrow, but the Idsat increase 3× from w1 = 0.5µm to w1 = 0.8µm, The value of 0.5µm is thus chosen for the optimum value of w 1. 5 =
15V
20V
25V
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Vgs SJ-TMOS
4
C-TMOS
3
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Ids (kA/cm
2
)
DT-MOS
2
1
0
2
4
6
8
10
12
14
Vds (V)
Output characteristic curves at Vgs = 15V/20V /25V.
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Fig.7.
8
w2=0.2µ µm w2=0.3µ µm
6
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Isat (kA/cm
2
)
w1=0.8µm
4
w2=0.4µ µm w2=0.5µ µm
w1 from 0.8µm to 0.4µm, step 0.1µm w1=0.8µm
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2
Fig.8.
0.5µm
w1=0.4µm
0 w1=0.4µm
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
Ron,sp (mΩ Ω⋅cm
2
)
Tradeoff between Ron,sp and Idsat for the SJ-TMOS as the functions of w1 and w2.
Figure 9 gives the short-circuit waveforms for the SJ-TMOS, the C-TMOS and the DT-MOS at the bus voltage of 600V. The gate resistance and the stray inductance are set to be 5Ω and 10nH, respectively. The gate turns on at 5µs. The short-circuit current for SJ-TMOS is the lowest due to its lowest saturation current as mentioned above. The
ACCEPTED MANUSCRIPT short-circuit duration time for SJ-TMOS, C-TMOS and DTMOS is set to 11µs, 5µs and 8µs, respectively. The failure for C-TMOS and DT-MOS is detected after the gate turns off as shown within the blue and green lines, because the high heat produced during short-circuit is stored and it can’t give away. Consequently, the short-circuit withstanding time (tsc) for C-TMOS and DT-MOS is less than 5µs and 8µs, respectively. For the SJ-TMOS, thanks to
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the low saturation current, the heat produced during short-circuit doesn’t reach the critical value and thus the SJ-TMOS is found no failure.
800 600 400
20
600V
10n H
10
5µs
5
8µs
DUT
11µs
0 -5 -10
6
2
Ids (kA/cm )
5Ω
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Vgs (V)
15
SJ-TMOS C-TMOS DT-MOS
4 2 0 5
10
15
20
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0
Fig.9.
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Vds(V)
1000
50
t (µs)
75
100
125
150
Output currents and gate voltages at room temperature with the short-circuit time of 11µs, 5µs and 8µs, respectively. The inserted figure is the test circuit of short-circuit for simulation.
The reverse transfer capacitance (Crss = Cgd) and the output capacitance (Coss) play critical
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roles on reducing the switching losses. As shown in figure 10 (a), the capacitance characteristic for the SJ-TMOS is strongly nonlinear. This phenomenon in SJ devices has
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been discussed in [14]-[16]. The equivalent capacitance for SJ-TMOS at Vds < Vc (see figure 10(a)) and Vds > Vc are potted in figure 10 (b), When Vds < Vc, the Crss is small because the neutral region of the P-region connects to the source, which shields Cgd. Therefore, the capacitance at the bottom of the trench is gate-to-source (Cgs). As Vds increases beyond Vc, the Crss increases due to the weakened shielding effect with the shrinking P-neutral region. Gate charges of these three structures are tested with the circuit in the inset of figure 10 (c). All the device areas are set to be 1 cm2, the dc voltage of 600V is applied, and the currents of load and gate are 100A and 200mA, respectively. A SiC JBS diode is used to provide a freewheeling path. As shown in figure 10 (b), the Qgd for the SJ-TMOS, the C-TMOS and DT-MOS is 162nC/cm2, 211nC/cm2 and 304 nC/cm2. The lowest Qgd for the SJ-TMOS
ACCEPTED MANUSCRIPT exhibits the lowest switching losses. 15
10
-8
10
-9
SJ-TMOS
C-TMOS
Qgd (nC/cm2)
DT-MOS
SJ-TMOS 162 C-TMOS 211 DT-MOS 304
600V
10
Vg (V)
Cgs
Coss 10-10
200mA
5
Crss
10-11
SiC JBS
100A
DUT Qgd
10-12
Cgd
depletion boundary
0 Vc=60V
200
400
600
Vds (V)
Vds < Vc
(a)
0
0
200
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2
C (F/cm )
10-7
400
600
800
1000
2
Qg (nC/cm )
Vds > Vc
(b)
(c)
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Fig.10. (a) Terminal capacitances of SJ-TMOS, C-TMOS and DT-MOS. (b) the equivalent capacitances are plotted in the SJ-TMOS for Vds < Vc and Vds > Vc. (c) Specific gate charge characteristic curves. The extracted Qgd is 162, 211, and 304nC/cm2, respectively. The inserted figure is the text circuit.
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Table I summarizes the simulation results of SJ-TMOS, C-TMOS and DT-MOS. The FoM BV2/Ron,sp for the SJ-TMOS increases by more than 100%, and the FoM Ron,sp×Qgd decreases by more than 50% compared with those of the other two devices. The larger value of BV2/Ron,sp and the smaller value of Ron,sp × Qgd exhibit the better static and dynamic performance, respectively. As can be seen from figure 11, the result of the proposed SJ-TMOS is closed to the theoretical 1-D limit of 4H-SiC unipolar devices. With the
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advancement of fabrication process technology, the SiC SJ technology can be extended to higher level of voltages, such as 3.3kV, 6.5kV, and the advantages would be more outstanding.
1633
1.77
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SJ-TMOS
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Device Type
TABLE I. CHARACTERISTICS OF SJ-TMOS, C-TMOS AND DT-MOS Ron,sp BV Eox-max Qgd BV2/ Ron,sp Ron,sp×Qgd tsc 2 (V) (MV/cm) (mΩ·cm ) (nC/cm2) (MW/cm2) (mΩ·nC) (µs) 1.14
162
2339
185
11
C-TMOS
1486
2.74
2.11
211
1046
445
4
DT-MOS
1554
3.07
2.07
304
1167
629
7
Eox-max at Vgs=0V, Vds=1200V.
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[1 8]
it [5] [11]
[10]
[4]
1
[6]
[7]
This work 0.1 100
1000
BV (V) Fig.11.
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4H -S iC
[4]
un ip ola rl im
un ip o la r
10
Si
Ron,sp (mΩ Ω⋅cm
2
)
lim
it
[1 7]
100
10000
Tradeoff between the breakdown voltage and the specific on-resistance in recent 4H-SiC
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simulation reports and research samples.
A feasible fabrication procedure is shown in figure 12. The deep trench is formed by ICP etching after the shallow trench in (e). A metal with high etching selectivity to 4H-SiC is
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selected for the mask layer, and it can be used for next three steps from (f) to (h). Figure 13 (a) shows the 3-D layout of SJ-TMOS, the P+ source is located in the z-direction, and it is protruded over the P-body to contact on the P+ buried layer. The schematic cross section of the face ABCD and A’B’C’D’ are plotted in figure13 (b) and (c). The P+ buried layer is well
(a) METEL
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G
SUB
SUB
SUB
SUB
(b)
(c)
(d)
(e)
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SUB
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grounded by the P+ source.
SUB
SUB
SUB
SUB
SUB
(j)
(i)
(h)
(g)
(f)
Fig.12. key fabrication process flows for the SJ-TMOS: (a) Form the P+ buried layer, (b) n-type epitaxial growth (c) form the P+, N+ sources and the P-body, (d) ICP etch to form the shallow trench, (e) ICP etch to form the deep trench, (f) vertical implantation to form the P-region at the bottom of trench, (g) tilted implantation to form the P-region along the sidewall of trench (h) fill the deep trench with SiO2, (i) thermal oxidation to form the gate oxide, (j) deposition the poly silicon and form electrodes.
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A’ ’
B’ ’
x A y D
P+
N+ P P+
B B
Poly
C
SiO22 SiO SiO2
N+ P
P+
SiO2
SiO2
N-drift D’ ’ N+
P+
Contact
C’ ’ D
(a) Fig.13.
B’ ’
A’ ’ A
C
(b)
SiO2
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Poly
(c)
(a) 3-D view of SJ-TMOS. (b) Schematic cross section of the face ABCD (c) Schematic cross
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section of the face A’B’C’D’.
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CONCLUSION
A 1200-class 4H-SiC SJ-TMOS is proposed in this paper. The TLB effectively lowers the saturation current by more than 50%, leading to the lengthened tsc of 11µs. The SJ structure reduces the on-resistance and improve the breakdown capability. The electric field in oxide is low owing to the shielding effect of the P-region and the grounded P+ buried layer. In
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addition, the SJ-TMOS also exhibits a good dynamic performance because of the low Qgd. The SJ-TMOS is more attractive and promising for the high frequency and high power
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carbide." (2001).
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The three-level buffer of the proposed device lowers the saturation current and thus improves the short-circuit ruggedness.
●
the superjunction structure reduces the specific on-resistance and improves the breakdown voltage.
●
The P-region and the grounded P+ buried layer shield the trench and thus reduce the electric field in oxide.
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The low switching loss is caused by the low gate-to-drain charge.
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1
S0749-6036(18)31665-3
DOI:
10.1016/j.spmi.2018.10.016
Reference:
YSPMI 5928
To appear in:
Superlattices and Microstructures
Received Date: 12 August 2018 Revised Date:
17 September 2018
Accepted Date: 16 October 2018
Please cite this article as: Q. He, X. Luo, T. Liao, J. Wei, G. Deng, T. Sun, J. Fang, F. Yang, 4H-SiC superjunction trench MOSFET with reduced saturation current, Superlattices and Microstructures (2018), doi: https://doi.org/10.1016/j.spmi.2018.10.016. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
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4H-SiC Superjunction Trench MOSFET With Reduced Saturation Current
Fanga, Fei Yangb a
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Qingyuan Hea, Xiaorong Luoa, Tian Liaoa, Jie Weia, Gaoqiang Denga, Tao Suna, Jian
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
Global Energy Interconnection Research Institute, Changping District, Beijing 102209, China
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b
Corresponding author. Tel: +86 28 83206788, Fax: +86 28 83207120, Email: [email protected]
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Abstract—A novel 4H-SiC superjunction trench metal oxide semiconductor field effect transistor (SJ-TMOS) is proposed in this paper. The device features a grounded P+ buried layer below the P-body, an oxide trench beneath the gate, and a P-region surrounding the oxide trench. The P-region, grounded P+ buried layer, and P-body serve as a three-level buffer (TLB) to lower the saturation current and thus improve the short-circuit ruggedness. Moreover, the P-region, P+ buried layer and N-drift form an SJ structure to decrease the
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specific on-resistance (Ron,sp) and increase the breakdown capability. Compared with conventional trench MOSFET (C-TMOS), the saturation current for SJ-TMOS is drastically lowered and thus the short-circuit time (tsc) extends by 175%. Meanwhile, the Ron,sp decreases by 45% and the breakdown voltage increases by 10%. In addition, the SJ-TMOS exhibits a
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low gate-to-drain charge (Qgd) due to the low permittivity of oxide trench and the nonlinearity in SJ capacitance characteristics.
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Keywords: 4H-SiC, superjunction (SJ), saturation current, on-resistance, breakdown capability.
INTRODUCTION
Silicon carbide MOSFETs, as a potential candidate for the next generation power switching device, are developing toward lower specific on-resistance (Ron,sp), lower switching loss, higher breakdown capability, and better short-circuit ruggedness [1], [2]. The trench technology and superjunction (SJ) structure are employed to reduce Ron,sp. The former optimizes the channel density and scalability, and some shielding structures are joined to overcome premature breakdown in oxide so as to keep the high breakdown voltage (BV)
ACCEPTED MANUSCRIPT [3]-[5]. The latter allows drift region heavily doped and modifies the electric field distribution, realizing high BV and low Ron,sp [6]-[8]. Reducing the Ron,sp often leads to higher saturation current and thus degrades the short-circuit ruggedness. To lower saturation current, one typical way is to increase the JFET resistance, while the Ron,sp inevitably increases [9], [10]. In terms of improving the high frequency characteristics, shrinking the gate-to-drain
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overlapped area and thickening the bottom oxide are common methods in [11]-[13]. The 4H-SiC superjunction trench MOSFET (SJ-TMOS) is proposed to optimize the
trade-off relationship between Ron,sp and short-circuit ruggedness, simultaneously improves
dynamic performance and BV. The three-level buffer (TLB) reduces the saturation current
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(Idsat). The SJ structure reduces Ron,sp and improves BV. The switching loss is decreased because of the reduced gate-to-drain capacitance (Cgd). Simulation based on Sentaurus TCAD is carried out to investigate the static and dynamic characteristics. Shockley-Read-Hall
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recombination, Auger recombination, Okuto avalanche, incomplete dopant ionization mobility, doping dependence mobility, and high field saturation mobility are used in simulation. The thermodynamic model is covered in simulation of short-circuit test and an appropriate heat resistance is attached to the drain contact.
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DEVICE STRUCTURE AND MECHANISM
Figure 1 shows the schematic cross-sectional structures of the proposed SJ-TMOS, the conventional trench MOS (C-TMOS) and the double-trench MOS (trench source and trench gate, DT-MOS). The gate structure of SJ-TMOS includes a shallow trench and a deep trench.
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The shallow trench is wider and filled with polysilicon. The gate oxide thickness is 50nm. The deep trench is filled with SiO2 to form an oxide trench. A P-region surrounding the oxide
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trench relieves the electric field (E-field) at its bottom and corner. A grounded P+ buried layer touches the shallow trench to reduce the high E-field at its corner. The P-region, the grounded P+ buried layer and the P-body make up the TLB to drastically lower the Idsat. The P-region assists in depleting the N-drift and thus the Nd is increased. The oxide trench can withstand high voltage and reduce the Cgd owing to the low permittivity. The nonlinearity in SJ capacitance characteristics further lowers Cgd. In simulation of this paper, the channel length is 0.3µm, and an electron mobility of 20cm2/V·s. The doping concentration of P-body is 2×1017cm-3. The doping profile of P+ buried layer for SJ-TMOS and C-TMOS exhibits Gauss distribution, with surface concentration of 1×1019cm-3 and junction depth of 0.3µm. The doping concentration of drift region and the P-region are represented by Nd and Np, respectively. The distance between
ACCEPTED MANUSCRIPT P-body and P+ buried (w1) and the distance from P+ buried to the central of JFET region (w2) influence the saturation current. 2.25µm
Source
1.75µm
N+ P
1.75µm
Source Gate
Gate Poly
1.2µm
w1 P+
N+ P CSL (2 ×1016cm-3)
Source Gate
Poly P 1µm
Metal
P+
N+ P Lm
Poly P
P+
w2 SiO2
SiO2
0.5µm
7µm
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0.4 µm
10µm
1µm N-drift
N-drift
N-drift
( 6.5× ×1015cm -3)
( 6.5× ×1015cm-3)
N+
N+
N+
Drain
Drain
Drain
(a) SJ-TMOS
(b) C-TMOS
(N d)
Fig.1.
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P (Np)
(c) DT-MOS
Schematic cross-sectional structures of (a) proposed superjunction trench MOSFET (SJ-TMOS), (b)
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the conventional trench MOSFET (C-TMOS) and (c) DT-MOS.
Figure 2 shows the off-state E-field contours. At the drain voltage of 1200V, the maximum E-field in oxide (Eox-max) of 1.77MV/cm for the SJ-TMOS is far below those of the other devices. Even though the breakdown occurs at 1633V, the Eox-max for the SJ-TMOS is in the safe area. Figure 3 (a) shows the depletion boundary of the three-level buffer (TLB) at the on-state. The depletion caused by TLB narrows the current and thus the out-put current is apt
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to saturate. Figure 3 (b) shows the assistant depletion effect of the P-region and the P+ buried layer on the N drift region and the JFET region at off-state, and thus the higher optimum Nd is
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allowed.
Fig.2.
Electric Field(MV/cm) 3.0
Oxide Trench
EOX=1.77MV/cm
(a)
EOX=3.07MV/cm
ESiC =3.88MV/cm
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ESiC=3.19MV/cm
EOX=2.74MV/cm
Oxide Trench
ESiC=3.87MV/cm
2.5
ESiC=3.7MV/cm 2.0 1.5 1.0 0.5
EOX=2.68MV/cm 0.0
(b)
(c)
(d)
OFF-state E-field contours for the (a) SJ-TMOS at Vds=1200V, (b) SJ-TMOS at Vds=BV=1633V (c)
C-TMOS at Vds=1200V and (d) DT-MOS at Vds=1200V.
ACCEPTED MANUSCRIPT N+ P-body
Poly
Poly
Poly
Poly
3rd 2nd
SiO SiO2
P+
SiO2 SiO 2
1st
2
P
SiO 2 SiO
SiO2 SiO 2
2
P
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N-drift
Depletion boundary
(a) Fig.3.
(b)
(a) In the on-state, the mechanism of three-level buffer to lower the saturation current. (b) In the
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OFF-state, the P-region and the P+ buried layer assist to deplete the N-drift.
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RESULTS AND DISCUSSION
Figure 4 (a) shows the breakdown characteristic curves. The SJ-TMOS has the highest BV of 1663V, and the equipotential lines distribution is more uniform than those of C-TMOS and DT-MOS. Figure 4 (b) shows the vertical electric field distributions. Because of the mutual depletion effect of the P- and N- pillar in the SJ, the E-field distribution for the SJ-TMOS at the P/N interface is uniform and thus its BV is higher than those of C-TMOS and DT-MOS.
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Figure 5 (a) shows the relationship between BV and Nd, Np for SJ-TMOS. For each Nd, there is an optimum Np correspondingly. As Nd increases, Np must be increased to realize the charge balance, while the BV will degrade owing to the increase in lateral electric field. Figure 5 (b) shows the impacts of Nd on the BV, Ron,sp and the figure of merit
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(FoM=BV2/Ron,sp). The proposed structure without the P-region of SJ is as a comparison with the proposed SJ-TMOS, the optimum Nd for the SJ-TMOS of 9.5×1016 cm-3 is far higher than
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1.2×1016 cm-3 for the comparison structure, and the FoM is 2× high. Figure 6 shows the trade-off relationship between Ron,sp and Eox-max for these three devices. The SJ-TMOS exhibits a great advantage in reducing Eox-max- and Ron,sp over the other two devices. For the DT-MOS, the Eox-max decreases and the Ron,sp increases as the length of mesa (Lm, see figure 1(c)) reduces.
ACCEPTED MANUSCRIPT 4 SJ-TMOS BV=1633V BV=1486V
DT-MOS
BV=1554V
SJ-TMOS Electric Potential (V)
3
1600 1200
10-2
400 0 SJ-TMOS
C-TMOS
Flat Electric Field
1
DT-MOS
10-4
0 0
400
800
1200
1600
0
2
4
6
8
y (µm)
Vds (V) (a) Fig.4.
DT-MOS
2
800
10-3
C-TMOS
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10-1
C-TMOS
E (MV/cm)
Ids (µ µ A/cm2)
100
10
(b)
(a) Blocking I-V curves, the breakdown voltages are 1633V, 1486V, 1554V, respectively. The inset
Nd= 9.5× ×1016cm-3
Nd= 11× ×1016cm-3
1600 1400 1200 1000 800 0.5
1.0
1.5
2.0
2.5
3.0
Np /1017 (cm-3)
2500
3.0
Optimum
FoM
2000
2.5
Optimum
2.0
1500
1.5
1000
500 0.5
3.5
1.0
1.5
1.0
2.0 6
8
10
12
14
Nd /1016 (cm-3) (b)
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(a) Fig.5.
with P-region w/o P-region BV Ron,sp
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BV (V)
1800
Nd= 8× ×1016cm-3
Ron,sp (mΩ Ω⋅cm2)
3000 Nd= 6.5× ×1016cm-3
BV (V) , FoM (MW/cm2)
2000
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figures are electric potential contours. (b) Electric field distributions in the vertical direction.
(a) Relationship between BV and Np with different Nd for the SJ-TMOS. (b) Relationship between FoM and the Ron,sp for the proposed SJ-TMOS and the proposed structure without the P-region of SJ. Lm(µm)=1
5
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Eox-max (MV/cm)
6
Fig.6.
0.9 DT-MOS
4
0.8 0.7
Ron,sp : 45%
3
0.6 C-TMOS
Eox-max : 42%
2 SJ-TMOS
1
1.2
1.4
1.6
1.8
Ron,sp (mΩ Ω⋅cm
2.0 2
2.2
2.4
)
Ron,sp verse Eox for SJ-TMOS, C-TMOS and DT-MOS. The Lmesa of DT-MOS is from 1µm to 0.6µm
with the step of 0.1µm.
Figure 7 shows the I-V characteristic curves of the three structures at different Vgs. The SJ-TMOS has the lowest both Ron,sp and Idsat among the three devices. It’s worth noting that the ST-TMOS works in the saturated state around Vds = 5V, but the output currents for the
ACCEPTED MANUSCRIPT C-TMOS and the DT-MOS are still unsaturated at Vds = 15V. The trade-off relationships between the Idsat and the Ron,sp for the SJ-TMOS are shown in figure 8. As w1 and w2 reduce, the Idsat decreases while the Ron,sp increases. If the value of w1 or w2 is too small (w1 = 0.4µm or w2 = 0.2µm), the current paths have pinched off owing to the depletion of PN junction, so the Ron,sp is large. When the value of w1 is too large (e.g. w1 =
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0.8µm), w2 pays a critical impact on Idsat. As w1 reduces, the impact of w2 on Idsat is decreased. When w1 ≥ 0.5µm, the change range of Ron,sp is relatively narrow, but the Idsat increase 3× from w1 = 0.5µm to w1 = 0.8µm, The value of 0.5µm is thus chosen for the optimum value of w 1. 5 =
15V
20V
25V
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Vgs SJ-TMOS
4
C-TMOS
3
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Ids (kA/cm
2
)
DT-MOS
2
1
0
2
4
6
8
10
12
14
Vds (V)
Output characteristic curves at Vgs = 15V/20V /25V.
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Fig.7.
8
w2=0.2µ µm w2=0.3µ µm
6
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Isat (kA/cm
2
)
w1=0.8µm
4
w2=0.4µ µm w2=0.5µ µm
w1 from 0.8µm to 0.4µm, step 0.1µm w1=0.8µm
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2
Fig.8.
0.5µm
w1=0.4µm
0 w1=0.4µm
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
Ron,sp (mΩ Ω⋅cm
2
)
Tradeoff between Ron,sp and Idsat for the SJ-TMOS as the functions of w1 and w2.
Figure 9 gives the short-circuit waveforms for the SJ-TMOS, the C-TMOS and the DT-MOS at the bus voltage of 600V. The gate resistance and the stray inductance are set to be 5Ω and 10nH, respectively. The gate turns on at 5µs. The short-circuit current for SJ-TMOS is the lowest due to its lowest saturation current as mentioned above. The
ACCEPTED MANUSCRIPT short-circuit duration time for SJ-TMOS, C-TMOS and DTMOS is set to 11µs, 5µs and 8µs, respectively. The failure for C-TMOS and DT-MOS is detected after the gate turns off as shown within the blue and green lines, because the high heat produced during short-circuit is stored and it can’t give away. Consequently, the short-circuit withstanding time (tsc) for C-TMOS and DT-MOS is less than 5µs and 8µs, respectively. For the SJ-TMOS, thanks to
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the low saturation current, the heat produced during short-circuit doesn’t reach the critical value and thus the SJ-TMOS is found no failure.
800 600 400
20
600V
10n H
10
5µs
5
8µs
DUT
11µs
0 -5 -10
6
2
Ids (kA/cm )
5Ω
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Vgs (V)
15
SJ-TMOS C-TMOS DT-MOS
4 2 0 5
10
15
20
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0
Fig.9.
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Vds(V)
1000
50
t (µs)
75
100
125
150
Output currents and gate voltages at room temperature with the short-circuit time of 11µs, 5µs and 8µs, respectively. The inserted figure is the test circuit of short-circuit for simulation.
The reverse transfer capacitance (Crss = Cgd) and the output capacitance (Coss) play critical
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roles on reducing the switching losses. As shown in figure 10 (a), the capacitance characteristic for the SJ-TMOS is strongly nonlinear. This phenomenon in SJ devices has
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been discussed in [14]-[16]. The equivalent capacitance for SJ-TMOS at Vds < Vc (see figure 10(a)) and Vds > Vc are potted in figure 10 (b), When Vds < Vc, the Crss is small because the neutral region of the P-region connects to the source, which shields Cgd. Therefore, the capacitance at the bottom of the trench is gate-to-source (Cgs). As Vds increases beyond Vc, the Crss increases due to the weakened shielding effect with the shrinking P-neutral region. Gate charges of these three structures are tested with the circuit in the inset of figure 10 (c). All the device areas are set to be 1 cm2, the dc voltage of 600V is applied, and the currents of load and gate are 100A and 200mA, respectively. A SiC JBS diode is used to provide a freewheeling path. As shown in figure 10 (b), the Qgd for the SJ-TMOS, the C-TMOS and DT-MOS is 162nC/cm2, 211nC/cm2 and 304 nC/cm2. The lowest Qgd for the SJ-TMOS
ACCEPTED MANUSCRIPT exhibits the lowest switching losses. 15
10
-8
10
-9
SJ-TMOS
C-TMOS
Qgd (nC/cm2)
DT-MOS
SJ-TMOS 162 C-TMOS 211 DT-MOS 304
600V
10
Vg (V)
Cgs
Coss 10-10
200mA
5
Crss
10-11
SiC JBS
100A
DUT Qgd
10-12
Cgd
depletion boundary
0 Vc=60V
200
400
600
Vds (V)
Vds < Vc
(a)
0
0
200
RI PT
2
C (F/cm )
10-7
400
600
800
1000
2
Qg (nC/cm )
Vds > Vc
(b)
(c)
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Fig.10. (a) Terminal capacitances of SJ-TMOS, C-TMOS and DT-MOS. (b) the equivalent capacitances are plotted in the SJ-TMOS for Vds < Vc and Vds > Vc. (c) Specific gate charge characteristic curves. The extracted Qgd is 162, 211, and 304nC/cm2, respectively. The inserted figure is the text circuit.
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Table I summarizes the simulation results of SJ-TMOS, C-TMOS and DT-MOS. The FoM BV2/Ron,sp for the SJ-TMOS increases by more than 100%, and the FoM Ron,sp×Qgd decreases by more than 50% compared with those of the other two devices. The larger value of BV2/Ron,sp and the smaller value of Ron,sp × Qgd exhibit the better static and dynamic performance, respectively. As can be seen from figure 11, the result of the proposed SJ-TMOS is closed to the theoretical 1-D limit of 4H-SiC unipolar devices. With the
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advancement of fabrication process technology, the SiC SJ technology can be extended to higher level of voltages, such as 3.3kV, 6.5kV, and the advantages would be more outstanding.
1633
1.77
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SJ-TMOS
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Device Type
TABLE I. CHARACTERISTICS OF SJ-TMOS, C-TMOS AND DT-MOS Ron,sp BV Eox-max Qgd BV2/ Ron,sp Ron,sp×Qgd tsc 2 (V) (MV/cm) (mΩ·cm ) (nC/cm2) (MW/cm2) (mΩ·nC) (µs) 1.14
162
2339
185
11
C-TMOS
1486
2.74
2.11
211
1046
445
4
DT-MOS
1554
3.07
2.07
304
1167
629
7
Eox-max at Vgs=0V, Vds=1200V.
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[1 8]
it [5] [11]
[10]
[4]
1
[6]
[7]
This work 0.1 100
1000
BV (V) Fig.11.
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4H -S iC
[4]
un ip ola rl im
un ip o la r
10
Si
Ron,sp (mΩ Ω⋅cm
2
)
lim
it
[1 7]
100
10000
Tradeoff between the breakdown voltage and the specific on-resistance in recent 4H-SiC
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simulation reports and research samples.
A feasible fabrication procedure is shown in figure 12. The deep trench is formed by ICP etching after the shallow trench in (e). A metal with high etching selectivity to 4H-SiC is
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selected for the mask layer, and it can be used for next three steps from (f) to (h). Figure 13 (a) shows the 3-D layout of SJ-TMOS, the P+ source is located in the z-direction, and it is protruded over the P-body to contact on the P+ buried layer. The schematic cross section of the face ABCD and A’B’C’D’ are plotted in figure13 (b) and (c). The P+ buried layer is well
(a) METEL
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G
SUB
SUB
SUB
SUB
(b)
(c)
(d)
(e)
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SUB
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grounded by the P+ source.
SUB
SUB
SUB
SUB
SUB
(j)
(i)
(h)
(g)
(f)
Fig.12. key fabrication process flows for the SJ-TMOS: (a) Form the P+ buried layer, (b) n-type epitaxial growth (c) form the P+, N+ sources and the P-body, (d) ICP etch to form the shallow trench, (e) ICP etch to form the deep trench, (f) vertical implantation to form the P-region at the bottom of trench, (g) tilted implantation to form the P-region along the sidewall of trench (h) fill the deep trench with SiO2, (i) thermal oxidation to form the gate oxide, (j) deposition the poly silicon and form electrodes.
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A’ ’
B’ ’
x A y D
P+
N+ P P+
B B
Poly
C
SiO22 SiO SiO2
N+ P
P+
SiO2
SiO2
N-drift D’ ’ N+
P+
Contact
C’ ’ D
(a) Fig.13.
B’ ’
A’ ’ A
C
(b)
SiO2
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Poly
(c)
(a) 3-D view of SJ-TMOS. (b) Schematic cross section of the face ABCD (c) Schematic cross
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section of the face A’B’C’D’.
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CONCLUSION
A 1200-class 4H-SiC SJ-TMOS is proposed in this paper. The TLB effectively lowers the saturation current by more than 50%, leading to the lengthened tsc of 11µs. The SJ structure reduces the on-resistance and improve the breakdown capability. The electric field in oxide is low owing to the shielding effect of the P-region and the grounded P+ buried layer. In
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addition, the SJ-TMOS also exhibits a good dynamic performance because of the low Qgd. The SJ-TMOS is more attractive and promising for the high frequency and high power
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application.
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ACCEPTED MANUSCRIPT Electronics 31.3 (2016): 2485-2495. [17] B. J. Baliga. "Power semiconductor device figure of merit for high-frequency applications". IEEE Electron Device Letters, 10.10 (1989): 455-457. [18] D. T. Morisette. "Development of robust power Schottky barrier diodes in silicon
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The three-level buffer of the proposed device lowers the saturation current and thus improves the short-circuit ruggedness.
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the superjunction structure reduces the specific on-resistance and improves the breakdown voltage.
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The P-region and the grounded P+ buried layer shield the trench and thus reduce the electric field in oxide.
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The low switching loss is caused by the low gate-to-drain charge.
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