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A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET)
Superlattices and Microstructures 86 (2015) 211–220
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A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET) S. Dash a, G.P. Mishra b,⇑ a Dept. of Electronics & Communication Engg., Device Simulation Lab, Institute of Technical Education & Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar, India b Dept. of Electronics & Instrumentation Engg., Device Simulation Lab, Institute of Technical Education & Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar, India
a r t i c l e
i n f o
Article history: Received 5 June 2015 Received in revised form 17 July 2015 Accepted 20 July 2015 Available online 21 July 2015 Keywords: CG-TFET Drain current Shortest tunneling distance Transconductance
a b s t r a c t The cylindrical gate tunnel FET (CG-TFET) is one of the potential candidates for future nano-technology, as it exhibit greater scaling capability and low subthreshold swing (SS) as compared to conventional MOSFET. In this paper, a new analytical approach is proposed to extract the gate dependent threshold voltage for CG-TFET. The potential distribution and electric field distribution in the cylindrical channel has been obtained using the 2-D Poisson’s equation which in turn computes the shortest tunneling distance and tunneling current. The threshold voltage is extracted using peak transconductance change method based on the saturation of tunneling barrier width. The impact of scaling of effective oxide thickness, cylindrical pillar diameter and gate length on the threshold voltage has been investigated. The consistency of the proposed model is validated with the TCAD simulated results. The present model can be a handful for the study of switching behavior of TFET. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction Increased leakage current (IOFF) and subthreshold swing (SS) are the two major hindrances in the downscaling process of complementary metal oxide semiconductor (CMOS) technology in the low-power applications [1–6]. Tunnel FET (TFET) is one of the emerging alternative for conventional MOSFET beyond 90 nm regime due to its low IOFF and SS below 60 mV/decade. But on the contrary it results low drain current due to the tunneling of charge carriers at the source–channel interface based on non-local Band-to-Band tunneling (BTBT) phenomena [7–10]. However a number of techniques such as bandgap engineering, gate engineering, use of compound semiconductors, use of high-k dielectric have been employed to improve the drain current in TFET structure [11–14]. Similarly different TFET models based on multi-gate structure have been developed in recent times, to improve the device performance and scaling capability [15–17]. Cylindrical gate tunnel FET (CG-TFET) provides enhanced electrostatic performance and optimum scaling capability due to its typical characteristics length [18,19]. The investigation of device performance and the scaling optimization of CG-TFET are mostly focused using TCAD simulations and experiments. But analytical models can give a brief insight for the design and fabrication of TFET devices. Barely a few numbers of analytical models have been proposed to calculate surface potential, drain current of CG-TFET [20–23]. This
⇑ Corresponding author. E-mail address: [email protected] (G.P. Mishra). http://dx.doi.org/10.1016/j.spmi.2015.07.049 0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.
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is due to the fact that, the physics related to the carrier tunneling of CG-TFET is completely different from standard CG-MOSFETs. The gate dependent threshold voltage is one of the key electrical parameters of CG-TFET, as it switches the device. In this paper, an analytical gate threshold voltage model for CG-TFET is developed based on the saturation of the shortest tunneling distance with respect to gate voltage. The threshold voltage is extracted using peak transconductance change (TC) method and a methodical comparison with the constant current (CC) method is reported. Also the effect of the variation of effective gate oxide thickness, cylindrical pillar diameter and gate length on the threshold voltage and drain current has been studied extensively. The model accuracy is validated using TCAD Sentaurus simulator [24]. To study the transport behavior of CG-TFET, non-local path BTBT model, Shockley–Read–Hall (SRH) Recombination model, band-gap narrowing concentration models, and quantum potential model are considered. 2. Analytical model and its validation 2.1. Device structure & electrostatic analysis Fig. 1 displays the structural architecture of n-channel Si based CG-TFET with 50 nm channel length (L) and 20 nm source/drain length (LS/LD). The source and drain of the model is uniformly doped with trivalent and pentavalent impurity of the order NS = ND = 1020 cm3 respectively. The gated channel region is very lightly doped with NC = 1015 cm3. The cylindrical body diameter (tsi) and Equivalent Oxide Thickness (EOT) of SiO2 dielectric layer is considered as 10 nm and 2 nm respectively. Here the work-function (Um) for the material used as metal gate contact is assumed as 4.2 eV for the model which spreads over the 50 nm effective channel. Threshold voltage is one of the significant electrical parameter of a device which influences the critical voltage values characterizing IC digital circuits. In TFET, it signifies the transition between weak tunneling and strong tunneling of charge carriers at the source–channel interface [25]. To develop the threshold voltage model of CG-TFET, we need to resolve the 2-D Poisson’s equation for the entire channel region. The electrostatic distribution and electric field along the lateral direction of N-TFET can be obtained by solving Poisson’s equation in the cylindrical coordinate system from the weak inversion (OFF-state) to the onset of the strong inversion (ON-state). This further helps us to develop the analysis of drain current using band-to-band generation rate and shortest tunneling distance. The potential distribution u(r, z) in the cylindrical channel can be realized by 2-D Poisson’s equation with parabolic approximation [1]. Here the effect of the mobile carriers and trapped charges in the oxide layer has been neglected.
1 @ @ @ 2 uðr; zÞ qNc r uðr; zÞ þ ¼ ; r @r @r @z2 si
06r6
t si 2
& 06z6L
ð1Þ
where si is the dielectric constant of silicon. The surface potential along the channel–gate dielectric interface can be obtained using the boundary conditions defined for the cylindrical structure [1] as
@ 2 us ðzÞ ðV GS V FB us ðzÞÞ qN c þ ¼ 2 @z2 si lc
ð2Þ
Here V GS and V FB represents the gate-to-source voltage and flat-band voltage respectively. The characteristics length of cylindrical gate structure (lc ) is defined as
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi u ut2 si ln 1 þ 2EOT t si t si lc ¼ 8ox
ð3Þ
Eq. (2) can be solved using the boundary conditions at the source–channel and drain–channel interface.
Fig. 1. (a) Schematic cross-sectional and (b) side-view of n-type CG-TFET.
S. Dash, G.P. Mishra / Superlattices and Microstructures 86 (2015) 211–220
us ðzÞz¼0 ¼
KT NS log q ni
us ðzÞz¼L ¼ V DS þ
213
ð4Þ
KT ND log q ni
ð5Þ
where V DS is the drain-to-source voltage, ox is the relative permittivity of SiO2, NS/ND is the doping profile of source/drain, KT q is the thermal voltage and ni is the intrinsic carrier concentration of silicon. For this model, the approximations are
NS ¼ ND ¼ N ¼ 1020 cm3
& Vt ¼
KT ¼ 0:0259 V: q
Solving Eq. (2), the surface potential in the lateral direction of cylindrical channel is found to be z lc
lz
us ðzÞ ¼ Ae þ Be c V FB V GS þ
2
qNc lc
!
si
ð6Þ
where
"
# ! 2 KT qNc lc N lL lL c c V DS þ V FB V GS þ 1e 1þe A¼ log þ q ni si 2 sinh L 1
ð7Þ
lc
B¼
1 2 sinh
" V DS þ V FB V GS þ L lc
# ! 2 KT L qN c lc lL N 1 þ e lc log ec 1 q ni si
ð8Þ
Here the electrostatic potential distribution along the z-direction is modulated by gate bias as CG-TFET is a gated P-I-N diode. The electric field along the lateral direction plays a significant role in the drain current analysis and thus in the threshold voltage extraction. This is primarily because of the maximum BTBT charge carrier flow along the z-axis of the channel [23]. The electric field distribution can be expressed within the range 0 6 z 6 L as
Ez ðr; zÞ ¼
@ us A ðlz Þ B ðlz Þ ec þ e c ¼ lc lc @z
ð9Þ
Fig. 2a and b illustrate the potential and lateral electric field distribution of n-channel CG-TFET for different gate voltages. The figure shows the improvement in surface potential with the increase in gate bias from 0.3 V to 0.5 V which is due to the enhanced gate control on the intrinsic channel. Here the drain voltage and work function of material is kept constant. The potential at the source/drain interface is dependent on built-in-potential which is controlled by the doping profile of source/drain. However the slope of the surface potential curve increases due to high gate voltage at constant VDS. This change in potential critically decides the shortest tunneling distance in the tunneling of charge carriers. The constant potential is obtained at the middle of channel for a fixed VGS as gate control becomes saturated. This leads to zero lateral electric field along the channel as shown in Fig. 2b. The model produces highest electric field at the tunneling junction (source–channel interface) for high gate voltage which on the contrary reduces the shortest tunneling distance. But at the drain end, the low-k dielectric SiO2 suppresses the ambipolar leakage conduction due to low electric field.
Fig. 2. (a) Surface potential distribution and (b) lateral electric field distribution of n-channel CG-TFET along the channel for different gate voltages.
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Fig. 3. Energy band diagram of the proposed model in (a) OFF-state (VGS = 0 V) and (b) ON-state (VGS = 1 V).
2.2. Shortest tunneling distance analysis The energy band diagram for the n-channel CG-TFET model of both OFF-state (VGS = 0 V) and ON-state (VGS = 1 V) has been presented in Fig. 3(a) and (b). It is observed that the charge carriers tunnel through the source–channel interface in the ON-state as the conduction band of channel and the valence band of source are in-line to each other [23]. This outline an inflection point in the z-axis known as shortest tunneling distance (lt) which can be modulated by gate-to-source voltage.
ðus Þv al ðzÞ i uscond ðzÞ
z¼0
¼ us ð0Þ ¼
KT NS log q ni
ð10Þ 2
z¼lt
lt lt Eg qN l ¼ us ðlt Þ þ ¼ Aelc þ Belc V FB V GS þ c c q si
! þ
Eg q
ð11Þ
where uscond ðzÞ and usv al ðzÞ denotes the potential of conduction band of channel and valence band of source for the n-channel CG-TFET model. The shortest tunneling distance can be evaluated as
lt ¼ lc loge
kþ
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! 2 k 4AB 2A
ð12Þ
where 2
k ¼ V FB V GS þ
qN c lc
si
þ
Eg KT NS log q q ni
ð13Þ
Fig. 4. Shortest tunneling distance variation w.r.t. gate voltages at constant drain voltage due to scaling of (a) effective oxide thickness and (b) Si pillar diameter.
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215
The shortest tunneling distance (lt) as a function of gate bias for different effective gate oxide thickness and silicon cylindrical pillar diameter are displayed in Fig. 4a and b. As the applied gate voltage increases past threshold value, the major charge carrier tunnel through the source–channel interface and thus reduces the shortest tunneling distance due to superior gate control. As the effective gate oxide thickness downscaled from 4 nm to 2 nm, the capacitive coupling effect between gate and channel improves which curtails the shortest tunneling distance for a constant drain voltage. Similarly lt reduces further with decrease in silicon body thickness from 14 nm to 10 nm, as the impact of gate voltage on channel increases at low tsi. The reduction in the shortest tunneling distance at constant gate bias improves tunneling current due to larger tunneling volume. Here the BTBT process is assumed to be extended up to the drain end along the channel and remain independent of the variation of device parameters. 2.3. Tunneling current and transconductance Here Kane’s nonlocal BTBT model [26] has been taken into consideration for the evaluation of tunneling current through the channel for the interval of [z1 = lt, z2] and is expressed as [17]
ID ¼ q
Z
t si 2
Z
t
2si
Eg Ak Ez ðBEkgqzÞ dz dr e qz
z2
lt
ð14Þ
where Ak and Bk are Kane’s tunneling parameters and the values taken in this model are 2.8 1019 m1/2 V5/2 s1 and 3.2 109 V/m respectively. Similarly Eg denotes the band-gap energy of silicon material and affect the shortest tunneling distance significantly. Substituting electric field distribution along z-axis in the above equation, we get
2 ID ¼ tsi Eg Ak 4
Z
z2
lt
0 1 0 1 3 qB qB Z z2 ðl1 E k Þz ðl1 þ E k Þz g g c c Ae Be @ Adz þ @ Adz5 lc z lc z lt
ð15Þ
The drain current finally can be obtained by neglecting the effect of polynomial terms within the interval of [z1 = lt, z2] and found to be
20 3 1 0 1 tsi Eg Ak 4@ A A B A Qz Qz 5 Pz2 Pz1 @qB ID ¼ 2 1 qBk k lc l1 þ l1 E E g
c
g
ð16Þ
c
where qB
qB
ð 1 E k Þz
Pz ¼
e lc
ðl1 þ E k Þz
g
z
and Q z ¼
e
g
c
ð17Þ
z
It has been observed that the coefficient P z2 Pz1 and Q z2 Q z1 . The simplified drain current is obtained by neglecting the insignificant effects of Pz2 and Q z2 as
20 1 0 13 tsi Eg Ak 4@ AP z1 A @ BQ z1 A5 þ 1 qB ID ¼ 1 k lc qB þ Ek l l E c
g
c
ð18Þ
g
The transconductance of the model can be obtained by the 1st order differentiation of drain current w.r.t. gate voltage for a constant drain voltage and is expressed as
L L Y 1 elc 1 Y 2 elc 1 dID dY 1 dY 2 þA gm ¼ ¼ þB L dV GS dV dV GS GS 2 sinh lc
ð19Þ
where
t si Eg Ak Pz1 Y1 ¼ 1 lcEqBg k
tsi Eg Ak Q z1 & Y2 ¼ 1 þ lcEqBg k
ð20Þ
Similarly the transconductance generation factor (TGF) is one of the important figure of merit of the device and is defined as the ratio of transconductance to the drain current for a fixed value of gate voltage (gm/ID). TGF also gives an idea about the gain of the device per unit power dissipation. In Fig. 5, ID VGS transfer characteristics has been shown in both linear and logarithmic scale for a constant drain voltage. The effect of scaling of gate oxide thickness and silicon cylindrical pillar diameter on drain current performance has been illustrated in Fig. 6. The current characteristics both in log scale and linear scale for constant VDS are displayed in the left and right vertical axis respectively. It is clearly evident that the drain current increases with the reduction in the gate oxide thickness and Si pillar diameter. This is due to the decrease in the shortest tunneling distance and improvement of non-local
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Fig. 5. Drain current (ID) as a function of gate voltage (VGS) for the CG-TFET model.
Fig. 6. ID VGS characteristics for various (a) effective gate oxide thickness and (b) silicon cylindrical pillar diameter at constant drain voltage.
Fig. 7. TGF as a function of gate voltage for different values of (a) effective gate oxide thickness and (b) silicon cylindrical pillar diameter at VDS = 1 V and L = 50 nm.
BTBT volume. The nonlinear current curve in CG-TFET is influenced by the variation of EOT and tsi, which is due to the variation of gate control on intrinsic region at constant drain bias. The scaling of effective gate oxide thickness and silicon cylindrical pillar diameter also results in improvement of sub-threshold swing (SS). The average sub-threshold swing improves by 9 mV/dec i.e. from 50 mV/dec to 41 mV/dec with
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217
downscaling of EOT from 4 nm to 2 nm. Similarly scaling of tsi results in decrease of SS by 5 mV/dec (from 46 mV/dec to 41 mV/dec). The above results are compared and validated with the existing experimental results [27]. Fig. 7 displays the variation of TGF w.r.t. gate voltage for various values of EOT and tsi for 50 nm gate length. It is worth noting that TGF reduces with the increase in gate voltage as TGF is maximum at the weak tunneling region and reduces faster as we approach strong tunneling of charge carriers. The above figure also illustrates the effect of downscaling of EOT and tsi on the TGF performance. The small value of gate oxide thickness (EOT = 2 nm) and Si pillar diameter (tsi = 10 nm) gives the lowest TGF at constant drain voltage which indicates that the tunneling of carriers at the interface starts for low VGS. 2.4. Threshold voltage extraction and model validation The ID VGS characteristics of CG-TFET displays the non-linear behavior which mainly controlled by narrowing the shortest tunneling distance (lt) in the ON-state as shown in Figs. 5 and 6. The shortest tunneling distance primarily varies w.r.t. applied gate voltage. However the tunneling of charge carriers in the ON-state need a minimum amount of drain voltage irrespective of gate bias which reverse bias the P-I-N diode. Threshold voltage of a tunnel FET is the gate voltage for which the shortest tunneling distance gradually starts to saturate with the applied gate bias. This is due to the saturation of narrowing of energy barrier between valence band and conduction band. The threshold voltage of conventional MOSFET can be computed using several approaches such as constant current method (CC), linear extrapolation method (LE), split C-V method (SC), Fowler and Hartstein method (FH) and transconductance peak method (TC) [28]. In constant current (CC) method the threshold voltage is the value of the gate voltage for which drain current IDcon ¼ 1013 A=lm [11,14]. But this method uses an optimized value of drain current which may not produce accurate threshold voltages for TFET models and thus carry less practical meaning [29]. The ID VGS characteristics of CG-TFET provides the value of threshold (Vth = VGS) in a graphical manner at which drain current reaches a constant value of 1013 A=lm. The threshold voltage curve is shown in Fig. 8 at a constant drain voltage which corresponds to shortest tunneling path of around 5–6 nm. In this paper, the more accurate peak transconductance change (TC) method has been used to extract the threshold voltage of the n-channel CG-TFET. In this method, the threshold voltage of CG-TFET is the value of gate voltage which corre dg m sponds to the maximum of the 1st order differentiation of transconductance dV . This threshold voltage extraction GS method detects the gate voltage where the shortest tunneling path gets saturated. Also it exhibits the transition between strong and weak controls of the tunneling energy barrier width [25]. The change in transconductance can be analytically obtained by differentiating Eq. (19) as
L L T 1 elc 1 T 2 elc 1 dg m dT 1 dT 2 ¼ þB þA L dV GS dV dV GS GS sinh lc
ð21Þ
where
2At si Eg Ak T 3 Pz1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi T1 ¼ 2 k þ k 4AB
2At si Eg Ak T 3 Q z1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi and T 2 ¼ 2 k þ k 4AB
ð22Þ
Here constant T 3 is defined as
Fig. 8. Extraction of threshold voltage of CG-TFET by peak transconductance change method for (a) VGS = 1 V and (b) VGS = 1.5 V at constant drain voltage.
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T3 ¼
4AT 4 sinh
L lc
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi L 2 þ k þ k 4AB 1 elc 8A2 sinh lLc
ð23Þ
where
2
3 L lL L lc c k sinh þ A 1 e B 1 e lc 6 7 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi T 4 ¼ 1 4 5 2 k 4AB sinh lLc
ð24Þ
However the peak value of transconductance change can be realized by finding the inflection point of the curve. The point is the byproduct of finding 1st order derivative of the result and equating to zero. The process has been illustrated in the Fig. 8 and validated by the TCAD simulator. Fig. 8 display the drain current (ID), transconductance (g m ) and change in transconductance (gm ) for the proposed model at a maximum gate voltage of 1 V and 1.5 V respectively. The transconductance and change in transconductance are obtained by the 1st order and 2nd order differentiation of drain current w.r.t. gate bias keeping drain voltage constant. Here the line represents the results of analytical threshold model and are accurately validated by the symbols, signifies TCAD simulation. Here the threshold voltage of CG-TFET is defined by the peak value of change in transconductance curve as shown in Fig. 8a and b. The TC method of extracting threshold voltage is more precise with the simulation result and is independent of gate length at constant drain voltage. Fig. 9a displays the 2nd order differentiation of drain current w.r.t. gate voltage for 50 nm channel length with different gate oxide thickness (EOT = 2 nm, 3 nm and 4 nm). The maximum value of dgm/dVGS curve indicates the threshold value of the structure. It is clearly evident that the non-linear behavior of rate of change in transconductance curve is influenced by the change in oxide thickness. The downscaling of EOT from 4 nm to 2 nm yields the reduction in shortest tunneling path and thus decrease in threshold voltage as illustrated in Fig. 9b. However the threshold voltage extracted using proposed TC method is compared with constant current method and produces results very similar to that of TCAD simulation result. The threshold voltage versus gate length at constant drain and gate voltage is shown in Fig. 10. The threshold values for different gate length are extracted using 1st order differentiation of transconductance and CC method. Here the threshold voltage extracted by the proposed TC method is 0.91 V which corresponds to the narrowing of the shortest tunneling distance and is much higher than the threshold voltage defined by the constant current method (Vth = 0.52 V at ID ¼ 1013 A=lm). The proposed results show good coincidence to that of TCAD simulation results as compared to CC approach. However the constant nature of the curve is due to the fact that the lateral electric field is maximum at the source–channel interface irrespective of gate length as shown in Fig. 2b. The threshold voltage of CG-TFET is independent of the gate length for a positive drain voltage. Fig. 11 illustrates the threshold voltage variation of n-channel CG-TFET as a function of Si pillar diameter and effective gate oxide thickness at VGS = 1.5 V and VDS = 1 V. When the Si pillar diameter is scaled down from 20 nm to 10 nm at a fixed gate length, the threshold voltage reduces linearly as the narrowing of shortest tunneling distance saturates. However the proposed method of extraction of the threshold voltage resembles with the simulated result as compared to CC method. Similarly the threshold voltage variation in CG-TFET is sensitive to the gate oxide thickness. Low Vth is obtained for EOT = 2 nm, because of the better capacitive control of the barrier width at the source–channel interface.
Fig. 9. (a) Threshold voltage extraction using TC method and (b) variation of threshold voltage for different values of effective gate oxide thickness with VGS = 1 V and VDS = 1 V.
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219
Fig. 10. Variation of threshold voltage due to change in channel length with VGS = 1 V and VDS = 1 V.
Fig. 11. Variation of threshold voltage w.r.t. (a) Si pillar diameter and (b) gate oxide thickness with L = 50 nm, VGS = 1.5 V and VDS = 1 V.
3. Conclusions In this paper, the analytical expression for the shortest tunneling distance and drain current have been derived using the solution of 2-D Poisson’s equation in the intrinsic channel. The gate threshold voltage is further extracted using proposed transconductance change method based on the saturation of shortest tunneling distance. It is clearly evident that the proposed method predicts the nature of switching behavior more precisely as compared to constant current method. However the analytical model is also able to investigate the drain current and threshold voltage w.r.t. the variation in the gate length, effective oxide thickness and silicon pillar diameter. Finally the proposed threshold voltage model for CG-TFET can provide an insight for the future TFET technology in the low power applications. References [1] A. Kranti, S. Haldar, R.S. Gupta, Analytical model for threshold voltage and I–V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET, Microelectron. Eng. 56 (2001) 241–259. [2] K.K. Young, Short-channel effect in fully-depleted SOI MOSFETs, IEEE Trans. Electron. Dev. 36 (1989) 399–402. [3] A.O. Adan, T. Naka, A. Kagisawa, H. Shimizu, SOI as a mainstream IC technology, in: Proc. of IEEE International SOI Conference, 1998, pp. 9–12. [4] C.P. Auth, J.D. Plummer, Scaling theory for cylindrical fully-depleted, surrounding gate MOSFET’s, IEEE Electron Dev. Lett. 18 (1997) 74–76. [5] J.P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008. [6] J.P. Colinge, Multiple-gate SOI MOFETs, Solid-State Electron. 48 (2004) 897–905. [7] W.Y. Choi, B.G. Park, J.D. Lee, T.J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Dev. Lett. 28 (2007) 743–745. [8] L. Lattanzio, A. Biswas, L.D. Michielis, A.M. Ionescu, Abrupt switch based on internally combined band-to-band and barrier tunneling mechanisms, Solid-State Electron. 65–66 (2011) 234–239. [9] Q. Zhang, W. Zhao, S. Alan, Low-subthreshold-swing tunnel transistors, IEEE Electron Dev. Lett. 27 (2006) 297–300.
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A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET) S. Dash a, G.P. Mishra b,⇑ a Dept. of Electronics & Communication Engg., Device Simulation Lab, Institute of Technical Education & Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar, India b Dept. of Electronics & Instrumentation Engg., Device Simulation Lab, Institute of Technical Education & Research, Siksha ‘O’ Anusandhan University, Khandagiri, Bhubaneswar, India
a r t i c l e
i n f o
Article history: Received 5 June 2015 Received in revised form 17 July 2015 Accepted 20 July 2015 Available online 21 July 2015 Keywords: CG-TFET Drain current Shortest tunneling distance Transconductance
a b s t r a c t The cylindrical gate tunnel FET (CG-TFET) is one of the potential candidates for future nano-technology, as it exhibit greater scaling capability and low subthreshold swing (SS) as compared to conventional MOSFET. In this paper, a new analytical approach is proposed to extract the gate dependent threshold voltage for CG-TFET. The potential distribution and electric field distribution in the cylindrical channel has been obtained using the 2-D Poisson’s equation which in turn computes the shortest tunneling distance and tunneling current. The threshold voltage is extracted using peak transconductance change method based on the saturation of tunneling barrier width. The impact of scaling of effective oxide thickness, cylindrical pillar diameter and gate length on the threshold voltage has been investigated. The consistency of the proposed model is validated with the TCAD simulated results. The present model can be a handful for the study of switching behavior of TFET. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction Increased leakage current (IOFF) and subthreshold swing (SS) are the two major hindrances in the downscaling process of complementary metal oxide semiconductor (CMOS) technology in the low-power applications [1–6]. Tunnel FET (TFET) is one of the emerging alternative for conventional MOSFET beyond 90 nm regime due to its low IOFF and SS below 60 mV/decade. But on the contrary it results low drain current due to the tunneling of charge carriers at the source–channel interface based on non-local Band-to-Band tunneling (BTBT) phenomena [7–10]. However a number of techniques such as bandgap engineering, gate engineering, use of compound semiconductors, use of high-k dielectric have been employed to improve the drain current in TFET structure [11–14]. Similarly different TFET models based on multi-gate structure have been developed in recent times, to improve the device performance and scaling capability [15–17]. Cylindrical gate tunnel FET (CG-TFET) provides enhanced electrostatic performance and optimum scaling capability due to its typical characteristics length [18,19]. The investigation of device performance and the scaling optimization of CG-TFET are mostly focused using TCAD simulations and experiments. But analytical models can give a brief insight for the design and fabrication of TFET devices. Barely a few numbers of analytical models have been proposed to calculate surface potential, drain current of CG-TFET [20–23]. This
⇑ Corresponding author. E-mail address: [email protected] (G.P. Mishra). http://dx.doi.org/10.1016/j.spmi.2015.07.049 0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.
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is due to the fact that, the physics related to the carrier tunneling of CG-TFET is completely different from standard CG-MOSFETs. The gate dependent threshold voltage is one of the key electrical parameters of CG-TFET, as it switches the device. In this paper, an analytical gate threshold voltage model for CG-TFET is developed based on the saturation of the shortest tunneling distance with respect to gate voltage. The threshold voltage is extracted using peak transconductance change (TC) method and a methodical comparison with the constant current (CC) method is reported. Also the effect of the variation of effective gate oxide thickness, cylindrical pillar diameter and gate length on the threshold voltage and drain current has been studied extensively. The model accuracy is validated using TCAD Sentaurus simulator [24]. To study the transport behavior of CG-TFET, non-local path BTBT model, Shockley–Read–Hall (SRH) Recombination model, band-gap narrowing concentration models, and quantum potential model are considered. 2. Analytical model and its validation 2.1. Device structure & electrostatic analysis Fig. 1 displays the structural architecture of n-channel Si based CG-TFET with 50 nm channel length (L) and 20 nm source/drain length (LS/LD). The source and drain of the model is uniformly doped with trivalent and pentavalent impurity of the order NS = ND = 1020 cm3 respectively. The gated channel region is very lightly doped with NC = 1015 cm3. The cylindrical body diameter (tsi) and Equivalent Oxide Thickness (EOT) of SiO2 dielectric layer is considered as 10 nm and 2 nm respectively. Here the work-function (Um) for the material used as metal gate contact is assumed as 4.2 eV for the model which spreads over the 50 nm effective channel. Threshold voltage is one of the significant electrical parameter of a device which influences the critical voltage values characterizing IC digital circuits. In TFET, it signifies the transition between weak tunneling and strong tunneling of charge carriers at the source–channel interface [25]. To develop the threshold voltage model of CG-TFET, we need to resolve the 2-D Poisson’s equation for the entire channel region. The electrostatic distribution and electric field along the lateral direction of N-TFET can be obtained by solving Poisson’s equation in the cylindrical coordinate system from the weak inversion (OFF-state) to the onset of the strong inversion (ON-state). This further helps us to develop the analysis of drain current using band-to-band generation rate and shortest tunneling distance. The potential distribution u(r, z) in the cylindrical channel can be realized by 2-D Poisson’s equation with parabolic approximation [1]. Here the effect of the mobile carriers and trapped charges in the oxide layer has been neglected.
1 @ @ @ 2 uðr; zÞ qNc r uðr; zÞ þ ¼ ; r @r @r @z2 si
06r6
t si 2
& 06z6L
ð1Þ
where si is the dielectric constant of silicon. The surface potential along the channel–gate dielectric interface can be obtained using the boundary conditions defined for the cylindrical structure [1] as
@ 2 us ðzÞ ðV GS V FB us ðzÞÞ qN c þ ¼ 2 @z2 si lc
ð2Þ
Here V GS and V FB represents the gate-to-source voltage and flat-band voltage respectively. The characteristics length of cylindrical gate structure (lc ) is defined as
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi u ut2 si ln 1 þ 2EOT t si t si lc ¼ 8ox
ð3Þ
Eq. (2) can be solved using the boundary conditions at the source–channel and drain–channel interface.
Fig. 1. (a) Schematic cross-sectional and (b) side-view of n-type CG-TFET.
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us ðzÞz¼0 ¼
KT NS log q ni
us ðzÞz¼L ¼ V DS þ
213
ð4Þ
KT ND log q ni
ð5Þ
where V DS is the drain-to-source voltage, ox is the relative permittivity of SiO2, NS/ND is the doping profile of source/drain, KT q is the thermal voltage and ni is the intrinsic carrier concentration of silicon. For this model, the approximations are
NS ¼ ND ¼ N ¼ 1020 cm3
& Vt ¼
KT ¼ 0:0259 V: q
Solving Eq. (2), the surface potential in the lateral direction of cylindrical channel is found to be z lc
lz
us ðzÞ ¼ Ae þ Be c V FB V GS þ
2
qNc lc
!
si
ð6Þ
where
"
# ! 2 KT qNc lc N lL lL c c V DS þ V FB V GS þ 1e 1þe A¼ log þ q ni si 2 sinh L 1
ð7Þ
lc
B¼
1 2 sinh
" V DS þ V FB V GS þ L lc
# ! 2 KT L qN c lc lL N 1 þ e lc log ec 1 q ni si
ð8Þ
Here the electrostatic potential distribution along the z-direction is modulated by gate bias as CG-TFET is a gated P-I-N diode. The electric field along the lateral direction plays a significant role in the drain current analysis and thus in the threshold voltage extraction. This is primarily because of the maximum BTBT charge carrier flow along the z-axis of the channel [23]. The electric field distribution can be expressed within the range 0 6 z 6 L as
Ez ðr; zÞ ¼
@ us A ðlz Þ B ðlz Þ ec þ e c ¼ lc lc @z
ð9Þ
Fig. 2a and b illustrate the potential and lateral electric field distribution of n-channel CG-TFET for different gate voltages. The figure shows the improvement in surface potential with the increase in gate bias from 0.3 V to 0.5 V which is due to the enhanced gate control on the intrinsic channel. Here the drain voltage and work function of material is kept constant. The potential at the source/drain interface is dependent on built-in-potential which is controlled by the doping profile of source/drain. However the slope of the surface potential curve increases due to high gate voltage at constant VDS. This change in potential critically decides the shortest tunneling distance in the tunneling of charge carriers. The constant potential is obtained at the middle of channel for a fixed VGS as gate control becomes saturated. This leads to zero lateral electric field along the channel as shown in Fig. 2b. The model produces highest electric field at the tunneling junction (source–channel interface) for high gate voltage which on the contrary reduces the shortest tunneling distance. But at the drain end, the low-k dielectric SiO2 suppresses the ambipolar leakage conduction due to low electric field.
Fig. 2. (a) Surface potential distribution and (b) lateral electric field distribution of n-channel CG-TFET along the channel for different gate voltages.
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Fig. 3. Energy band diagram of the proposed model in (a) OFF-state (VGS = 0 V) and (b) ON-state (VGS = 1 V).
2.2. Shortest tunneling distance analysis The energy band diagram for the n-channel CG-TFET model of both OFF-state (VGS = 0 V) and ON-state (VGS = 1 V) has been presented in Fig. 3(a) and (b). It is observed that the charge carriers tunnel through the source–channel interface in the ON-state as the conduction band of channel and the valence band of source are in-line to each other [23]. This outline an inflection point in the z-axis known as shortest tunneling distance (lt) which can be modulated by gate-to-source voltage.
ðus Þv al ðzÞ i uscond ðzÞ
z¼0
¼ us ð0Þ ¼
KT NS log q ni
ð10Þ 2
z¼lt
lt lt Eg qN l ¼ us ðlt Þ þ ¼ Aelc þ Belc V FB V GS þ c c q si
! þ
Eg q
ð11Þ
where uscond ðzÞ and usv al ðzÞ denotes the potential of conduction band of channel and valence band of source for the n-channel CG-TFET model. The shortest tunneling distance can be evaluated as
lt ¼ lc loge
kþ
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! 2 k 4AB 2A
ð12Þ
where 2
k ¼ V FB V GS þ
qN c lc
si
þ
Eg KT NS log q q ni
ð13Þ
Fig. 4. Shortest tunneling distance variation w.r.t. gate voltages at constant drain voltage due to scaling of (a) effective oxide thickness and (b) Si pillar diameter.
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215
The shortest tunneling distance (lt) as a function of gate bias for different effective gate oxide thickness and silicon cylindrical pillar diameter are displayed in Fig. 4a and b. As the applied gate voltage increases past threshold value, the major charge carrier tunnel through the source–channel interface and thus reduces the shortest tunneling distance due to superior gate control. As the effective gate oxide thickness downscaled from 4 nm to 2 nm, the capacitive coupling effect between gate and channel improves which curtails the shortest tunneling distance for a constant drain voltage. Similarly lt reduces further with decrease in silicon body thickness from 14 nm to 10 nm, as the impact of gate voltage on channel increases at low tsi. The reduction in the shortest tunneling distance at constant gate bias improves tunneling current due to larger tunneling volume. Here the BTBT process is assumed to be extended up to the drain end along the channel and remain independent of the variation of device parameters. 2.3. Tunneling current and transconductance Here Kane’s nonlocal BTBT model [26] has been taken into consideration for the evaluation of tunneling current through the channel for the interval of [z1 = lt, z2] and is expressed as [17]
ID ¼ q
Z
t si 2
Z
t
2si
Eg Ak Ez ðBEkgqzÞ dz dr e qz
z2
lt
ð14Þ
where Ak and Bk are Kane’s tunneling parameters and the values taken in this model are 2.8 1019 m1/2 V5/2 s1 and 3.2 109 V/m respectively. Similarly Eg denotes the band-gap energy of silicon material and affect the shortest tunneling distance significantly. Substituting electric field distribution along z-axis in the above equation, we get
2 ID ¼ tsi Eg Ak 4
Z
z2
lt
0 1 0 1 3 qB qB Z z2 ðl1 E k Þz ðl1 þ E k Þz g g c c Ae Be @ Adz þ @ Adz5 lc z lc z lt
ð15Þ
The drain current finally can be obtained by neglecting the effect of polynomial terms within the interval of [z1 = lt, z2] and found to be
20 3 1 0 1 tsi Eg Ak 4@ A A B A Qz Qz 5 Pz2 Pz1 @qB ID ¼ 2 1 qBk k lc l1 þ l1 E E g
c
g
ð16Þ
c
where qB
qB
ð 1 E k Þz
Pz ¼
e lc
ðl1 þ E k Þz
g
z
and Q z ¼
e
g
c
ð17Þ
z
It has been observed that the coefficient P z2 Pz1 and Q z2 Q z1 . The simplified drain current is obtained by neglecting the insignificant effects of Pz2 and Q z2 as
20 1 0 13 tsi Eg Ak 4@ AP z1 A @ BQ z1 A5 þ 1 qB ID ¼ 1 k lc qB þ Ek l l E c
g
c
ð18Þ
g
The transconductance of the model can be obtained by the 1st order differentiation of drain current w.r.t. gate voltage for a constant drain voltage and is expressed as
L L Y 1 elc 1 Y 2 elc 1 dID dY 1 dY 2 þA gm ¼ ¼ þB L dV GS dV dV GS GS 2 sinh lc
ð19Þ
where
t si Eg Ak Pz1 Y1 ¼ 1 lcEqBg k
tsi Eg Ak Q z1 & Y2 ¼ 1 þ lcEqBg k
ð20Þ
Similarly the transconductance generation factor (TGF) is one of the important figure of merit of the device and is defined as the ratio of transconductance to the drain current for a fixed value of gate voltage (gm/ID). TGF also gives an idea about the gain of the device per unit power dissipation. In Fig. 5, ID VGS transfer characteristics has been shown in both linear and logarithmic scale for a constant drain voltage. The effect of scaling of gate oxide thickness and silicon cylindrical pillar diameter on drain current performance has been illustrated in Fig. 6. The current characteristics both in log scale and linear scale for constant VDS are displayed in the left and right vertical axis respectively. It is clearly evident that the drain current increases with the reduction in the gate oxide thickness and Si pillar diameter. This is due to the decrease in the shortest tunneling distance and improvement of non-local
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Fig. 5. Drain current (ID) as a function of gate voltage (VGS) for the CG-TFET model.
Fig. 6. ID VGS characteristics for various (a) effective gate oxide thickness and (b) silicon cylindrical pillar diameter at constant drain voltage.
Fig. 7. TGF as a function of gate voltage for different values of (a) effective gate oxide thickness and (b) silicon cylindrical pillar diameter at VDS = 1 V and L = 50 nm.
BTBT volume. The nonlinear current curve in CG-TFET is influenced by the variation of EOT and tsi, which is due to the variation of gate control on intrinsic region at constant drain bias. The scaling of effective gate oxide thickness and silicon cylindrical pillar diameter also results in improvement of sub-threshold swing (SS). The average sub-threshold swing improves by 9 mV/dec i.e. from 50 mV/dec to 41 mV/dec with
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217
downscaling of EOT from 4 nm to 2 nm. Similarly scaling of tsi results in decrease of SS by 5 mV/dec (from 46 mV/dec to 41 mV/dec). The above results are compared and validated with the existing experimental results [27]. Fig. 7 displays the variation of TGF w.r.t. gate voltage for various values of EOT and tsi for 50 nm gate length. It is worth noting that TGF reduces with the increase in gate voltage as TGF is maximum at the weak tunneling region and reduces faster as we approach strong tunneling of charge carriers. The above figure also illustrates the effect of downscaling of EOT and tsi on the TGF performance. The small value of gate oxide thickness (EOT = 2 nm) and Si pillar diameter (tsi = 10 nm) gives the lowest TGF at constant drain voltage which indicates that the tunneling of carriers at the interface starts for low VGS. 2.4. Threshold voltage extraction and model validation The ID VGS characteristics of CG-TFET displays the non-linear behavior which mainly controlled by narrowing the shortest tunneling distance (lt) in the ON-state as shown in Figs. 5 and 6. The shortest tunneling distance primarily varies w.r.t. applied gate voltage. However the tunneling of charge carriers in the ON-state need a minimum amount of drain voltage irrespective of gate bias which reverse bias the P-I-N diode. Threshold voltage of a tunnel FET is the gate voltage for which the shortest tunneling distance gradually starts to saturate with the applied gate bias. This is due to the saturation of narrowing of energy barrier between valence band and conduction band. The threshold voltage of conventional MOSFET can be computed using several approaches such as constant current method (CC), linear extrapolation method (LE), split C-V method (SC), Fowler and Hartstein method (FH) and transconductance peak method (TC) [28]. In constant current (CC) method the threshold voltage is the value of the gate voltage for which drain current IDcon ¼ 1013 A=lm [11,14]. But this method uses an optimized value of drain current which may not produce accurate threshold voltages for TFET models and thus carry less practical meaning [29]. The ID VGS characteristics of CG-TFET provides the value of threshold (Vth = VGS) in a graphical manner at which drain current reaches a constant value of 1013 A=lm. The threshold voltage curve is shown in Fig. 8 at a constant drain voltage which corresponds to shortest tunneling path of around 5–6 nm. In this paper, the more accurate peak transconductance change (TC) method has been used to extract the threshold voltage of the n-channel CG-TFET. In this method, the threshold voltage of CG-TFET is the value of gate voltage which corre dg m sponds to the maximum of the 1st order differentiation of transconductance dV . This threshold voltage extraction GS method detects the gate voltage where the shortest tunneling path gets saturated. Also it exhibits the transition between strong and weak controls of the tunneling energy barrier width [25]. The change in transconductance can be analytically obtained by differentiating Eq. (19) as
L L T 1 elc 1 T 2 elc 1 dg m dT 1 dT 2 ¼ þB þA L dV GS dV dV GS GS sinh lc
ð21Þ
where
2At si Eg Ak T 3 Pz1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi T1 ¼ 2 k þ k 4AB
2At si Eg Ak T 3 Q z1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi and T 2 ¼ 2 k þ k 4AB
ð22Þ
Here constant T 3 is defined as
Fig. 8. Extraction of threshold voltage of CG-TFET by peak transconductance change method for (a) VGS = 1 V and (b) VGS = 1.5 V at constant drain voltage.
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T3 ¼
4AT 4 sinh
L lc
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi L 2 þ k þ k 4AB 1 elc 8A2 sinh lLc
ð23Þ
where
2
3 L lL L lc c k sinh þ A 1 e B 1 e lc 6 7 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi T 4 ¼ 1 4 5 2 k 4AB sinh lLc
ð24Þ
However the peak value of transconductance change can be realized by finding the inflection point of the curve. The point is the byproduct of finding 1st order derivative of the result and equating to zero. The process has been illustrated in the Fig. 8 and validated by the TCAD simulator. Fig. 8 display the drain current (ID), transconductance (g m ) and change in transconductance (gm ) for the proposed model at a maximum gate voltage of 1 V and 1.5 V respectively. The transconductance and change in transconductance are obtained by the 1st order and 2nd order differentiation of drain current w.r.t. gate bias keeping drain voltage constant. Here the line represents the results of analytical threshold model and are accurately validated by the symbols, signifies TCAD simulation. Here the threshold voltage of CG-TFET is defined by the peak value of change in transconductance curve as shown in Fig. 8a and b. The TC method of extracting threshold voltage is more precise with the simulation result and is independent of gate length at constant drain voltage. Fig. 9a displays the 2nd order differentiation of drain current w.r.t. gate voltage for 50 nm channel length with different gate oxide thickness (EOT = 2 nm, 3 nm and 4 nm). The maximum value of dgm/dVGS curve indicates the threshold value of the structure. It is clearly evident that the non-linear behavior of rate of change in transconductance curve is influenced by the change in oxide thickness. The downscaling of EOT from 4 nm to 2 nm yields the reduction in shortest tunneling path and thus decrease in threshold voltage as illustrated in Fig. 9b. However the threshold voltage extracted using proposed TC method is compared with constant current method and produces results very similar to that of TCAD simulation result. The threshold voltage versus gate length at constant drain and gate voltage is shown in Fig. 10. The threshold values for different gate length are extracted using 1st order differentiation of transconductance and CC method. Here the threshold voltage extracted by the proposed TC method is 0.91 V which corresponds to the narrowing of the shortest tunneling distance and is much higher than the threshold voltage defined by the constant current method (Vth = 0.52 V at ID ¼ 1013 A=lm). The proposed results show good coincidence to that of TCAD simulation results as compared to CC approach. However the constant nature of the curve is due to the fact that the lateral electric field is maximum at the source–channel interface irrespective of gate length as shown in Fig. 2b. The threshold voltage of CG-TFET is independent of the gate length for a positive drain voltage. Fig. 11 illustrates the threshold voltage variation of n-channel CG-TFET as a function of Si pillar diameter and effective gate oxide thickness at VGS = 1.5 V and VDS = 1 V. When the Si pillar diameter is scaled down from 20 nm to 10 nm at a fixed gate length, the threshold voltage reduces linearly as the narrowing of shortest tunneling distance saturates. However the proposed method of extraction of the threshold voltage resembles with the simulated result as compared to CC method. Similarly the threshold voltage variation in CG-TFET is sensitive to the gate oxide thickness. Low Vth is obtained for EOT = 2 nm, because of the better capacitive control of the barrier width at the source–channel interface.
Fig. 9. (a) Threshold voltage extraction using TC method and (b) variation of threshold voltage for different values of effective gate oxide thickness with VGS = 1 V and VDS = 1 V.
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Fig. 10. Variation of threshold voltage due to change in channel length with VGS = 1 V and VDS = 1 V.
Fig. 11. Variation of threshold voltage w.r.t. (a) Si pillar diameter and (b) gate oxide thickness with L = 50 nm, VGS = 1.5 V and VDS = 1 V.
3. Conclusions In this paper, the analytical expression for the shortest tunneling distance and drain current have been derived using the solution of 2-D Poisson’s equation in the intrinsic channel. The gate threshold voltage is further extracted using proposed transconductance change method based on the saturation of shortest tunneling distance. It is clearly evident that the proposed method predicts the nature of switching behavior more precisely as compared to constant current method. However the analytical model is also able to investigate the drain current and threshold voltage w.r.t. the variation in the gate length, effective oxide thickness and silicon pillar diameter. Finally the proposed threshold voltage model for CG-TFET can provide an insight for the future TFET technology in the low power applications. References [1] A. Kranti, S. Haldar, R.S. Gupta, Analytical model for threshold voltage and I–V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET, Microelectron. Eng. 56 (2001) 241–259. [2] K.K. Young, Short-channel effect in fully-depleted SOI MOSFETs, IEEE Trans. Electron. Dev. 36 (1989) 399–402. [3] A.O. Adan, T. Naka, A. Kagisawa, H. Shimizu, SOI as a mainstream IC technology, in: Proc. of IEEE International SOI Conference, 1998, pp. 9–12. [4] C.P. Auth, J.D. Plummer, Scaling theory for cylindrical fully-depleted, surrounding gate MOSFET’s, IEEE Electron Dev. Lett. 18 (1997) 74–76. [5] J.P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008. [6] J.P. Colinge, Multiple-gate SOI MOFETs, Solid-State Electron. 48 (2004) 897–905. [7] W.Y. Choi, B.G. Park, J.D. Lee, T.J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Dev. Lett. 28 (2007) 743–745. [8] L. Lattanzio, A. Biswas, L.D. Michielis, A.M. Ionescu, Abrupt switch based on internally combined band-to-band and barrier tunneling mechanisms, Solid-State Electron. 65–66 (2011) 234–239. [9] Q. Zhang, W. Zhao, S. Alan, Low-subthreshold-swing tunnel transistors, IEEE Electron Dev. Lett. 27 (2006) 297–300.
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