Drain current model for a gate all around (GAA) p–n–p–n tunnel FET

Microelectronics Journal 44 (2013) 479–488

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Drain current model for a gate all around (GAA) p–n–p–n tunnel FET Rakhi Narang a, Manoj Saxena b, R.S. Gupta c, Mridula Gupta a,n a b c

Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus, Benito Juarez Road, New Delhi 110021, India Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, Karampura, New Delhi 110015, India. Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, Sector-22, Rohini, Delhi 110086, India.

art ic l e i nf o

a b s t r a c t

Article history: Received 21 November 2012 Received in revised form 29 March 2013 Accepted 4 April 2013 Available online 2 May 2013

A two dimensional drain current model has been proposed for a gate all around silicon p–n–p–n (pocket doped or tunnel source) tunnel field effect transistor (TFET) including the influence of drain voltage and source/drain depletion widths. The results extracted through numerical simulations have been used to obtain a semi empirical formulation of tunnel barrier width (LBW) which captures the dependence of gate voltage, drain voltage, and geometrical parameters (radii (R) and gate oxide thickness (tox)). The model is then used for evaluating various electrical parameters such as: drain current Ids, sub-threshold swing (SS), trans-conductance (gm), and device efficiency (gm/Ids). The impact of scaling R and tox on the above mentioned parameters have also been investigated. Moreover, the model depicts the influence of pocket doping and pocket width (which are crucial parameters for optimization of p–n–p–n TFET performance) on the energy band profile of a p–n–p–n TFET very well. The modeled results are in good agreement with the device simulation results. & 2013 Elsevier Ltd. All rights reserved.

Keywords: Barrier width Device simulation Gate all around (GAA) Pocket doped p–n–p–n Tunnel field effect transistor (TFET)

1. Introduction The potential of TFET as a device capable of either replacing MOSFET or working along with MOSFET to form hybrid circuitry and thus providing power saving has been demonstrated both experimentally and through computational/numerical simulations [1–3]. Recently, there have been a large number of experimental reports on TFET, with the scaling reaching up to the sub 60 nm gate length [4]. However, the innovations and efforts are still lacking in the domain of finding compact analytical solutions to model TFET. It has already been reported in previous studies that the compact analytical model is not available for a TFET [5] and thus to perform circuit simulation for TFET based devices the table look up approaches are generally used. In 2009, Hong et al. had reported a SPICE behavioral model for TFET by fitting the I–V and C–V characteristics and employing nearly 20 odd parameters [6]. This behavioral model is based on empirical equations which are not easily scalable when device dimensions are changed. The current characteristics for a fixed gate length and oxide thickness i.e. 50 nm and 0.8 nm, respectively, are directly fitted with mathematical expressions to describe the behavior of the device. There are few models reported for TFET till date, some of them are 1-D [7], does not take into account the effect of drain bias [8]. A pseudo 2D model was reported which takes into account the drain n

Corresponding author. Tel.: +91 11 2411 5580; fax: +91 11 2411 0606. E-mail addresses: [email protected] (R. Narang), [email protected] (M. Saxena), [email protected] (R.S. Gupta), [email protected], [email protected] (M. Gupta). 0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.04.002

voltage influence [9]. Most of the models available are for single gate SOI architecture [10–12] and double gate geometry [13,14] p–i–n TFET. Moreover, the electrostatics of the TFET using analytical models has been exhaustively studied, but there is a dire need for a complete model working fairly well for a large operating voltage range. Most of the models are accurate in predicting the impact of gate voltage on the device electrostatics, but the impact of drain voltage which also plays a crucial role in lowering the barrier width of the tunnel junction especially at scaled dimensions is still not accurately captured. Thus, there is an immediate requirement for developing compact analytical model for TFET which does not involve too many fitting parameter and is applicable for wide operating voltage range. This work is an attempt to develop a simple, device physics based compact analytical model for a pocket doped gate all around (GAA) silicon p–n–p–n TFET. The GAA geometry is explored for a p–n–p–n TFET architecture keeping in view that there are only a few theoretical investigation studies available [8]. Boucart and Ionescu [15] predicted through simulations that the energy barrier width narrowing in case of a TFET to be a complex function of both gate and drain voltage. In order to capture this unique effect we emphasize on developing gate voltage, drain voltage and geometrical parameter (radii (R) and gate oxide thickness (tox)) dependent semi empirical expression of tunnel barrier width. This would then be beneficial in predicting accurately the current-voltage characteristics over a wide voltage range (both Vgs and Vds). Thus, in the present work, a physics based approach is considered, where, initially the device electrostatics is developed by solving Poisson's equation. A semi-empirical expression for barrier width incorporating

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the impact of drain voltage (Vds) dependence and device dimensions (R, tox) is derived. The main purpose of deriving expression of barrier width is that, it is a physical quantity and is an integral and crucial parameter in determining the device characteristics of TFET. The model has been verified by scaling the radii in the range of 6.5 nm to 10 nm, gate oxide thickness from 4 nm to 2 nm for a channel length of 45 nm and is continuous and predicts very well the sub-threshold swing (SS), trans-conductance gm, (first order derivatives of drain current) and device efficiency (gm/Ids). Moreover, the model can also be extended for low bandgap, homo and hetero-junction TFET by modifying the boundary conditions appropriately, although it is beyond the scope of this work.

2. Device architecture, simulation and calibration The structure considered in this study is a Si based gate all around (GAA) pocket doped (also known as p–n–p–n) TFET as shown in Fig. 1 (a and b). The non local band-to-band tunneling (BTBT) model available in ATLAS 2D [16] has been calibrated [17] utilizing the experimental results of a double gate Si p–n–p–n TFET [18] recently reported by Tura et al. It is to be noted that the experimental p–n–p–n TFET has Tox ¼6.6 nm, Lg ¼90 nm and silicon channel thickness of nearly 100 nm. Due to the sub-optimal Tox/Lg ratio¼6.6 nm/90 nm and the presence of oxygen impurities the sub-threshold swing of the experimental device used for calibration is quite high ( 200 mV/dec). However, the device dimensions used for modeling and simulation are scaled in comparison to the experimental device, which results in lower sub-threshold swings.” For calibration, the effective mass parameters me.tunnel (relative effective mass of electron) and mh.tunnel (relative effective mass of hole) were adjusted, since the tunneling probability depends exponentially on these parameters. The best fit with the experimental data is obtained for me.tunnel ¼0.42 and mh. tunnel ¼0.67. These calibrated tunneling parameters are then used in the model and simulations. The physical models activated during simulation are as follows: Shockley Read Hall recombination model, concentration and field-dependent mobility model and Fermi Dirac statistics. The source and drain doping is kept asymmetric to suppress the ambipolar characteristics and in order

to take into account the effect of lower drain doping in the modeling scheme as will be discussed in the next section.

3. Model formulation 3.1. Surface potential, electric field and energy band diagram The device electrostatics is developed by solving Poisson's equation in source (p+) (region I), pocket (n+) (region II), channel (intrinsic) (region III) and drain (n+) (region IV) neglecting the influence of mobile charges. The relevance of obtaining solution in the drain region is to take into account the effect of drain doping, which is a crucial parameter in case of TFET, to curb the ambipolarity [19]. Since source is always taken to be degenerately doped (for efficient TFET operation), so the depletion width in the source is considered to be only doping dependent, while the effect of Vgs is incorporated in the drain depletion width through fringing field effect [9]. The potential profile is assumed to be parabolic for the fully depleted silicon along the radial direction [20–21].
 qN j 1 ∂ r ∂Ψ ðr; yÞ ∂2 Ψ ðr; yÞ þ ¼ ð1Þ r ∂r ∂r εSi ∂y2 where NI ¼Na (p+ source), NII ¼−Nh (n+ pocket), NIII ¼ Nch (lightly p type channel), NIV ¼ −Nd (n+ drain) and εSi is permittivity of Silicon channel. Ψ j ðr; yÞ ¼ P 1j ðyÞ þ P 2j ðyÞ r þ P 3j ðyÞ r 2

ð2Þ

where j¼ 1, 2, 3, 4 depending on the region I, II, III, IV, respectively. The following boundary conditions are applied to solve the coefficients P1j, P2j and P3j. 1) The surface potential is only ‘y’ dependent   ¼ Ψ sj ðyÞ Ψ j ðr; yÞ r¼R

2) Electric field at the center of the channel is zero ∂Ψ ðr; yÞ  ¼0  ∂r r¼0

ð3aÞ

ð3bÞ

Fig. 1. (a) GAA p–n–p–n TFET architecture (b) two dimensional cross section view with the co-ordinate system (c) barrier width (LBW) and tunneling volume (shaded region) across which electron tunneling takes place. Device parameters: gate oxide thickness (tox) ¼ 3 nm of SiO2, channel length (Lch) ¼45 nm, channel radius (R) ¼ 6.5 nm to 10 nm, pocket width (Lh) ¼5 nm, source doping (Na) ¼1020 cm−3, pocket doping (Nh) ¼ 2  1019 cm−3, drain doping (Nd) ¼ 5  1018 cm−3, gate metal work function Φm ¼ 4.5 eV.

R. Narang et al. / Microelectronics Journal 44 (2013) 479–488

3) Electric field at the Si/SiO2 interface is continuous and is given by  Cj  ∂Ψ ðr; yÞ  ¼ V gs −V f b −Ψ sj ðyÞ ð3cÞ  ∂r r¼R εSi

where Vfb is the flatband voltage (Vfb ¼Φm−ΦSi with Φm is gate metal work-function and ΦSi is silicon channel work-function), Cj is the region dependent capacitance. C 2 ¼ C 3 ¼ C ox ¼

ε  ox  C 1 ¼ C 4 ¼ ð2=πÞ C 2 R ln 1 þ tRox

ð4Þ

where εox is gate oxide (SiO2) permittivity, tox is gate oxide thickness and (2/π) factor in C1 and C4 accounts for the fringing field effect of gate voltage on the source and drain depletion regions [9]. Applying the boundary conditions we get: P 2j ðyÞ ¼ 0

ð5aÞ

Ψ sj ðyÞ ¼ P 1j ðyÞ þ P 3j ðyÞ R2

ð5bÞ

P 3j ðyÞ ¼

 Cj  V gs −V f b −Ψ sj ðyÞ 2R εSi

ð5cÞ

LDDW

481

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffi 2εSi ðV bi;d þ V ds Þ 2εSi η3 ¼ − qN d q Nd

are the extension of depletion width inside source and drain respectively. LSDW is evaluated by applying p–n junction analysis at source/n+ pocket and assuming negligible impact of Vgs (because of high source doping). LDDW is determined by employing the diode analysis [22]. The amount of voltage drop across the channel/drain junction (i.e. potential difference between the channel region due to the gate voltages (η3 ) and at the drain end (Vbid+Vds)) is used to evaluate the depletion width extension inside the drain region LDDW. The lateral and transverse electric fields are given as: 2-D transverse electric field Er;j ðr; yÞ ¼ 2 r P 3j ðyÞ;

j ¼ 1; 2; …; 4

ð9aÞ

Lateral surface electric field is given as: Esy;j ¼ λj Aj eλj y −λj Bj e−λj y ;

j ¼ 1; 2; …; 4

ð9bÞ

2-D lateral electric field Ey;j ðr; yÞ ¼ −

dðΨ j ðr; yÞÞ ; dy

j ¼ 1; 2; …; 4

ð9cÞ

Substituting (5) in (2), and then putting (2) in (1), we get 1D differential equation for surface potential given as 3.2. Drain current formulation

2

d Ψ sj ðyÞ 2 q Nj 2 −λj Ψ sj ðyÞ ¼ −λj ðV gs −V f b Þ εSi dy2

ð6Þ

where λ2j ¼

2C j RεSi

and

ηj ¼

qN j 2 −λj ðV gs −V f b Þ εSi

The solution for (6) is given as Ψ sj ðyÞ ¼ Aj eλj y þ Bj e−λj y −

ηj λ2j

;

j ¼ 1; 2; 3; 4

ð7Þ

Now, using the following boundary conditions at the interface of each region and to determine Aj and Bj (complete solution is given in Appendix I). Ψ s1 ðy ¼ 0Þ ¼ V bi;s Ψ s4 ðy ¼ LSDW þ Lh þ Lch þ LDDW Þ ¼ V bi;d þV ds at the depletion width edge of source and drain.



 kT Nd kT Na ln ln V bi;d ¼ V bi;s ¼ − q q ni ni are the built-in potential of drain and source region, respectively. And   Ψ s1 ðyÞ ¼ Ψ s2 ðyÞ y ¼ LSDW

dΨ s1 ðyÞ dΨ s2 ðyÞ  ¼  dy dy y ¼ LSDW   Ψ s2 ðyÞ ¼ Ψ s3 ðyÞ y ¼ LSDW þLh

dΨ s2 ðyÞ dΨ s3 ðyÞ  ¼  dy dy y ¼ LSDW þLh   Ψ s3 ðyÞ ¼ Ψ s4 ðyÞ y ¼ LSDW þLh þLch

dΨ s3 ðyÞ dΨ s4 ðyÞ  ¼  dy dy y ¼ LSDW þLh þLch where LSDW

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2εSi N h ðκT=qÞðlnðNa Nh Þ=n2i Þ ¼ q N a ðNa þ Nh Þ

ð8Þ

For evaluating drain current, the well known Kane's formulation [23] is used to determine generation rate which is integrated over volume to obtain tunneling current. In this case the barrier width has a crucial role in determining the magnitude of tunneling current. The generation rate is integrated over a small cylindrical volume (¼ π  R2  LBW′) at the tunneling junction formed by barrier width, LBW (also termed as tunneling length [24] or tunnel path [25]) (i.e. y direction), radii (i.e. r direction) and width (angular direction) as shown in Fig. 1(c). But it has been noticed that the effect of gate voltage on barrier width narrowing is captured very well through the energy band, but the effect of drain voltage is not correctly accounted for and thus the current characteristics deviate for the lower drain bias. The amount of drain voltage that appears at the tunneling junction and hence influences the barrier width is dependent on the channel resistance (which is controlled by gate voltage, Vgs) [26]. The barrier width in the present case is derived using the energy band diagram at the maximum electric field point which occurs at E¼ 0 as depicted in Fig. 2. When the conduction band of channel region gets aligned with the valence band of the source region, the corresponding gate voltage is defined as the Vonset. For Vgs 4Vonset tunneling probability increases and BTBT current starts flowing, and for Vgs oVonset the tunneling probability is assumed to be negligible. The lateral distance between the two bands as depicted in Fig. 2 is defined as the tunnel barrier width (LBW). LBW will keep on decreasing as the band bending continues due to the increasing applied gate voltage till it gets minimized.

3.2.1. Bias and geometrical parameter dependent barrier width formulation In order to incorporate the contribution of drain voltage on source/channel tunnel junction, the methodology of fitting (generally used for the development of compact models) is used. Moreover, the impact of geometrical parameters (i.e. radii, gate oxide thickness, tox) have also been incorporated. The step wise procedure for obtaining accurate barrier width formulation is

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Fig. 2. Graphical depiction of tunneling barrier width (LBW) from the energy band diagram at different gate bias conditions (a) off state, no band-to-band tunneling and , (b) alignment of VB of source with CB of channel at Vonset and (c) gate bias higher than Vonset and appreciable BTBT taking place defined as on state.

described below including the impact of Vgs, Vds and geometrical parameters (i.e. radii (R), gate oxide thickness (tox)).

14

Step 1: The analytical drain current values are fitted with simulated drain current values by adjusting LBW through parameter ‘αBW’ (Eq. (10)) for wide operating range of Vds (0.1 to 1 V) and Vgs (from Vonset to 1.5 V) and a range of radii (6.5 nm to 10 nm) and gate oxide thickness, tox (2 nm to 4 nm) for a given channel length (45 nm).

12

LBW αBW V ds

ð10Þ

where LBW is the calculated tunnel barrier width, which does not capture the effect of Vds, LBW ′ is the fitted tunnel barrier width which accounts for the impact of Vds as well as the device geometry parameters (i.e. radii (R), gate oxide thickness (tox)). This results in formulation of an array of αBW(i, j) values (Eq. (11)) for a range of Vgs (Vonset to 1.5 V) (representing i) and Vds (0.1 V to 1 V) (representing j) for a particular radius (R), oxide thickness (tox) and channel length (Lch).

Vds increasing

from 0.1 V to 1V 8 αBW

LBW ′ ¼

10

6 4 2 0 0.4

0.6

0.8

1 Vgs (V)

1.2

1.4

Fig. 3. Dependence of gate and drain voltage on αBW .

ð11Þ

Step 2: The αBWði;jÞ value varies with Vgs as ‘i’ varies from 1 to 12 i.e. for Vgs ¼0.4 V to 1.5 V for a particular j (i.e. Vds) as shown in Fig. 3. The Vgs dependence of αBWði;jÞ can be represented in the form of an equation given as:
 V gs αBWj ¼ Aj þ Bj exp − ð12Þ Cj Eq. (12), which represents the Vgs dependence on αBWj is chosen such that it fits the trend for all Vds range (j¼1 to 10 corresponding to Vds ¼ 0.1 V to 1 V). Step 3: The coefficients of Eq. (12) i.e. Aj, Bj and Cj are Vds dependent (as j varies from 1 to 10 or Vds ¼0.1 V to 1 V). So, Aj, Bj and Cj are plotted with Vds to obtain their dependence in the form of polynomials given as A ¼ p0 þ p1 V ds þ p2 V 2ds þ p3 V 3ds þ p4 V 4ds

ð13aÞ

B ¼ q0 þ q1 V ds þ q2 V 2ds þ q3 V 3ds

ð13bÞ

C ¼ t 0 þ t 1 V ds þ t 2 V 2ds þ t 3 V 3ds

ð13cÞ

The fourth and third order polynomial fits well and allows the barrier width and consequently the drain current to be differentiable otherwise the term A and B would vanish resulting in erroneous values for higher order derivatives. Step 4: The expressions of A, B and C as derived in step 3 are valid for a particular radius (R) and gate oxide thickness (tox). In order to include the dependence of device geometry parameters such as radius and tox as well, steps 1 to 3 are repeated for a set of R and tox combinations (where k represents the total number of cases studied i.e. k ¼6) which are shown in Table 1. The dependence of R and tox is taken through the term λ, which is the scale length for GAA [27]. vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  u u 2ε ð2R Þ2 ln 1 þ t ox;k þ εox ð2Rk Þ2 si k t Rk λk ¼ ð14Þ 16εox

R. Narang et al. / Microelectronics Journal 44 (2013) 479–488

where R is the radius, εox is gate oxide (SiO2) permittivity, εsi is silicon channel permittivity and tox is gate oxide thickness and k varies from 1 to 6 for the 6 different R and tox combinations or in turn λ. Thus we obtain Ak, Bk and Ck for k ¼1 to 6. To capture the dependence of λ, the coefficients of Ak, Bk and Ck i.e. p0,…,p4, q0,…, q3 and t0,…,t3 are individually plotted with λ (in nm) and expressions are derived in terms of λ (in nm) (Table 2). Thus, the total number of fitting parameter are 13 (i.e. p0,…,p4, q0,…,q3 and t0,…,t3) which are used to match analytical results over a wide range of bias conditions (Vgs ¼0.4 V to 1.5 V and Vds ¼ 0.1 V to 1 V) and device dimensions (i.e. R¼6.5 nm to 10 nm and tox ¼2 nm to 4 nm). By adopting the methodology step by step as described above the dependence of gate and drain voltages along with device geometry parameters (R and tox) can be included in the modeling scheme to make it operational for a wide range of parameters. The expression of LBW ′ has pre-factor and power term of high order polynomial. The advantage of taking a higher order polynomial is to make the drain current expression differentiable, otherwise the barrier width term would vanish resulting in erroneous results for higher order derivatives. The generation rate is evaluated using the following expression Gbtbt ðEavg Þ ¼ Akane


 −Bkane E2avg exp Eavg

ð15Þ

483

where pffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffi π 2 Eg 3=2 mtunnel =2 q2 2mtunnel Akane ¼ Bkane ¼ 2 1=2 qh h Eg ð1=mtunnel Þ ¼ ð1=mee Þ þ ð1=meh Þ, meh ¼mh mo, mee ¼me mo, me and mh are the electron and hole effective masses, respectively [16] (taken to be equal to the masses obtained by ATLAS model calibration with experimental data [18]), mo is the rest mass of an electron and Eg is the band gap. The total electric field, ETotal (16) is integrated over the barrier width (LBW') to estimate the average electric field, Eavg, as R rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2  2     L ′ E Total dy ETotal ¼ Er  þ Ey  and Eavg ¼ BW ð16Þ LBW ′ The expression for drain current (Ids) is given as: I ds ¼ q π R2 LBW ′ Gbtbt ðEavg Þ

ð17Þ

where the dependence of source, drain doping and length of the device on the drain current is implicit in the expression of Gbtbt(Eavg).

4. Results verification and discussion The model proposed in the work has been verified through device simulations results obtained from ATLAS. The surface potential profile over a large gate voltage range (0.4 V to 1.2 V) is shown in Fig. 4((a)–(c)). Since the analysis also takes into account the depletion width extension inside the source/drain region along with their doping, thus the model can be helpful for studying the impact of doping variations.

Table 1 Combination of radius (R) and gate oxide thickness (tox) considered for the study.

4.1. Impact of pocket doping and width Case (k)

Radius, Rk (in nm)

tox,k (in nm)

Lambda (λk) (in nm)

1 2 3 4 5 6

10 10 10 7.5 7.5 6.5

2 3 4 3 4 4

7.25 8.04 8.71 6.53 7.10 6.42

Table 2 λ dependent expressions of the coefficients of Eq. (13). p0 ¼ 23:118−8:113λ þ 0:978λ2 −0:039λ3

q0 ¼ 81:37−29:54λ þ 3:58λ2 −0:0144λ3

p1 ¼ 8:77−2:02λ þ 0:125λ2

q1 ¼ 100:83−36:82λ þ 4:48λ2 −0:181λ3

p2 ¼ 39:614−14:42λ þ 1:775λ2 −0:073λ3

q2 ¼ 104:64−38:09λ þ 4:61λ2 −0:186λ3

p3 ¼ 43:34−15:94λ þ 1:98λ2 −0:082λ3

q3 ¼ 84:883−30:31λ þ 3:6λ2 −0:142λ3

p4 ¼ 45:85−17:01λ þ 2:13λ2 −0:089λ3 t 0 ¼ −2:61 þ 0:425λ t 2 ¼ 1:67−0:155λ

t 1 ¼ 1:62−0:151λ t 3 ¼ 1:72−0:163λ

The impact of pocket doping and pocket width which are crucial parameter in the design of a p–n–p–n TFET have also been studied. Fig. 5 shows the impact of increasing the pocket doping on the energy band diagram and tunneling barrier width at different gate bias. With increase in pocket doping, the band bending becomes sharper leading to reduction in barrier width and hence increased tunneling current (Fig. 5(b)). But, the counter effect is the degradation in the off condition (Fig. 5(a)) because of higher band bending the device will allow tunneling at lower gate bias and hence leakage current will increase. On the other hand, for a fixed pocket doping, if the pocket width is increased, the pocket no longer remains fully depleted as shown in Fig. 5(c). As reported by Nagavarapu et al. [28] when the pocket is under partial depletion the device no longer follows the tunneling injection mechanism and behaves like a conventional FET with diffusion as the injection mechanism, thus undermining the advantage expected in terms of steep sub-threshold from tunneling based devices. Thus, it is necessary that p–n–p–n TFET be

Fig. 4. (a)–(c) 2-D Surface potential along the length (i.e. y axis) from source to drain for radii varying from 10 nm to 6.5 nm.

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R. Narang et al. / Microelectronics Journal 44 (2013) 479–488

1.5

_____

1

0 -0.5 -1

source

-2.5 -20

0

20

-0.5

Nh =9x1018 cm-3 Nh =5x1019 cm-3 Model Vgs=V ds=1V Lh=5nm

-1 -1.5

Vgs=0.2V Vds=1V Lh=5nm

channel

_____

0

-2 -2.5 -20

40

source

pocket

-2

pocket

-1.5

οο

0.5

Energy (eV)

Energy (eV)

0.5

1.5

Nh =9x1018 cm-3 Nh =5x1019 cm-3 Model

οο

1

0

Distance, y (nm)

channel 20

40

Distance, y (nm)

1.5

0.5

Energy (eV)

ATLAS Model

pocket

1

Vgs=V ds=1V Lh =15nm Nh =2x1019 cm-3

0 -0.5 -1

channel

-1.5

drain

source

-2 -2.5 -50

0

50

100

Distance, y (nm) Fig. 5. Impact of pocket doping on the band bending at the tunneling junction in the off and on state of operation (a) Vgs ¼ 0.2 V, Vds ¼ 1 V (b) Vgs ¼1 V, Vds ¼ 1 V. (c) Impact of pocket width on the energy band profile depicting the case of partial depletion. Symbol: simulation; line: model.

1.4E-08

1 V, the drain voltage influence further increases and the barrier thinning saturates at higher Vds.

R=10 nm tox=4 nm Lch=45 nm

1.2E-08

4.2. Impact of device geometry parameters on I–V characteristics

LBW' (m)

1.0E-08 8.0E-09 6.0E-09

Vds=0.4V

4.0E-09

Vds=0.5V

2.0E-09 0.0E+00

Vds=0.9 0.5

0.7

0.9 1.1 Vgs (V)

1.3

1.5

Fig. 6. Barrier width (LBW') variation with gate voltage at different drain bias.

optimized for pocket doping and pocket width to attain optimum device performance: Vth, Ion/Ioff and Sub-threshold swing. After the device electrostatics have been verified, the model is extended to calculate the drain current characteristics, transconductance and device efficiency (gm/Ids). As already been discussed in the previous section that a semi-empirical expression for barrier width is obtained and the results are shown in Fig. 6. The drain voltage influence on the barrier width with increasing gate voltages is evident from Fig. 6. It can be observed that at low gate voltage (0.5–0.6 V just above Vonset), the barrier width narrowing saturates early, on the other hand, as the gate voltage increases to

4.2.1. Scaling of radii (R) and channel length (Lch) The model is valid from onset to saturation as shown by the Ids– Vgs characteristics (Fig. 7). The impact of scaling the radii can be seen (Fig. 7(a)), by reduction in Vonset due to lowering of barrier width as radius reduces. The On current (@Vds ¼0.8 V) increases by  1.5 times when radius is scaled from 10 nm to 6.5 nm. Because with radius scaling, the gate control over channel electrostatics is improved. This results in increased lateral electric field component (EFy) at the tunneling junction (Fig. 8(a)) for smaller radii, while the transverse electric field component (EFr) is almost same (Fig. 8 (b)). The high electric field results in lower barrier width and onset voltage and enhancement of drain current (as also observed in the earlier works [7,8]) and hence improvement in trans-conductance as well. The impact of scaling the channel length (from 90 nm to 45 nm) on the drain current characteristics is negligible as shown in Fig.7(b). The impact of channel length scaling only starts appearing when the gate length is scaled to less than 4 times of (λ/π, where λ is the scale length) [13] due to enhancement in the influence of drain voltage at the tunneling barrier width. 4.2.2. Scaling of gate oxide thickness (tox) The impact of tox scaling on the drain current is shown in Fig. 9. As the gate oxide thickness is reduced by 1 nm, the ON current (@Vds ¼0.8 V) increases by  4 times in magnitude and Vonset decreases by  20–30 mV. The average sub-threshold swing (SSavg) evaluated over five orders improves by 10 mV/dec i.e. from 50 mV/dec to 40.2 mV/dec when tox is scaled from 4 nm to 2 nm

R. Narang et al. / Microelectronics Journal 44 (2013) 479–488

1.E-07

1.E-06

Vds =0.8V Lch =45nm tox =4nm

1.E-08 1.E-09

2.0E-07

Lch=90 nm ATLAS

1.E-07

Lch=45nm ATLAS

1.E-08

Lch=90nm Model

1.5E-07

Lch=45nm Model

1.E-09

R=6.5 nm R=7.5 nm

1.E-12

0.3

0.6

0.9

1.2

5.0E-08

1.E-14

1.E-15 0

1.0E-07

1.E-13

Line:Model Symbol: ATLAS

1.E-14

R=10nm tox =2nm Vds=0.8V

1.E-11 1.E-12

R=10 nm

1.E-13

1.E-10

I ds (A)

1.E-11

I ds (A)

1.E-10

I ds (A)

485

1.E-15

1.5

0

0.3

0.6

Vgs (V)

0.9

1.2

1.5

0.0E+00

Vgs (V)

Fig. 7. (a) Impact of radii scaling (b) impact of channel length on the Ids–Vgs characteristics.

Distance, y (nm) -25

0

25

50

75

0

Distance, y (nm)

-2

Vgs = 1.6 V Vds = 1V

EFy max (M V/cm)

6.5

3.98

7.5

3.83

10

3.69

-3 R=6.5nm R=7.5nm

-4

-25

0

25

50

75

0

EFr (MV/cm)

EFy (MV/cm)

-1

R (nm)

Vgs = 1.6 V Vds = 1V

-0.5

R=6.5nm R=7.5nm R=10nm

-1

R=10nm

-5

-1.5

Fig. 8. (a) Lateral electric field component, EFy (b) transverse electric field component, EFr along the device at different radii.

1.E-06

1.E-07

Vds=0.8V Lch=45nm

1.E-08

1.E-07

R=10nm tox=2nm Lch=45nm

1.E-08

R=10nm

1.E-09

1.E-09

Ids (A)

Ids (A)

1.E-11

1.E-13

1.E-12 1.E-13

1.E-15 0

0.3

0.6

0.9

1.2

1.5

Vgs (V)

Vds=0.6Vand 1.0V

1.E-11

tox=3 nm tox=4 nm Line:Model Symbol: ATLAS

1.E-14

1.E-10

tox=2 nm 1.E-12

1.5E-07

1.0E-07

Ids (A)

1.E-10

2.0E-07

Solid line: Model Dotted Line: ATLAS

5.0E-08

1.E-14 1.E-15 0

0.3

0.6

0.9

1.2

0.0E+00 1.5

Vgs (V) Fig. 10. Impact of drain voltage (Vds) on the Ids–Vgs characteristics.

Fig. 9. Impact of gate oxide scaling on the drain current.

for R ¼10 nm. Thus, we can notice that the tox scaling has larger impact on the device performance of the TFET as compared to radii scaling. The agreement between proposed model and numerical

simulations is very good, but the reason of deviation in the saturation region (Fig. 7(b), Fig. 10) is the non-inclusion of mobile charge density. Because during inversion condition the mobile charges dominates the device electrostatics and leads to pinning of the surface potential in the channel potential and preventing the

486

R. Narang et al. / Microelectronics Journal 44 (2013) 479–488

band bending further. This phenomenon results in slower increment of the drain current in the saturation regime and hence the modeled drain current increases at a higher rate than the simulation results as also reported by Liu et al. [13].

4.E-09 Line: Model Symbol:ATLAS

Ids (A)

3.E-09

R=10 nm tox=4 nm Lch=45 nm

2.E-09

Vgs increasing from 1 V to 1.3 V in step of 0.1 V

1.E-09

0.E+00

0

0.2

0.4 0.6 Vds (V)

0.8

1

Fig. 11. Ids–Vds characteristics for GAA p–n–p–n TFET.

4.3. Ids–Vds characteristics and delayed saturation effect The drain voltage influence on the barrier width at different gate bias is evident from Fig. 6, and the concept of delayed saturation effect reported for TFET is very well captured by the model as shown in the Ids–Vds characteristics (Fig. 11). For the condition |Vgs|≫|Vds| a large number of electrons are present in the channel region which results in low channel resistance and conduction band pinning. If the Vds is now increased there is negligible drain voltage drop in the channel and a large part of drain voltage will appear at the tunneling junction leading to barrier thinning resulting in the phenomenon drain induced barrier thinning (DIBT) [13]. As the drain voltage kept on increasing and leading to condition |Vds|≫|Vgs|, where the gate voltage can no longer maintain the electron concentration in the channel region, the channel region starts depleting of electrons leading to high channel resistance. In this condition, most of the drain voltage drops at the channel/drain junction [29] and the drain potential no longer affects the tunneling barrier width at the source/channel junction resulting in saturation of drain current. Thus for a higher gate voltage, the drain saturation voltage shifts to higher drain potential or the pinch-off point shifts in towards higher drain voltage resulting in delayed saturation [30]. The influence of drain voltage on tunnel FET operation studied through the analytical model proposed in this work is in consonance with a detailed simulation study by Mallik and Chattopadhyay [26], confirming the capability of the model to describe the TFET operation satisfactorily.

1.E-07

1.E-09

g m (S)

1.E-09

g m (S)

1.E-07

R=6.5nm tox=4nm Vds=0.8V

1.E-11

Model 1.E-13

R=7.5nm tox=4nm Vds=0.8V

1.E-11

Model

1.E-13

ATLAS

ATLAS 1.E-15

0.3

0.6

0.9

1.E-15 0.3

1.2

0.6

100

100 R=6.5nm tox=4nm Vds=0.8V

10

Model ATLAS

1.E-13

1.E-11

Ids (A)

1.E-09

Device Efficieny, gm/Ids (V-1)

Device Efficieny, gm/Ids (V-1)

1.2

Vgs (V)

Vgs (V)

1 1.E-15

0.9

R=7.5nm tox=4nm Vds=0.8V 10

Model ATLAS 1 1.E-15

1.E-13

1.E-11

1.E-09

Ids (A)

Fig. 12. (a) and (b) gm variation with gate voltage (c) and (d) device efficiency (gm/Ids) variation with drain current (Ids), for GAA p–n–p–n TFET at different radii.

R. Narang et al. / Microelectronics Journal 44 (2013) 479–488

band bending, Ids–Vgs, Ids–Vds, SSavg, gm and gm/Ids) with good accuracy over large voltage range and device dimensions. It has been shown, that the impact of tox scaling is higher in terms of Vonset reduction and SSavg improvement as compared to radii scaling. The average sub-threshold swing (SSavg) evaluated over five orders improves by10 mV/dec when tox is scaled from 4 nm to 2 nm for R¼10 nm.

Device Efficieny, g m/Ids (V-1)

100

10

487

Dotted Line:Model Symbol: ATLAS tox=2 nm tox=4 nm

1 1.E-15

1.E-13

R=10nm Vds=0.8 V Lch=45nm

1.E-11 Ids (A)

1.E-09

Acknowledgments Authors would like to thank University of Delhi and Ministry of Science and Technology, Department of Science and Technology (DST), Government of India. Rakhi Narang would like to thank University Grants Commission, Govt. of India, for providing the necessary financial assistance during the course of this research work.

Fig. 13. Impact of tox scaling on device efficiency (gm/Ids).

Appendix 4.4. Trans-conductance and device efficiency (gm/Ids) The first order derivative of drain current with respect to gate voltage, also known as trans-conductance, gm (one of the important device parameter) is obtained. Fig. 12 shows the variation of gm with gate voltage and it can be observed that with scaling of radii gm improves as the drain current also improves for lower radii. Using the derived gm and Ids, a key parameter in analog design i.e. trans-conductance generation efficiency or the device efficiency, known as gm/Ids ratio has been derived as shown in Fig. 12. gm/Ids represents the available gain per unit of power dissipation. gm/Ids is maximum in the weak inversion region and decreases monotonically as the drain current increases. One of the important point to be noticed and which has been emphasized in this work is that, the gm/Ids value in the sub-threshold (or near the Vonset in this case), is above the maximum possible value of 40 V−1 that can be obtained in case of conventional MOSFET. This is a huge advantage similar to another fundamental and attractive property of TFET of going below the 60-mV/dec sub-threshold swing limit. Thus, TFET can deliver higher gain in comparison to MOSFET for the same power dissipation. The fact that TFET has different current conduction mechanism and thus different set of physical equations governing the tunneling phenomenon in comparison to MOSFET makes it possible to overcome these two fundamental limits. With gate oxide scaling the analog performance in terms of gm/Ids ratio can further be improved as shown in Fig. 13. Thus, with the advantages of sub-60 mV/dec sub-threshold swing and a higher device efficiency, along with better scalability, suppressed SCEs, low leakage and power dissipation the future prospects of TFET seems very promising.

The expressions for the coefficients Aj and Bj are given below:

 λ2 A:1 α1 ¼ expðλ2 L1 Þ coshðλ1 L1 Þ− sinhðλ1 L1 Þ λ1

 λ2 α2 ¼ expð−λ2 L1 Þ coshðλ1 L1 Þ þ sinhðλ1 L1 Þ λ1

A:2

α3 ¼ ðη2 −η1 Þcoshðλ1 L1 Þ

A:3


 α1 λ3 1þ ω1 ¼ expððλ3 −λ2 ÞðL1 þ L2 ÞÞ 2 λ2
 α2 λ3 1− expððλ3 þ λ2 ÞðL1 þ L2 ÞÞ þ 2 λ2 ω2 ¼


 α1 λ3 1− expðð−λ3 −λ2 ÞðL1 þ L2 ÞÞ 2 λ2
 α2 λ3 1þ expðð−λ3 þ λ2 ÞðL1 þ L2 ÞÞ þ 2 λ2

  ω3 ¼ 0:5 η3 −η2 ½α1 expð−λ2 ðL1 þ L2 ÞÞ þ α2 expðλ2 ðL1 þ L2 ÞÞ
 ω1 λ4 1þ expððλ4 −λ3 ÞðL1 þ L2 þ L3 ÞÞ s1 ¼ 2 λ3
 ω2 λ4 1− expððλ4 þ λ3 ÞðL1 þ L2 þ L3 ÞÞ þ 2 λ3 s2 ¼


 ω1 λ4 1− expðð−λ4 −λ3 ÞðL1 þ L2 2 λ3
 ω2 λ4 1þ þL3 ÞÞ þ expðð−λ4 þ λ3 ÞðL1 þ L2 þ L3 ÞÞ 2 λ3

A:4

A:5 A:6

A:7

A:8

  s3 ¼ 0:5 η4 −η3 ½ω1 expð−λ3 ðL1 þ L2 þ L3 ÞÞ þω2 expðλ3 ðL1 þ L2 þ L3 ÞÞ

5. Conclusion In conclusion, a two-dimensional drain current model for GAA pocket doped TFET has been developed, incorporating the effect of drain bias and source/drain doping. The integrated influence of gate and drain voltage and the device geometry parameters (R, tox) on the characteristics of a TFET is captured using an empirically derived barrier width expression. The role of pocket doping and pocket width, impact of device geometrical parameters such as radii, EOT and channel length have also been investigated. The important feature of the proposed model is that, it can predict most of the important parameters (potential, electric field, energy

γ ¼ s 3 þ ω3 þ α 3

A:9 A:10

ξ1 ¼ expðλ4 ðL1 þ L2 þ L3 þ L4 ÞÞ ξ2 ¼ expð−λ4 ðL1 þ L2 þ L3 þ L4 ÞÞ

A:11

A4 ¼

 ðV bis −η1 Þξ2 −ðV bid þ V ds −η4 Þω2 −ξ2 γ ξ2 s1 −ξ1 s2

A:12

B4 ¼

 ðV bis −η1 Þξ1 −ðV bid þ V ds −η4 Þω1 −ξ1 γ ξ1 s2 −ξ2 s1

A:13

488

A3 ¼

B3 ¼

A2 ¼

R. Narang et al. / Microelectronics Journal 44 (2013) 479–488


 A4 λ4 expððλ4 −λ3 ÞðL1 þ L2 þ L3 ÞÞ 1 þ 2 λ3 B4 þ expðð−λ4 −λ3 ÞðL1 þ L2 þ L3 ÞÞ
2   λ4 η −η þ 4 3 expð−λ3 ðL1 þ L2 þ L3 ÞÞ  1− λ3 2
 A4 λ4 expððλ4 þ λ3 ÞðL1 þ L2 þ L3 Þ 1− 2 λ3 B4 þ expðð−λ4 þ λ3 ÞðL1 þ L2 þ L3 ÞÞ
2   λ4 η −η  1þ þ 4 3 expðλ3 ðL1 þ L2 þ L3 Þ λ3 2

A:14

A:15


 A3 λ3 B3 expððλ3 −λ2 ÞðL1 þ L2 ÞÞ 1 þ þ expðð−λ3 −λ2 ÞðL1 þ L2 ÞÞ 2 λ2 2
  λ3 η −η þ 3 2 expð−λ2 ðL1 þ L2 ÞÞ A:16  1− λ2 2


 A3 λ3 expððλ3 þ λ2 ÞðL1 þ L2 Þ 1− 2 λ
2  B3 λ3 þ expðð−λ3 þ λ2 ÞðL1 þ L2 ÞÞ 1 þ 2 λ2 η −η 3 2 expðλ2 ðL1 þ L2 ÞÞ þ 2
 A2 λ2 expððλ2 −λ1 ÞðL1 ÞÞ 1 þ A1 ¼ 2 λ
1   B2 λ2 η −η þ 2 1 expð−λ1 L1 Þ þ expðð−λ2 −λ1 ÞðL1 ÞÞ 1− 2 λ1 2 B2 ¼

B1 ¼


 A2 λ2 expððλ2 þ λ1 ÞðL1 ÞÞ 1− 2 λ
1   B2 λ2 η −η þ 2 1 expðλ1 L1 Þ þ expðð−λ2 þ λ1 ÞðL1 ÞÞ 1 þ 2 λ1 2

A:17

A:18

A:19

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