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PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis
Superlattices and Microstructures 86 (2015) 121–125
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis Dawit Burusie Abdi ⇑, M. Jagadesh Kumar Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi 110 016, India
a r t i c l e
i n f o
Article history: Received 25 April 2015 Received in revised form 15 July 2015 Accepted 15 July 2015 Available online 16 July 2015 Keywords: Source-pocket (PNPN) TFET Tunneling Pocket implantation In-built N+ pocket Charge plasma Electrostatic doping 2D TCAD simulation
a b s t r a c t A detailed study of a technique to realize a PNPN tunnel field effect transistor (TFET) with a controllable tunnel barrier width on the drain side is reported in this paper. By using the charge plasma concept on a doped N+/P starting structure, we have demonstrated the possibility of realizing the PNPN TFET without the need for any additional chemically doped junctions. We have showed that using electrostatic doping on the drain side of TFETs provides a new design parameter, the gate–drain electrode gap. This gate–drain electrode gap can be used to control the ambipolar current in TFETs by controlling the tunneling barrier width at the channel–drain junction. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction For ultra-low power circuit applications, with the goal of replacing the metal oxide semiconductor field effect transistors (MOSFETs) by transistors based on a new carrier injection mechanism, the tunnel field effect transistors (TFETs) are being aggressively studied. TFETs exhibit a sub-60 mV/decade subthreshold swing (SS) and a low OFF-state current [1–3]. However, TFETs have low drive current and inherent ambipolar conduction which adversely affect the performance and the functionality of circuits based on these transistors. Therefore, increasing the ON-state current, reducing the fabrication complexity, controlling the ambipolar current and improving the reliability of TFETs are being studied extensively [4–16]. A PNPN TFET, which has the same structure as the conventional p-i-n TFET except for the introduction of a narrow N+ doped pocket between the source and the channel, exhibits increased ON-state current, enhanced SS as well as improved device reliability over the conventional p-i-n TFET [4,13,14]. Although introducing the N+ pocket results in improved electrical characteristics, realizing this narrow and highly doped pocket is a technological challenge [17–20]. The in-built N+ pocket PNPN TFET [21], which we have recently reported, is one possible technique to overcome these difficulties in realizing the narrow N+ pocket in the PNPN TFET. The in-built N+ pocket PNPN TFET technique uses the charge plasma (also known as electrostatic doping) concept [11,22–29] on the source side starting with an NPN structure to realize the PNPN TFET. This technique eliminates the need for a separate ion implantation or an epitaxial growth to create the N+ pocket. Therefore, it simultaneously leads to improved electrical characteristics and device reliability due to its PNPN nature, and eases the fabrication complexity.
⇑ Corresponding author. E-mail addresses: [email protected] (D.B. Abdi), [email protected] (M. Jagadesh Kumar). http://dx.doi.org/10.1016/j.spmi.2015.07.045 0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.
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Fig. 1. Schematic view of (a) starting N+/P junction structure to realize the in-built N+ pocket PNPN TFET (b) the proposed in-built N+ pocket PNPN TFET.
Fig. 2. The induced (a) hole and (b) electron carrier concentration contours under thermal equilibrium conditions for an N+ pocket length (L+N) of 4 nm and gate–drain electrode gap (Lgap) of 15 nm.
0
Fig. 3. Transfer characteristics of the conventional p-i-n TFET and the proposed in-built N+ pocket PNPN TFET with a single chemically doped PN junction and with a pocket length (L+N) of 4 nm and a gate–drain electrode gap (Lgap) of 15 nm, for different VDS.
To further simplify the fabrication process and suppress the ambipolar current by controlling the tunnel barrier width at the channel–drain junction, in this paper, we have proposed and analyzed a technique of realizing the in-built N+ pocket PNPN TFET starting with a single PN junction structure as shown in Fig. 1(a). Using the charge plasma concept, as shown in Fig. 1(b), (i) a part of N+ region is converted into ‘‘P+’’ source region with a source electrode of appropriate work function leaving a pocket of N+ doped region between the source and the channel, and (ii) the P region is converted into the ‘‘N+’’ drain region with a drain electrode of appropriate work function. Using 2D TCAD simulations, we have demonstrated that by choosing an appropriate spacer thickness between the gate and the drain electrodes (Lgap), the drain side tunneling barrier width in the proposed device can be controlled which is not possible in the case of both conventional PNPN TFET and p-i-n
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Fig. 4. Energy-band profiles to show the effect of (a) the gate–drain electrode gap (Lgap) and (b) the drain to source voltage (VDS) on the tunneling barrier.
Fig. 5. Minimum tunneling barrier width for different gate–drain electrode gaps (Lgap) and different drain to source voltages (VDS) at VGS =
0.5 V.
TFET. We have showed that this unique ability of using electrostatic doping on the drain side to control the drain side tunneling barrier width can be used to effectively suppress the ambipolar current in TFETs. 2. Simulation parameters The parameters used in our simulation are: silicon film thickness tsi = 10 nm, gate oxide thickness (SiO2) tox = 3 nm, channel length (L) = 50 nm, gate work function = 4.37 eV, source doping ND = 4 1019 cm 3 and channel doping NA = 1 1016 cm 3. The source electrode work function is chosen to be 5.93 eV to induce holes in a part of the N+ region of the PN junction and hence convert it into a ‘‘P+’’ source of the PNPN TFET [11]. This results in an N+ pocket length L+N of 4 nm between the induced ‘‘P+’’ source and the channel. A work function value of 3.93 eV [11] for the drain electrode is used to induce electrons and hence create the ‘‘N+’’ drain of the PNPN TFET. The concentration of induced holes and electrons in
Fig. 6. The effect of the gate–drain electrode gap (Lgap) and the drain to source voltage (VDS) on the ambipolar current. The ambipolar current is extracted at VGS = 0.5 V.
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the source and the drain, respectively, is shown in the contour plots of Fig. 2. We observe that the induced surface carrier concentration is significantly large (1021 cm 3) which is required for the proper functioning of the transistor. To induce the largest possible hole and electron concentration in the source and drain regions, the effective oxide thickness (EOT) under the charge plasma electrodes is chosen to be 0.5 nm and 3 nm on the source and the drain side, respectively [11]. The gate–drain electrode gap length (Lgap) is varied from 3 nm to 35 nm to study how the drain side tunneling barrier width changes and suppresses the ambipolar current in the device. All the simulations were done in Silvaco Atlas, Version 5.19.20.R [30]. To take into account the tunneling along the lateral direction, we used a non-local band-to-band tunneling (BTBT) model. The Lombardi mobility model is used to include the mobility effect. Band-gap narrowing (BGN) model is also enabled to take care of high doping effects in the in-built N+ region. We have used the Fermi–Dirac statistics and the Shockley–Read-Hall (SRH) recombination models. As done earlier [11,12,16,21], we have calibrated our simulation models by reproducing the results reported in [31]. 3. Results and discussions The in-built N+ pocket PNPN TFET [21] results in improved subthreshold slope and ON-state current of the PNPN TFET as compared to the conventional doped p-i-n TFET [31] as shown in Fig. 3. The average subthreshold slope, extracted as given in [11], is found to be 25 mV/decade and 65 mV/decade for the proposed structure and the conventional p-i-n TFET, respectively. There are no electrically induced free carriers in the gap between the gate–drain electrodes (Lgap). This gap is equivalent to the depletion region between the channel and the drain in a conventional TFET. The tunneling barrier width on the drain side in a conventional TFET is controlled by the depletion layer width which in turn is decided by the doping on both sides of the junction. To minimize the ambipolar current, the depletion region width on the drain side should be large. However, increasing the depletion region width without reducing the drain doping or without using the gate drain underlap [32] is not possible in a conventional TFET. However, both the above techniques are used for chemically doped TFETs to suppress ambipolar current. On the other hand, in the proposed device by controlling Lgap, a wider depletion region between the gate and drain can be realized as illustrated in Fig. 4(a). The depletion width on the drain side also depends on the drain to source voltage, VDS, as can be seen in Fig. 4(b). Therefore in Fig. 5, we have shown the minimum tunneling barrier width as a function of Lgap for different values of drain to source voltage VDS. We observe that the minimum tunneling barrier width approximately varies linearly with Lgap. To minimize the drain side ambipolar current, we need a larger tunneling barrier width for a given VDS. Fig. 6 shows the effect of the gate–drain electrode gap Lgap and the drain to source voltage VDS on the ambipolar current extracted at a gate to source voltage VGS = 0.5 V. It is clear from Fig. 6 that the ambipolar current can be minimized by increasing the gate–drain electrode gap (Lgap). A larger Lgap is equivalent to a wider depletion width and thus increases the tunneling barrier width at the channel–drain junction. For example, if VDS = 0.7 V, we need a minimum Lgap of 20 nm to suppress the ambipolar current. Therefore, our results indicate that doping the drain electrostatically provides a new design parameter, Lgap, to suppress the ambipolar current in a TFETs. In addition, our approach also leads to a low thermal budget process due to the absence of the need to chemically dope the drain region. 4. Conclusions In this paper, using 2D TCAD simulations, we have reported a method for realizing a PNPN TFET with a controllable tunnel barrier width on the drain side. We have demonstrated that the proposed PNPN TFET structure can be realized on a doped N+/P starting structure using electrostatic doping and therefore, without the need for additional chemically doped junctions. Our approach will minimize the thermal budget required to fabricate the PNPN TFET. We have shown that the use of electrostatic doping on the drain side of TFETs provides a new design parameter, the gate–drain electrode gap (Lgap), for controlling the drain side tunneling barrier width. As a result, the ambipolar current can be effectively suppressed by choosing an appropriate gate–drain electrode gap (Lgap). References [1] [2] [3] [4] [5] [6] [7] [8] [9]
A.C. Seabaugh, Q. Zhang, Low-voltage tunnel transistors for beyond CMOS logic, Proc. IEEE 98 (12) (2010) 2095–2110. A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy efficient electronic switches, Nature 479 (7373) (2011) 329–337. A.C. Seabaugh, H. Lu, Tunnel field-effect transistors – update, IEEE Int. Conf. Solid-State Integr. Circ. Technol. (12) (2014) 1–4. N.V. Nagavarapu, R. Jhaveri, J.C.S. Woo, The tunnel source (PNPN) n-MOSFET: a novel high performance transistor, IEEE Trans. Electron Dev. 55 (4) (2008) 1013–1019. O. Nayfeh, C. Chleirigh, J. Hennessy, L. Gomez, J. Hoyt, D. Antoniadis, Design of tunneling field-effect transistors using strained-silicon/strainedgermanium type-II staggered heterojunctions, IEEE Electron Dev. Lett. 29 (9) (2008) 1074–1077. D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu, D. Loubychev, J. Fastenau, S. Datta, Experimental staggered-source and N+ pocket-doped channel III–V tunnel field-effect transistors and their scalabilities, Appl. Phys. Express 4 (2) (2011) 024105–024106. F. Conzatti, M. Pala, D. Esseni, E. Bano, L. Selmi, Strain-induced performance improvements in InAs nanowire tunnel FETs, IEEE Trans. Electron Dev. 59 (8) (2012) 2085–2092. Q. Huang, R. Huang, Z. Zhan, Y. Qiu, W. Jiang, C. Wu, Y. Wang, A novel Si tunnel FET with 36 mV/dec subthreshold slope based on junction depletedmodulation through striped gate configuration, in: Proc. IEEE Int. Electron Devices Meeting, December 2012, pp. 1–4. W.Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field-effect transistors, IEEE Trans. Electron Dev. 57 (9) (2010) 2317–2319.
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[10] N. Cui, R. Liang, J. Xu, Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation, Appl. Phys. Lett. 98 (14) (2011) 142105. [11] M.J. Kumar, S. Janardhanan, Doping-less tunnel field effect transistor: design and investigation, IEEE Trans. Electron Dev. 60 (October) (2013) 3285– 3290. [12] D.B. Abdi, M.J. Kumar, Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain, IEEE J. Electron Dev. Soc. 2 (6) (2014) 187–190. [13] W. Cao, C.J. Yao, G.F. Jiao, D. Huang, H.Y. Yu, M-F. Li, Improvement in reliability of tunneling field-effect transistor with p-n-i-n structure, IEEE Trans. Electron Dev. 58 (7) (2011) 2122–2126. [14] S. Cho, I.M. Kang, Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics, Curr. Appl. Phys. 12 (3) (2012) 673–677. [15] S. Saurabh, M.J. Kumar, Investigation of the novel attributes of a dual material gate nanoscale tunnel field effect transistor, IEEE Trans. Electron Dev. 58 (February) (2011) 404–410. [16] M.S. Ram, D.B. Abdi, Single grain boundary tunnel field effect transistors on recrystallized polycrystalline silicon: proposal and investigation, IEEE Electron Dev. Lett. 35 (10) (2014) 989–991. [17] R. Jhaveri, N.V. Nagavarapu, J.C.S. Woo, Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor, IEEE Trans. Electron Dev. 58 (1) (2011) 80–86. [18] A. Tura, Z. Zhang, P. Liu, Y-H. Xie, J.C.S. Woo, Vertical silicon p-n-p-n tunnel nMOSFET with MBE-grown tunneling junction, IEEE Trans. Electron Dev. 58 (7) (2011) 1907–1913. [19] H.-Y. Chang, B. Adams, P.-Y. Chien, J. Li, J.C.S. Woo, Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing, IEEE Trans. Electron Dev. 60 (1) (2013) 92–96. [20] Y. Zhang, H.-Chu, Tunneling field effect transistor (TFET) with ultra-shallow pockets formed by asymmetric ion implantation and method of making same, US patent: 20140158990, June 2014. [21] D.B. Abdi, M.J. Kumar, In-built N+ pocket PNPN tunnel field-effect transistor, IEEE Electron Dev. Lett. 35 (12) (2014) 1170–1172. [22] B. Rajasekharan, R.J.E. Hueting, C. Salm, T. van Hemert, R.A.M. Wolters, J. Schmitz, Fabrication and characterization of the charge plasma diode, IEEE Electron Dev. Lett. 31 (6) (2010) 528–530. [23] R.J.E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, Charge plasma P-N diode, IEEE Electron Dev. Lett. 29 (12) (2008) 1367–1368. [24] M.J. Kumar, K. Nadda, Bipolar charge plasma transistor: a novel three terminal device, IEEE Trans. Electron Dev. 59 (4) (2012) 962–967. [25] K. Nadda, M.J. Kumar, Thin-film bipolar transistors on recrystallized polycrystalline silicon without impurity doped junctions: proposal and investigation, IEEE/OSA J. Disp. Technol. 10 (7) (2014) 590–594. [26] K. Nadda, M.J. Kumar, Vertical bipolar charge plasma transistor with buried metal layer, Sci. Rep. 5 (January) (2015) 1–6 (article no. 7860). [27] M.S. Ram, D.B. Abdi, Dopingless PNPN tunnel FET with improved performance: design and analysis, Superlattices Microstruct. 82 (June) (2015) 430– 437. [28] M.J. Kumar, M. Maheedhar, P.P. Varma, Junctionless biristor: a bistable resistor without chemically doped P-N junctions, IEEE J. Electron Dev. Soc. 3 (4) (2015) 311–315. [29] C. Sahu, J. Singh, Charge-plasma based process variation immune junctionless transistor, IEEE Electron Dev. Lett. 35 (3) (2014) 411–413. [30] ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, USA, 2014. [31] K. Boucart, A.M. Ionescu, Double gate tunnel FET with high-k gate dielectric, IEEE Trans. Electron Dev. 54 (7) (2007) 1725–1733. [32] A.S. Verhulst, W.G. Vandenberghe, K. Maex, G. Groeseneken, Tunnel field-effect transistor without gate–drain overlap, Appl. Phys. Lett. 91 (5) (2007) 053102–053103.
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis Dawit Burusie Abdi ⇑, M. Jagadesh Kumar Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi 110 016, India
a r t i c l e
i n f o
Article history: Received 25 April 2015 Received in revised form 15 July 2015 Accepted 15 July 2015 Available online 16 July 2015 Keywords: Source-pocket (PNPN) TFET Tunneling Pocket implantation In-built N+ pocket Charge plasma Electrostatic doping 2D TCAD simulation
a b s t r a c t A detailed study of a technique to realize a PNPN tunnel field effect transistor (TFET) with a controllable tunnel barrier width on the drain side is reported in this paper. By using the charge plasma concept on a doped N+/P starting structure, we have demonstrated the possibility of realizing the PNPN TFET without the need for any additional chemically doped junctions. We have showed that using electrostatic doping on the drain side of TFETs provides a new design parameter, the gate–drain electrode gap. This gate–drain electrode gap can be used to control the ambipolar current in TFETs by controlling the tunneling barrier width at the channel–drain junction. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction For ultra-low power circuit applications, with the goal of replacing the metal oxide semiconductor field effect transistors (MOSFETs) by transistors based on a new carrier injection mechanism, the tunnel field effect transistors (TFETs) are being aggressively studied. TFETs exhibit a sub-60 mV/decade subthreshold swing (SS) and a low OFF-state current [1–3]. However, TFETs have low drive current and inherent ambipolar conduction which adversely affect the performance and the functionality of circuits based on these transistors. Therefore, increasing the ON-state current, reducing the fabrication complexity, controlling the ambipolar current and improving the reliability of TFETs are being studied extensively [4–16]. A PNPN TFET, which has the same structure as the conventional p-i-n TFET except for the introduction of a narrow N+ doped pocket between the source and the channel, exhibits increased ON-state current, enhanced SS as well as improved device reliability over the conventional p-i-n TFET [4,13,14]. Although introducing the N+ pocket results in improved electrical characteristics, realizing this narrow and highly doped pocket is a technological challenge [17–20]. The in-built N+ pocket PNPN TFET [21], which we have recently reported, is one possible technique to overcome these difficulties in realizing the narrow N+ pocket in the PNPN TFET. The in-built N+ pocket PNPN TFET technique uses the charge plasma (also known as electrostatic doping) concept [11,22–29] on the source side starting with an NPN structure to realize the PNPN TFET. This technique eliminates the need for a separate ion implantation or an epitaxial growth to create the N+ pocket. Therefore, it simultaneously leads to improved electrical characteristics and device reliability due to its PNPN nature, and eases the fabrication complexity.
⇑ Corresponding author. E-mail addresses: [email protected] (D.B. Abdi), [email protected] (M. Jagadesh Kumar). http://dx.doi.org/10.1016/j.spmi.2015.07.045 0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.
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Fig. 1. Schematic view of (a) starting N+/P junction structure to realize the in-built N+ pocket PNPN TFET (b) the proposed in-built N+ pocket PNPN TFET.
Fig. 2. The induced (a) hole and (b) electron carrier concentration contours under thermal equilibrium conditions for an N+ pocket length (L+N) of 4 nm and gate–drain electrode gap (Lgap) of 15 nm.
0
Fig. 3. Transfer characteristics of the conventional p-i-n TFET and the proposed in-built N+ pocket PNPN TFET with a single chemically doped PN junction and with a pocket length (L+N) of 4 nm and a gate–drain electrode gap (Lgap) of 15 nm, for different VDS.
To further simplify the fabrication process and suppress the ambipolar current by controlling the tunnel barrier width at the channel–drain junction, in this paper, we have proposed and analyzed a technique of realizing the in-built N+ pocket PNPN TFET starting with a single PN junction structure as shown in Fig. 1(a). Using the charge plasma concept, as shown in Fig. 1(b), (i) a part of N+ region is converted into ‘‘P+’’ source region with a source electrode of appropriate work function leaving a pocket of N+ doped region between the source and the channel, and (ii) the P region is converted into the ‘‘N+’’ drain region with a drain electrode of appropriate work function. Using 2D TCAD simulations, we have demonstrated that by choosing an appropriate spacer thickness between the gate and the drain electrodes (Lgap), the drain side tunneling barrier width in the proposed device can be controlled which is not possible in the case of both conventional PNPN TFET and p-i-n
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123
Fig. 4. Energy-band profiles to show the effect of (a) the gate–drain electrode gap (Lgap) and (b) the drain to source voltage (VDS) on the tunneling barrier.
Fig. 5. Minimum tunneling barrier width for different gate–drain electrode gaps (Lgap) and different drain to source voltages (VDS) at VGS =
0.5 V.
TFET. We have showed that this unique ability of using electrostatic doping on the drain side to control the drain side tunneling barrier width can be used to effectively suppress the ambipolar current in TFETs. 2. Simulation parameters The parameters used in our simulation are: silicon film thickness tsi = 10 nm, gate oxide thickness (SiO2) tox = 3 nm, channel length (L) = 50 nm, gate work function = 4.37 eV, source doping ND = 4 1019 cm 3 and channel doping NA = 1 1016 cm 3. The source electrode work function is chosen to be 5.93 eV to induce holes in a part of the N+ region of the PN junction and hence convert it into a ‘‘P+’’ source of the PNPN TFET [11]. This results in an N+ pocket length L+N of 4 nm between the induced ‘‘P+’’ source and the channel. A work function value of 3.93 eV [11] for the drain electrode is used to induce electrons and hence create the ‘‘N+’’ drain of the PNPN TFET. The concentration of induced holes and electrons in
Fig. 6. The effect of the gate–drain electrode gap (Lgap) and the drain to source voltage (VDS) on the ambipolar current. The ambipolar current is extracted at VGS = 0.5 V.
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the source and the drain, respectively, is shown in the contour plots of Fig. 2. We observe that the induced surface carrier concentration is significantly large (1021 cm 3) which is required for the proper functioning of the transistor. To induce the largest possible hole and electron concentration in the source and drain regions, the effective oxide thickness (EOT) under the charge plasma electrodes is chosen to be 0.5 nm and 3 nm on the source and the drain side, respectively [11]. The gate–drain electrode gap length (Lgap) is varied from 3 nm to 35 nm to study how the drain side tunneling barrier width changes and suppresses the ambipolar current in the device. All the simulations were done in Silvaco Atlas, Version 5.19.20.R [30]. To take into account the tunneling along the lateral direction, we used a non-local band-to-band tunneling (BTBT) model. The Lombardi mobility model is used to include the mobility effect. Band-gap narrowing (BGN) model is also enabled to take care of high doping effects in the in-built N+ region. We have used the Fermi–Dirac statistics and the Shockley–Read-Hall (SRH) recombination models. As done earlier [11,12,16,21], we have calibrated our simulation models by reproducing the results reported in [31]. 3. Results and discussions The in-built N+ pocket PNPN TFET [21] results in improved subthreshold slope and ON-state current of the PNPN TFET as compared to the conventional doped p-i-n TFET [31] as shown in Fig. 3. The average subthreshold slope, extracted as given in [11], is found to be 25 mV/decade and 65 mV/decade for the proposed structure and the conventional p-i-n TFET, respectively. There are no electrically induced free carriers in the gap between the gate–drain electrodes (Lgap). This gap is equivalent to the depletion region between the channel and the drain in a conventional TFET. The tunneling barrier width on the drain side in a conventional TFET is controlled by the depletion layer width which in turn is decided by the doping on both sides of the junction. To minimize the ambipolar current, the depletion region width on the drain side should be large. However, increasing the depletion region width without reducing the drain doping or without using the gate drain underlap [32] is not possible in a conventional TFET. However, both the above techniques are used for chemically doped TFETs to suppress ambipolar current. On the other hand, in the proposed device by controlling Lgap, a wider depletion region between the gate and drain can be realized as illustrated in Fig. 4(a). The depletion width on the drain side also depends on the drain to source voltage, VDS, as can be seen in Fig. 4(b). Therefore in Fig. 5, we have shown the minimum tunneling barrier width as a function of Lgap for different values of drain to source voltage VDS. We observe that the minimum tunneling barrier width approximately varies linearly with Lgap. To minimize the drain side ambipolar current, we need a larger tunneling barrier width for a given VDS. Fig. 6 shows the effect of the gate–drain electrode gap Lgap and the drain to source voltage VDS on the ambipolar current extracted at a gate to source voltage VGS = 0.5 V. It is clear from Fig. 6 that the ambipolar current can be minimized by increasing the gate–drain electrode gap (Lgap). A larger Lgap is equivalent to a wider depletion width and thus increases the tunneling barrier width at the channel–drain junction. For example, if VDS = 0.7 V, we need a minimum Lgap of 20 nm to suppress the ambipolar current. Therefore, our results indicate that doping the drain electrostatically provides a new design parameter, Lgap, to suppress the ambipolar current in a TFETs. In addition, our approach also leads to a low thermal budget process due to the absence of the need to chemically dope the drain region. 4. Conclusions In this paper, using 2D TCAD simulations, we have reported a method for realizing a PNPN TFET with a controllable tunnel barrier width on the drain side. We have demonstrated that the proposed PNPN TFET structure can be realized on a doped N+/P starting structure using electrostatic doping and therefore, without the need for additional chemically doped junctions. Our approach will minimize the thermal budget required to fabricate the PNPN TFET. We have shown that the use of electrostatic doping on the drain side of TFETs provides a new design parameter, the gate–drain electrode gap (Lgap), for controlling the drain side tunneling barrier width. As a result, the ambipolar current can be effectively suppressed by choosing an appropriate gate–drain electrode gap (Lgap). References [1] [2] [3] [4] [5] [6] [7] [8] [9]
A.C. Seabaugh, Q. Zhang, Low-voltage tunnel transistors for beyond CMOS logic, Proc. IEEE 98 (12) (2010) 2095–2110. A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy efficient electronic switches, Nature 479 (7373) (2011) 329–337. A.C. Seabaugh, H. Lu, Tunnel field-effect transistors – update, IEEE Int. Conf. Solid-State Integr. Circ. Technol. (12) (2014) 1–4. N.V. Nagavarapu, R. Jhaveri, J.C.S. Woo, The tunnel source (PNPN) n-MOSFET: a novel high performance transistor, IEEE Trans. Electron Dev. 55 (4) (2008) 1013–1019. O. Nayfeh, C. Chleirigh, J. Hennessy, L. Gomez, J. Hoyt, D. Antoniadis, Design of tunneling field-effect transistors using strained-silicon/strainedgermanium type-II staggered heterojunctions, IEEE Electron Dev. Lett. 29 (9) (2008) 1074–1077. D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu, D. Loubychev, J. Fastenau, S. Datta, Experimental staggered-source and N+ pocket-doped channel III–V tunnel field-effect transistors and their scalabilities, Appl. Phys. Express 4 (2) (2011) 024105–024106. F. Conzatti, M. Pala, D. Esseni, E. Bano, L. Selmi, Strain-induced performance improvements in InAs nanowire tunnel FETs, IEEE Trans. Electron Dev. 59 (8) (2012) 2085–2092. Q. Huang, R. Huang, Z. Zhan, Y. Qiu, W. Jiang, C. Wu, Y. Wang, A novel Si tunnel FET with 36 mV/dec subthreshold slope based on junction depletedmodulation through striped gate configuration, in: Proc. IEEE Int. Electron Devices Meeting, December 2012, pp. 1–4. W.Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field-effect transistors, IEEE Trans. Electron Dev. 57 (9) (2010) 2317–2319.
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[10] N. Cui, R. Liang, J. Xu, Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation, Appl. Phys. Lett. 98 (14) (2011) 142105. [11] M.J. Kumar, S. Janardhanan, Doping-less tunnel field effect transistor: design and investigation, IEEE Trans. Electron Dev. 60 (October) (2013) 3285– 3290. [12] D.B. Abdi, M.J. Kumar, Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain, IEEE J. Electron Dev. Soc. 2 (6) (2014) 187–190. [13] W. Cao, C.J. Yao, G.F. Jiao, D. Huang, H.Y. Yu, M-F. Li, Improvement in reliability of tunneling field-effect transistor with p-n-i-n structure, IEEE Trans. Electron Dev. 58 (7) (2011) 2122–2126. [14] S. Cho, I.M. Kang, Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics, Curr. Appl. Phys. 12 (3) (2012) 673–677. [15] S. Saurabh, M.J. Kumar, Investigation of the novel attributes of a dual material gate nanoscale tunnel field effect transistor, IEEE Trans. Electron Dev. 58 (February) (2011) 404–410. [16] M.S. Ram, D.B. Abdi, Single grain boundary tunnel field effect transistors on recrystallized polycrystalline silicon: proposal and investigation, IEEE Electron Dev. Lett. 35 (10) (2014) 989–991. [17] R. Jhaveri, N.V. Nagavarapu, J.C.S. Woo, Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor, IEEE Trans. Electron Dev. 58 (1) (2011) 80–86. [18] A. Tura, Z. Zhang, P. Liu, Y-H. Xie, J.C.S. Woo, Vertical silicon p-n-p-n tunnel nMOSFET with MBE-grown tunneling junction, IEEE Trans. Electron Dev. 58 (7) (2011) 1907–1913. [19] H.-Y. Chang, B. Adams, P.-Y. Chien, J. Li, J.C.S. Woo, Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing, IEEE Trans. Electron Dev. 60 (1) (2013) 92–96. [20] Y. Zhang, H.-Chu, Tunneling field effect transistor (TFET) with ultra-shallow pockets formed by asymmetric ion implantation and method of making same, US patent: 20140158990, June 2014. [21] D.B. Abdi, M.J. Kumar, In-built N+ pocket PNPN tunnel field-effect transistor, IEEE Electron Dev. Lett. 35 (12) (2014) 1170–1172. [22] B. Rajasekharan, R.J.E. Hueting, C. Salm, T. van Hemert, R.A.M. Wolters, J. Schmitz, Fabrication and characterization of the charge plasma diode, IEEE Electron Dev. Lett. 31 (6) (2010) 528–530. [23] R.J.E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, Charge plasma P-N diode, IEEE Electron Dev. Lett. 29 (12) (2008) 1367–1368. [24] M.J. Kumar, K. Nadda, Bipolar charge plasma transistor: a novel three terminal device, IEEE Trans. Electron Dev. 59 (4) (2012) 962–967. [25] K. Nadda, M.J. Kumar, Thin-film bipolar transistors on recrystallized polycrystalline silicon without impurity doped junctions: proposal and investigation, IEEE/OSA J. Disp. Technol. 10 (7) (2014) 590–594. [26] K. Nadda, M.J. Kumar, Vertical bipolar charge plasma transistor with buried metal layer, Sci. Rep. 5 (January) (2015) 1–6 (article no. 7860). [27] M.S. Ram, D.B. Abdi, Dopingless PNPN tunnel FET with improved performance: design and analysis, Superlattices Microstruct. 82 (June) (2015) 430– 437. [28] M.J. Kumar, M. Maheedhar, P.P. Varma, Junctionless biristor: a bistable resistor without chemically doped P-N junctions, IEEE J. Electron Dev. Soc. 3 (4) (2015) 311–315. [29] C. Sahu, J. Singh, Charge-plasma based process variation immune junctionless transistor, IEEE Electron Dev. Lett. 35 (3) (2014) 411–413. [30] ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, USA, 2014. [31] K. Boucart, A.M. Ionescu, Double gate tunnel FET with high-k gate dielectric, IEEE Trans. Electron Dev. 54 (7) (2007) 1725–1733. [32] A.S. Verhulst, W.G. Vandenberghe, K. Maex, G. Groeseneken, Tunnel field-effect transistor without gate–drain overlap, Appl. Phys. Lett. 91 (5) (2007) 053102–053103.