- Email: [email protected]
dec at low drain currents
Solid State Electronics xxx (xxxx) xxx–xxx
Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents ⁎
K. Narimani , S. Glass, P. Bernardy, N. von den Driesch, Q.T. Zhao, S. Mantl Peter-Grünberg-Institute (PGI9-IT), JARA-Fundamentals for Future Technology, Forschungszentrum Jülich, 52428 Jülich, Germany
A R T I C L E I N F O
A B S T R A C T
Keywords: Tunnel FET Line-tunneling Trap Assisted Tunneling (TAT)
In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10−7 A/µm at Vds = Von = Vgs − Voff = −0.5 V for an Ioff = 1 nA/µm and an average SS of 55 mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Id beats the MOSFET performance at low currents.
1. Introduction Tunnel FETs (TFETs) are promising candidates to overcome MOSFETs subthreshold slope (SS) limit of 60 mV/dec for low power computing and internet of things applications. Unlike MOSFETs which rely on thermionic emission of electrons or holes over a barrier, TFETs exploit quantum band to band tunneling of carriers through source to channel. This effect has less dependence on temperature and also filters out high and low energy tails of the Fermi distribution of carriers leading to steeper switching slopes [1]. Experimental demonstrations of TFETs using different materials have been already published [2,3]. Among these materials silicon TFETs show the best Ion/Ioff ratio [4], while having less on-current Ion compared to TFETs with III-V due to its indirect large bandgap. However, one of the huge advantages of silicon TFETs is that they are compatible with conventional CMOS fabrication processes which allows for advanced device designs and complementary circuits, as already demonstrated by Complementary-TFET inverters [5,6]. Moreover, different architectures of TFETs like planar, tri-gate and gate all around (GAA) Si nanowires have been reported [7,8]. GAA geometry greatly improves the gate electrostatic control over source-channel tunneling junction which leads to improvements in average SS, Ion/Ioff ratio and analogue characteristics like conductance and transconductance. Despite these improvements, Silicon TFETs, like other TFETs still suffer from degraded SS which can be attributed to improper dopant distribution profile and Trap Assisted Tunneling
⁎
(TAT). The latter contributes to premature thermionic increase of current before actual BTBT process begins, while the former leads to longer tunneling distance which in turn decreases tunneling probabilities and subthreshold slope (SS). Implantation into silicide (IIS) and low temperature annealing [9] were proposed as a solution to dopant profile optimization at the tunneling junction. In this paper, we take a novel approach to take advantage of line tunneling with source-gate overlap to improve the subthreshold slope and Ion of devices. Conventional point tunneling takes place at p-i or n-i junction, while in devices with source-gate overlap, provided with enough band bending, line tunneling occurs from the source to semiconductor-oxide interface (Fig. 1(a and b)). It has been shown that linetunneling can achieve steeper SS [10]. However, in a real device both of these contributions are present as depicted in Fig. 1(c). We take advantage of line-tunneling, as shown in Fig. 2, by first implantation and spike annealing using a dummy gate, and then etching down the source area to remove the end of range (EOR) implantation damage to reduce possible TAT and importantly to increase the electric field in the thinner area for line-tunneling with respect to the thicker part of the device where point-tunneling happens. 2. Device fabrication TFET devices as illustrated in Fig. 2 were fabricated on a 20 nm SOI wafer with 145 nm buried oxide as starting substrate. First, PECVD SiO2
Corresponding author. E-mail address: [email protected] (K. Narimani).
https://doi.org/10.1016/j.sse.2018.01.007
0038-1101/ © 2018 Elsevier Ltd. All rights reserved.
Please cite this article as: Narimani, K., Solid State Electronics (2018), https://doi.org/10.1016/j.sse.2018.01.007
Solid State Electronics xxx (xxxx) xxx–xxx
K. Narimani et al.
3. Experimental results 3.1. Transfer characteristics Fig. 4(a) presents the Id-Vg transfer characteristics of the fabricated pTFET device with 2 µm channel length and 2 µm gate width for a 1.5 keV phosphorus implantation dose of 2 × 1014 cm−2 at source which after activation corresponds to a dopant concentration of 3 × 1019 cm−3 at 5 nm thickness based on process simulations (Fig. 3(b)). Thenceforth we name this device T1. The device T1 shows steep increase of current with an average SS of 55 mV/dec over two decades of Id current between 10−13 to 1.5 × 10−11 A/µm at Vd = −0.1 V which is superior the state of the art GAA silicon nanowire pTEFTs with an average SS > 60 mV/dec [7]. Furthermore, the Ion/Ioff ratio is about 2.55 × 102 at Vds = Von = Vgs − Voff = −0.5 V for Ioff = 1 nA/µm. Fig. 4(b) shows a hump in the SS vs Id plot which divides the transfer curve into two parts. To explain the hump Fig. 5 depicts different tunneling regions and mechanisms in our device. Linetunneling occurs in two distinct regions, one region over the thinned source and other region over the thicker part of the device especially stronger at the top corner owing to the fringing field. To investigate in detail, TCAD simulation with Sentaurus was carried out. Models for fermi statistics, drift-diffusion transport, doping dependent SRH generation-recombination and non-local BTBT have been self-consistently solved with the Poisson equation for the structure. Parameters for the high-k dielectric and silicon were taken from the standard library of the TCAD software. Fig. 6(a) shows the simulated transfer characteristics of the device at Vd = −0.3 V. At Vg = −0.1 V line-tunneling initially starts at the top corner as a result of fringing field induced tunneling and then extends on the ramp due to contribution of Et and ER as indicated in Fig. 6(b). Increasing Vg to −1 V causes the line tunneling in the thinner area as shown by the contour of band to band generation in Fig. 6(c). This further increases the current but gives rise to the hump in the characteristics. Fig. 7(a) shows the transfer characteristics of a pTFET with a higher source implantation dose of 2 × 1015 cm−2 at 1.5 keV energy, which hereafter is called T2. Due to higher doping concentration the fringing field induced tunneling starts at an earlier voltage resulting in onsetvoltage shift of 0.25 V. On the other hand, a higher voltage Vg is required to form a depletion region for line-tunneling at the thin area of the source in the device T2 owing to the higher doping concentration. This also results in a hump which is clearly visible in SS vs Id plot for transistor T2 in Fig. 7(b) but occurs at a higher voltage compared to transistor T1. The hump in the transfer characteristics appears at Vg = −0.09 V for T1 whereas it appears at higher voltage of Vg = −0.21 V for T2 as a result of higher doping concentration.
Fig. 1. pTFET device configuration. (a) Tunneling path of carriers in case of point-tunneling, where tunneling occurs at the source channel interface. (b) Tunneling path of carriers in case of line-tunneling where the tunneling takes place in the gate/source overlapped region with a direction parallel to the gate electrical field. By applying a gate voltage a depletion/inversion region beneath the gate is formed and carriers tunnel to the oxide interface. (c) In a real device, both tunneling types contribute to the current.
was deposited and patterned to form the dummy gate. Then implantations of boron and phosphorus ions followed by high temperature spike annealing at 1050 °C were carried out to form the source and drain regions. Phosphorous was implanted with two different implantation doses of 2 × 1014 cm−2 and 2 × 1015 cm−2 to compare resulting devices. It should be noted that for each implantation step, the other side of the device was covered by photoresist to avoid intermixing of dopants. TRIM simulation of implantation for phosphorous in Fig. 3(a) shows that EOR damages reside at around 10 nm depth, indicating the importance of thinning down source area to less than 10 nm. The TCAD simulated dopant profile after annealing (Fig. 3(b)) further indicates an active dopant concentration of 3 × 1019 cm−3 for a dose of 2 × 1014 cm−2 at a depth of 15 nm, corresponding to a source thickness of 5 nm after thinning down as described below. After annealing, the dummy gate was removed and 60 nm PECVD SiO2 was deposited and patterned to open a window for thinning down the source junction. Source was etched down to 5 nm at room temperature by wet etching. Afterwards, 3 nm of ALD HfO2 and 60 nm of PVD TiN were deposited and patterned to form the High-k/Metal Gate stack. 2 nm of Ni was deposited and annealed at 750 °C for 30 s to form NiSi2 with smooth interface and low resistivity [11]. Fig. 2 schematically summarizes the key process steps.
Gate Drain
P+
P
Source
n+
Fig. 2. Fabrication schematics and key process steps. After implantation and activation, the source is thinned down through wet etching to get rid of EOR damages.
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Fig. 3. (a) TRIM simulation of the implantation. Point of maximum damage and EOR region are marked in the plot. (b) Net active dopant concentration achieved using Sentaurus TCAD process simulation for implantation and subsequent spike annealing at 1050 °C.
Fig. 4. (a) Transfer characteristics of T1 pTFET with lower source doping. (b) SS vs Id plot of the transfer curve. The bump in the curve indicates different line-tunneling onsets in the thicker area of the source due to fringing field and in the thinner area.
Et
behavior is achievable either by higher doping of the source junction or by using a lower bandgap material. However, as it was mentioned above, higher doping increases the onset voltages between the tunneling induced by the fringing field and tunneling at the thin source. Therefore we propose a structure where the doping is limited to only under the thin part of the source to get rid of tunneling caused by the fringing fields at the top corner as shown in Fig. 9(a). Now one can expect solely contribution of line-tunneling from the thinner area (Fig. 9(b)). Fig. 9(c) shows the simulated transfer characteristics of the proposed device which is hump free and has a steep subthreshold slope.
ER
Fig. 5. Schematics of different tunneling mechanisms in the fabricated device. Line tunneling takes place at the gate overlap with the thin area and also on the surface of thicker part of the device. Tunneling initially starts due to the fringing field at the top corner then extends over the ramp and finally on the thin part of the source. The source/ channel and drain/channel junctions are specified with dashed white lines.
3.2. Back gate bias To investigate how changing the geometry of the device helps to increase electrostatic control over the channel and improve the device characteristics, we treated the buried oxide and the substrate as a back gate for the transistor. Fig. 10 shows the transfer characteristics and SS vs Id plots for three different back gate bias voltages of Vbg = −10 V, 0 V, 10 V, respectively at Vd = −0.3 V for a transistor
Fig. 8 shows the output characteristics of the pTFET T1 for Vov = Vg − Voff = −0.5 V and −0.3 V where Ioff = 1 nA/µm. The characteristics shows super-linear onset of Id as Vd increases since transitions from shorter tunneling paths are made possible which result in this exponential dependence of Id on Vd [12]. A reduction of this
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Fig. 6. (a) Simulated transfer characteristics of the fabricated device at Vd = −0.3 V. (b), (c) show zoomed in contour of the device for different Vg. Source is on the right side, while drain is on the left and gate extends all over the top section of the device. (b) Contour of BTB generation at Vg = −0.1 V shows that line-tunneling first occurs at the corner due to the high fringing field. (c) BTB generation of carriers at Vg = −1 V shows that the hump in the characteristics is due to the late start of line-tunneling in the thinner area of source.
Fig. 7. (a) Measured transfer characteristics of pTFET T2 device with higher source doping. Notice the obvious shoulder in the curve, which is caused by stronger fringing field and starts earlier than line-tunneling at the thin part. (b) SS vs Id plot shows the effect of the bump more clearly.
extends from source all over the channel and covers all of drain doping area. So it is expected to affect the depletion region in the drain as well as the source. In case of a positive Vbg, the applied bias pushes the depletion region up and causes more band bending at the
doped like the device T1 shown in Fig. 4. It was observed that by applying a negative Vbg, Ion increases and minimum SS improves with some points under 60 mV/dec. On the other hand, a positive Vbg decreases Ion and degrades SS. It should be noted that the back gate
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Tri-gate and GAA NW devices, it would be possible to further enhance the characteristics of silicon line-tunneling FETs.
3.3. Analogue performance To investigate current saturation for analogue applications, output conductance gd = ∂Id/∂Vd in addition to output characteristics was evaluated as shown in Fig. 11. Since the tunneling junction of a TFET has a much higher resistance than the channel, TFETs do not suffer from short channel effects and show lower gd values and hence better saturation than MOSFETs. For our fabricated devices gd values drop in the range of 0.01 µS/µm which indicates very good saturation of Id and makes our devices suitable for implementation in circuits like differential amplifiers. In addition to gd, the transconductance gm and gm/Id transconductance efficiency have also been calculated as shown in Fig. 12. The transconductance gm = ∂Id/∂Vg is a measure of the electrostatic gate control and switching response. It is an important figure of merit for analogue design, and is directly proportional to voltage gain of a transistor. For our device gm is fairly low which is typical for planer devices. gm/Id = ∂Id/Id∂Vg = ln(10)/SS is the transconductance efficiency and is another important analogue device figure of merit as it relates current to amplification performance. As shown in Fig. 12, gm/Id surpasses the MOSFET limit and reaches the maximum value of 57 V−1, meaning that our pTFET outperforms MOSFET in sub 60 mV/dec region at low frequencies since gm values are limited and therefore cut-off frequency of the device should be small.
Fig. 8. Output characteristics of device T1 showing good saturation and slightly superlinear onset of drain current.
drain. This leads to higher ambipolar current due to the carrier contribution from drain and therefore an increase in the ambipolar current is measured. On the other hand, the negative Vbs, forms another depletion region on the source side of the device, which contributes to overall current, hence it leads to better SS and higher Ion current. This contribution mainly stems from thick part of the source, since the other part is too thin to form an effective band bending on the back gate side. Therefore by using other device structures such as
Fig. 9. The proposed device structure with the doping only in the thin area (a). (b) simulated BTB hole generation. In contrast to the previous device doping, now BTBT only takes place under the gate on the thin area of source. (c) Simulated transfer characteristics with improved subthreshold slope.
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Fig. 10. (a) Transfer characteristics of a pTFET device doped similar to the T1, with back gate bias at Vbg = −10 V, 0 V, 10 V. Gate leakage is shown for a reference. It is worth to note that for calculation of SS all Id points over the noise level and gate leakage were chosen. (b) SS vs Id plot shows the improvement in point subthreshold slope by exerting negative back bias.
4. Conclusion We have fabricated line-tunneling silicon pTFET with improved SS by first implantation and activation and then thinning down source to remove EOR damages to decrease TAT. Further analysis shows that for improvements, optimization of doping and different tunneling mechanisms in the device are required. Generally, line-tunneling gives rise to a steeper slope where electric field is stronger. In case of our device tunneling happens initially at the top corner due to fringing fields while the thinned source part of the device is the latest part where the linetunneling starts. As a work-around we proposed an optimized doping profile to get rid of the fringing field induced tunneling and improve the device characteristics. Acknowledgment This work is partially supported by the BMBF project UltraLowPower (16ES0060K) and the European project E2SWITCH.
Fig. 11. Calculated gd from output characteristics for T1. As it can be seen gd drops to small values indicating good current saturation which makes the fabricated device suitable for analogue device applications.
References [1] Ionescu AM, Riel H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 2011;479(7373):329–37. [2] Kazazis D, et al. Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator. Appl Phys Lett 2009;94(26). [3] Wirths S, et al. Band engineering and growth of tensile strained Ge/(Si)GeSn heterostructures for tunnel field effect transistors. Appl Phys Lett 2013;102(19). [4] Zhao Q-T, et al. Strained Si and SiGe nanowire tunnel FETs for logic and analog applications. IEEE J Electron Devices Soc 2015;3(3):103–14. [5] Luong GV, et al. Complementary strained Si GAA nanowire TFET inverter with suppressed ambipolarity. IEEE Electron Device Lett 2016;37(8):950–3. [6] Knoll L, et al. Inverters with strained Si nanowire complementary tunnel field-effect transistors. IEEE Electron Device Lett 2013;34(6):813–5. [7] Luong GV, et al. Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages. Solid State Electron 2015:8–15. [8] Knoll L, et al. Strained silicon based complementary tunnel-FETs: steep slope switches for energy efficient electronics. Solid State Electron 2014;98(August):32–7. [9] Knoll L et al. Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling. In: 2013 IEEE international electron devices meeting; 2013. p. 4.4.1–4.4.4. [10] Vandenberghe WG, Verhulst AS, Groeseneken G, Soree B, Magnus W. Analytical model for point and line tunneling in a tunnel field-effect transistor. In: Int. Conf. Simul. Semicond. Process. Devices, SISPAD, vol. i, no. 3; 2008. p. 137–40. [11] Knoll L, Zhao QT, Habicht S, Urban C, Ghyselen B, Mantl S. Ultrathin Ni silicides with low contact resistance on strained and unstrained silicon. IEEE Electron Device Lett Apr. 2010;31(4):350–2. [12] Verhulst AS, Leonelli D, Rooyackers R, Groeseneken G. Drain voltage dependent analytical model of tunnel field-effect transistors. J Appl Phys 2011;110(2).
Fig. 12. Transconductance efficiency vs Id calculated for T1. The MOSFET physical limit is also indicated in the plot. It is apparent from the plot that TFET can operate with values not achievable by MOSFETs at low frequencies. The inset of the image shows the gm of the measured device.
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K. Narimani et al. Keyvan Narimani received the B.Sc. and M.Sc. degrees in electrical engineering from the University of Tehran, Tehran, Iran, in 2011 and 2013, respectively. He is currently pursuing the Ph.D. degree with the Forschungszentrum Jülich, Peter Grünberg Institute 9, Jülich, Germany, with a focus on TFETs and circuits for low-power applications.
Nils von den Driesch received the B.Sc. and M.Sc. degrees in physics from the RWTH Aachen University, Aachen, Germany, in 2011 and 2013, respectively. He is currently pursuing the Ph.D. degree with the Forschungszentrum Jülich, Jülich, Germany, with a focus on CVD-based epitaxy of group IV materials.
Stefan Glass received the B.Sc. and M.Sc. degrees in nanostructure technology from the University of Wuerzburg, Würzburg, Germany, in 2012 and 2014, respectively. He is currently pursuing the Ph.D. degree with the Forschungszentrum Jülich, Jülich, Germany, with a focus on TFETs.
Dr. Qing-Tai Zhao received the Ph.D. degree from Peking University, Beijing, China, in 1993. He was with Peking University, Shenzhen, China. In 1997, he joined the Forschungszentrum Jülich, Peter Grünberg Institute 9, Jülich, Germany, where he is currently a Senior Research Scientist and the Leader of the Nano-Device Research Group. His current research interests include nanoelectronic devices.
Patric Bernardy received his bachelors from FH Jülich in chemical engineering and his master of science in polymer chemistry from RWTH Aachen. Since 2009 he has been working in PGI9 institute of Forschungszentrum Jülich mostly dealing with RTP and surface chemistry.
Prof. Siegfried Mantl is currently the Head of the Ion Beam Division, Peter Grünberg Institute 9, Jülich, Germany, a Professor of physics with RWTH Aachen University, Aachen, Germany. He holds an honorary Helmholtz professorship. His current research interests include siliconrelated nanoelectronic materials and devices.
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Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents ⁎
K. Narimani , S. Glass, P. Bernardy, N. von den Driesch, Q.T. Zhao, S. Mantl Peter-Grünberg-Institute (PGI9-IT), JARA-Fundamentals for Future Technology, Forschungszentrum Jülich, 52428 Jülich, Germany
A R T I C L E I N F O
A B S T R A C T
Keywords: Tunnel FET Line-tunneling Trap Assisted Tunneling (TAT)
In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10−7 A/µm at Vds = Von = Vgs − Voff = −0.5 V for an Ioff = 1 nA/µm and an average SS of 55 mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Id beats the MOSFET performance at low currents.
1. Introduction Tunnel FETs (TFETs) are promising candidates to overcome MOSFETs subthreshold slope (SS) limit of 60 mV/dec for low power computing and internet of things applications. Unlike MOSFETs which rely on thermionic emission of electrons or holes over a barrier, TFETs exploit quantum band to band tunneling of carriers through source to channel. This effect has less dependence on temperature and also filters out high and low energy tails of the Fermi distribution of carriers leading to steeper switching slopes [1]. Experimental demonstrations of TFETs using different materials have been already published [2,3]. Among these materials silicon TFETs show the best Ion/Ioff ratio [4], while having less on-current Ion compared to TFETs with III-V due to its indirect large bandgap. However, one of the huge advantages of silicon TFETs is that they are compatible with conventional CMOS fabrication processes which allows for advanced device designs and complementary circuits, as already demonstrated by Complementary-TFET inverters [5,6]. Moreover, different architectures of TFETs like planar, tri-gate and gate all around (GAA) Si nanowires have been reported [7,8]. GAA geometry greatly improves the gate electrostatic control over source-channel tunneling junction which leads to improvements in average SS, Ion/Ioff ratio and analogue characteristics like conductance and transconductance. Despite these improvements, Silicon TFETs, like other TFETs still suffer from degraded SS which can be attributed to improper dopant distribution profile and Trap Assisted Tunneling
⁎
(TAT). The latter contributes to premature thermionic increase of current before actual BTBT process begins, while the former leads to longer tunneling distance which in turn decreases tunneling probabilities and subthreshold slope (SS). Implantation into silicide (IIS) and low temperature annealing [9] were proposed as a solution to dopant profile optimization at the tunneling junction. In this paper, we take a novel approach to take advantage of line tunneling with source-gate overlap to improve the subthreshold slope and Ion of devices. Conventional point tunneling takes place at p-i or n-i junction, while in devices with source-gate overlap, provided with enough band bending, line tunneling occurs from the source to semiconductor-oxide interface (Fig. 1(a and b)). It has been shown that linetunneling can achieve steeper SS [10]. However, in a real device both of these contributions are present as depicted in Fig. 1(c). We take advantage of line-tunneling, as shown in Fig. 2, by first implantation and spike annealing using a dummy gate, and then etching down the source area to remove the end of range (EOR) implantation damage to reduce possible TAT and importantly to increase the electric field in the thinner area for line-tunneling with respect to the thicker part of the device where point-tunneling happens. 2. Device fabrication TFET devices as illustrated in Fig. 2 were fabricated on a 20 nm SOI wafer with 145 nm buried oxide as starting substrate. First, PECVD SiO2
Corresponding author. E-mail address: [email protected] (K. Narimani).
https://doi.org/10.1016/j.sse.2018.01.007
0038-1101/ © 2018 Elsevier Ltd. All rights reserved.
Please cite this article as: Narimani, K., Solid State Electronics (2018), https://doi.org/10.1016/j.sse.2018.01.007
Solid State Electronics xxx (xxxx) xxx–xxx
K. Narimani et al.
3. Experimental results 3.1. Transfer characteristics Fig. 4(a) presents the Id-Vg transfer characteristics of the fabricated pTFET device with 2 µm channel length and 2 µm gate width for a 1.5 keV phosphorus implantation dose of 2 × 1014 cm−2 at source which after activation corresponds to a dopant concentration of 3 × 1019 cm−3 at 5 nm thickness based on process simulations (Fig. 3(b)). Thenceforth we name this device T1. The device T1 shows steep increase of current with an average SS of 55 mV/dec over two decades of Id current between 10−13 to 1.5 × 10−11 A/µm at Vd = −0.1 V which is superior the state of the art GAA silicon nanowire pTEFTs with an average SS > 60 mV/dec [7]. Furthermore, the Ion/Ioff ratio is about 2.55 × 102 at Vds = Von = Vgs − Voff = −0.5 V for Ioff = 1 nA/µm. Fig. 4(b) shows a hump in the SS vs Id plot which divides the transfer curve into two parts. To explain the hump Fig. 5 depicts different tunneling regions and mechanisms in our device. Linetunneling occurs in two distinct regions, one region over the thinned source and other region over the thicker part of the device especially stronger at the top corner owing to the fringing field. To investigate in detail, TCAD simulation with Sentaurus was carried out. Models for fermi statistics, drift-diffusion transport, doping dependent SRH generation-recombination and non-local BTBT have been self-consistently solved with the Poisson equation for the structure. Parameters for the high-k dielectric and silicon were taken from the standard library of the TCAD software. Fig. 6(a) shows the simulated transfer characteristics of the device at Vd = −0.3 V. At Vg = −0.1 V line-tunneling initially starts at the top corner as a result of fringing field induced tunneling and then extends on the ramp due to contribution of Et and ER as indicated in Fig. 6(b). Increasing Vg to −1 V causes the line tunneling in the thinner area as shown by the contour of band to band generation in Fig. 6(c). This further increases the current but gives rise to the hump in the characteristics. Fig. 7(a) shows the transfer characteristics of a pTFET with a higher source implantation dose of 2 × 1015 cm−2 at 1.5 keV energy, which hereafter is called T2. Due to higher doping concentration the fringing field induced tunneling starts at an earlier voltage resulting in onsetvoltage shift of 0.25 V. On the other hand, a higher voltage Vg is required to form a depletion region for line-tunneling at the thin area of the source in the device T2 owing to the higher doping concentration. This also results in a hump which is clearly visible in SS vs Id plot for transistor T2 in Fig. 7(b) but occurs at a higher voltage compared to transistor T1. The hump in the transfer characteristics appears at Vg = −0.09 V for T1 whereas it appears at higher voltage of Vg = −0.21 V for T2 as a result of higher doping concentration.
Fig. 1. pTFET device configuration. (a) Tunneling path of carriers in case of point-tunneling, where tunneling occurs at the source channel interface. (b) Tunneling path of carriers in case of line-tunneling where the tunneling takes place in the gate/source overlapped region with a direction parallel to the gate electrical field. By applying a gate voltage a depletion/inversion region beneath the gate is formed and carriers tunnel to the oxide interface. (c) In a real device, both tunneling types contribute to the current.
was deposited and patterned to form the dummy gate. Then implantations of boron and phosphorus ions followed by high temperature spike annealing at 1050 °C were carried out to form the source and drain regions. Phosphorous was implanted with two different implantation doses of 2 × 1014 cm−2 and 2 × 1015 cm−2 to compare resulting devices. It should be noted that for each implantation step, the other side of the device was covered by photoresist to avoid intermixing of dopants. TRIM simulation of implantation for phosphorous in Fig. 3(a) shows that EOR damages reside at around 10 nm depth, indicating the importance of thinning down source area to less than 10 nm. The TCAD simulated dopant profile after annealing (Fig. 3(b)) further indicates an active dopant concentration of 3 × 1019 cm−3 for a dose of 2 × 1014 cm−2 at a depth of 15 nm, corresponding to a source thickness of 5 nm after thinning down as described below. After annealing, the dummy gate was removed and 60 nm PECVD SiO2 was deposited and patterned to open a window for thinning down the source junction. Source was etched down to 5 nm at room temperature by wet etching. Afterwards, 3 nm of ALD HfO2 and 60 nm of PVD TiN were deposited and patterned to form the High-k/Metal Gate stack. 2 nm of Ni was deposited and annealed at 750 °C for 30 s to form NiSi2 with smooth interface and low resistivity [11]. Fig. 2 schematically summarizes the key process steps.
Gate Drain
P+
P
Source
n+
Fig. 2. Fabrication schematics and key process steps. After implantation and activation, the source is thinned down through wet etching to get rid of EOR damages.
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Fig. 3. (a) TRIM simulation of the implantation. Point of maximum damage and EOR region are marked in the plot. (b) Net active dopant concentration achieved using Sentaurus TCAD process simulation for implantation and subsequent spike annealing at 1050 °C.
Fig. 4. (a) Transfer characteristics of T1 pTFET with lower source doping. (b) SS vs Id plot of the transfer curve. The bump in the curve indicates different line-tunneling onsets in the thicker area of the source due to fringing field and in the thinner area.
Et
behavior is achievable either by higher doping of the source junction or by using a lower bandgap material. However, as it was mentioned above, higher doping increases the onset voltages between the tunneling induced by the fringing field and tunneling at the thin source. Therefore we propose a structure where the doping is limited to only under the thin part of the source to get rid of tunneling caused by the fringing fields at the top corner as shown in Fig. 9(a). Now one can expect solely contribution of line-tunneling from the thinner area (Fig. 9(b)). Fig. 9(c) shows the simulated transfer characteristics of the proposed device which is hump free and has a steep subthreshold slope.
ER
Fig. 5. Schematics of different tunneling mechanisms in the fabricated device. Line tunneling takes place at the gate overlap with the thin area and also on the surface of thicker part of the device. Tunneling initially starts due to the fringing field at the top corner then extends over the ramp and finally on the thin part of the source. The source/ channel and drain/channel junctions are specified with dashed white lines.
3.2. Back gate bias To investigate how changing the geometry of the device helps to increase electrostatic control over the channel and improve the device characteristics, we treated the buried oxide and the substrate as a back gate for the transistor. Fig. 10 shows the transfer characteristics and SS vs Id plots for three different back gate bias voltages of Vbg = −10 V, 0 V, 10 V, respectively at Vd = −0.3 V for a transistor
Fig. 8 shows the output characteristics of the pTFET T1 for Vov = Vg − Voff = −0.5 V and −0.3 V where Ioff = 1 nA/µm. The characteristics shows super-linear onset of Id as Vd increases since transitions from shorter tunneling paths are made possible which result in this exponential dependence of Id on Vd [12]. A reduction of this
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Fig. 6. (a) Simulated transfer characteristics of the fabricated device at Vd = −0.3 V. (b), (c) show zoomed in contour of the device for different Vg. Source is on the right side, while drain is on the left and gate extends all over the top section of the device. (b) Contour of BTB generation at Vg = −0.1 V shows that line-tunneling first occurs at the corner due to the high fringing field. (c) BTB generation of carriers at Vg = −1 V shows that the hump in the characteristics is due to the late start of line-tunneling in the thinner area of source.
Fig. 7. (a) Measured transfer characteristics of pTFET T2 device with higher source doping. Notice the obvious shoulder in the curve, which is caused by stronger fringing field and starts earlier than line-tunneling at the thin part. (b) SS vs Id plot shows the effect of the bump more clearly.
extends from source all over the channel and covers all of drain doping area. So it is expected to affect the depletion region in the drain as well as the source. In case of a positive Vbg, the applied bias pushes the depletion region up and causes more band bending at the
doped like the device T1 shown in Fig. 4. It was observed that by applying a negative Vbg, Ion increases and minimum SS improves with some points under 60 mV/dec. On the other hand, a positive Vbg decreases Ion and degrades SS. It should be noted that the back gate
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Tri-gate and GAA NW devices, it would be possible to further enhance the characteristics of silicon line-tunneling FETs.
3.3. Analogue performance To investigate current saturation for analogue applications, output conductance gd = ∂Id/∂Vd in addition to output characteristics was evaluated as shown in Fig. 11. Since the tunneling junction of a TFET has a much higher resistance than the channel, TFETs do not suffer from short channel effects and show lower gd values and hence better saturation than MOSFETs. For our fabricated devices gd values drop in the range of 0.01 µS/µm which indicates very good saturation of Id and makes our devices suitable for implementation in circuits like differential amplifiers. In addition to gd, the transconductance gm and gm/Id transconductance efficiency have also been calculated as shown in Fig. 12. The transconductance gm = ∂Id/∂Vg is a measure of the electrostatic gate control and switching response. It is an important figure of merit for analogue design, and is directly proportional to voltage gain of a transistor. For our device gm is fairly low which is typical for planer devices. gm/Id = ∂Id/Id∂Vg = ln(10)/SS is the transconductance efficiency and is another important analogue device figure of merit as it relates current to amplification performance. As shown in Fig. 12, gm/Id surpasses the MOSFET limit and reaches the maximum value of 57 V−1, meaning that our pTFET outperforms MOSFET in sub 60 mV/dec region at low frequencies since gm values are limited and therefore cut-off frequency of the device should be small.
Fig. 8. Output characteristics of device T1 showing good saturation and slightly superlinear onset of drain current.
drain. This leads to higher ambipolar current due to the carrier contribution from drain and therefore an increase in the ambipolar current is measured. On the other hand, the negative Vbs, forms another depletion region on the source side of the device, which contributes to overall current, hence it leads to better SS and higher Ion current. This contribution mainly stems from thick part of the source, since the other part is too thin to form an effective band bending on the back gate side. Therefore by using other device structures such as
Fig. 9. The proposed device structure with the doping only in the thin area (a). (b) simulated BTB hole generation. In contrast to the previous device doping, now BTBT only takes place under the gate on the thin area of source. (c) Simulated transfer characteristics with improved subthreshold slope.
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Fig. 10. (a) Transfer characteristics of a pTFET device doped similar to the T1, with back gate bias at Vbg = −10 V, 0 V, 10 V. Gate leakage is shown for a reference. It is worth to note that for calculation of SS all Id points over the noise level and gate leakage were chosen. (b) SS vs Id plot shows the improvement in point subthreshold slope by exerting negative back bias.
4. Conclusion We have fabricated line-tunneling silicon pTFET with improved SS by first implantation and activation and then thinning down source to remove EOR damages to decrease TAT. Further analysis shows that for improvements, optimization of doping and different tunneling mechanisms in the device are required. Generally, line-tunneling gives rise to a steeper slope where electric field is stronger. In case of our device tunneling happens initially at the top corner due to fringing fields while the thinned source part of the device is the latest part where the linetunneling starts. As a work-around we proposed an optimized doping profile to get rid of the fringing field induced tunneling and improve the device characteristics. Acknowledgment This work is partially supported by the BMBF project UltraLowPower (16ES0060K) and the European project E2SWITCH.
Fig. 11. Calculated gd from output characteristics for T1. As it can be seen gd drops to small values indicating good current saturation which makes the fabricated device suitable for analogue device applications.
References [1] Ionescu AM, Riel H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 2011;479(7373):329–37. [2] Kazazis D, et al. Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator. Appl Phys Lett 2009;94(26). [3] Wirths S, et al. Band engineering and growth of tensile strained Ge/(Si)GeSn heterostructures for tunnel field effect transistors. Appl Phys Lett 2013;102(19). [4] Zhao Q-T, et al. Strained Si and SiGe nanowire tunnel FETs for logic and analog applications. IEEE J Electron Devices Soc 2015;3(3):103–14. [5] Luong GV, et al. Complementary strained Si GAA nanowire TFET inverter with suppressed ambipolarity. IEEE Electron Device Lett 2016;37(8):950–3. [6] Knoll L, et al. Inverters with strained Si nanowire complementary tunnel field-effect transistors. IEEE Electron Device Lett 2013;34(6):813–5. [7] Luong GV, et al. Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages. Solid State Electron 2015:8–15. [8] Knoll L, et al. Strained silicon based complementary tunnel-FETs: steep slope switches for energy efficient electronics. Solid State Electron 2014;98(August):32–7. [9] Knoll L et al. Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling. In: 2013 IEEE international electron devices meeting; 2013. p. 4.4.1–4.4.4. [10] Vandenberghe WG, Verhulst AS, Groeseneken G, Soree B, Magnus W. Analytical model for point and line tunneling in a tunnel field-effect transistor. In: Int. Conf. Simul. Semicond. Process. Devices, SISPAD, vol. i, no. 3; 2008. p. 137–40. [11] Knoll L, Zhao QT, Habicht S, Urban C, Ghyselen B, Mantl S. Ultrathin Ni silicides with low contact resistance on strained and unstrained silicon. IEEE Electron Device Lett Apr. 2010;31(4):350–2. [12] Verhulst AS, Leonelli D, Rooyackers R, Groeseneken G. Drain voltage dependent analytical model of tunnel field-effect transistors. J Appl Phys 2011;110(2).
Fig. 12. Transconductance efficiency vs Id calculated for T1. The MOSFET physical limit is also indicated in the plot. It is apparent from the plot that TFET can operate with values not achievable by MOSFETs at low frequencies. The inset of the image shows the gm of the measured device.
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K. Narimani et al. Keyvan Narimani received the B.Sc. and M.Sc. degrees in electrical engineering from the University of Tehran, Tehran, Iran, in 2011 and 2013, respectively. He is currently pursuing the Ph.D. degree with the Forschungszentrum Jülich, Peter Grünberg Institute 9, Jülich, Germany, with a focus on TFETs and circuits for low-power applications.
Nils von den Driesch received the B.Sc. and M.Sc. degrees in physics from the RWTH Aachen University, Aachen, Germany, in 2011 and 2013, respectively. He is currently pursuing the Ph.D. degree with the Forschungszentrum Jülich, Jülich, Germany, with a focus on CVD-based epitaxy of group IV materials.
Stefan Glass received the B.Sc. and M.Sc. degrees in nanostructure technology from the University of Wuerzburg, Würzburg, Germany, in 2012 and 2014, respectively. He is currently pursuing the Ph.D. degree with the Forschungszentrum Jülich, Jülich, Germany, with a focus on TFETs.
Dr. Qing-Tai Zhao received the Ph.D. degree from Peking University, Beijing, China, in 1993. He was with Peking University, Shenzhen, China. In 1997, he joined the Forschungszentrum Jülich, Peter Grünberg Institute 9, Jülich, Germany, where he is currently a Senior Research Scientist and the Leader of the Nano-Device Research Group. His current research interests include nanoelectronic devices.
Patric Bernardy received his bachelors from FH Jülich in chemical engineering and his master of science in polymer chemistry from RWTH Aachen. Since 2009 he has been working in PGI9 institute of Forschungszentrum Jülich mostly dealing with RTP and surface chemistry.
Prof. Siegfried Mantl is currently the Head of the Ion Beam Division, Peter Grünberg Institute 9, Jülich, Germany, a Professor of physics with RWTH Aachen University, Aachen, Germany. He holds an honorary Helmholtz professorship. His current research interests include siliconrelated nanoelectronic materials and devices.
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