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The “barrier mode” behaviour of a junction FET at low drain currents
Solid-State
Efecbonics, 1975, Vol. 18, pp. 1013-1017.
Pergamon Press.
Prinkd
in Great Britain
THE “BARRIER MODE” BEHAVIOUR OF A JUNCTION FET AT LOW DRAIN CURRENTS R. J. BREWER Mullard Research Laboratories, Redhill, Surrey, England (Recked 9 January 1975) Abstract-The behaviour of a junction FET with a gate-source reverse bias exceeding the pinch-off voltage is discussed. It is seen that both the transfer and output characteristics have an exponential character, and this is attributed to the presence of a potential barrier between the source and drain, Simple expressions are given for both the conductance and transconductance in terms of parameters which, in the case of long gate devices, may be evaluated analytically, or, in the case of short gate devices, evaluated numerically using a relatively simple computer
model.
1.INTRODUCTION
The behaviour of a junction field-effect transistor (JFET) with the gate-drain reverse bias beyond pinch-off, but with the gate-source reverse bias at or below pinch-off, has been extensively studied [ 11. In this paper, however, we consider the case where the gate-source reverse bias exceeds the pinch-off voltage, which we define as the gate voltage at which, with zero source-drain voltage, the gate and substrate depletion regions just meet in the channel. The drain current under these conditions will be small. Certain of the properties of a JFET at low drain currents have been observed, and remarked upon in the literature [4,5], but no detailed physical or mathematical analysis has previously been attempted. The analogous problem of the behaviour of a MOSFET with a gate voltage short of the classical inversion point has been discussed in detail elsewhere [2,31. 2.PBySlCAL MODEL
Consider the idealised JFET shown schematically in Fig. 1. If initially there is no source-drain voltage, and the gate-source reverse bias equals the pinch-off voltage, the gate and substrate depletion regions will, by definition, just meet in the centre of the channel, and there will be a plane of conducting material at source potential connecting the source and drain. If the gate reverse bias is then increased, the potential in the channel will rise above the source potential, so that free carriers enter the substantially depleted channel by thermal excitation over a potential barrier of height Vs. When the drain voltage, V,, is applied, it induces a screening charge on the drain end of the gate so that the penetration of the drain field into
Source
rt’ n+ I
x
--\--
\
Late 1
1
Negative
t Potential
IDrain 1
P+ _-
“-type
___
P Y
the channel is limited and the potential within the channel remains largely unaffected. The features of the resultant potential distribution within the device are illustrated by Fig. 2. In a more typical asymmetric structure with a heavily doped gate and lightly doped substrate the potential distribution will be relatively complicated, but it will be shown later that the same qualitative physical features occur. Under these conditions, the channel potential will be closely coupled to the gate potential, while it may be shown that the effective depth of the channel will be of the order of the extrinsic Debye length, and will not vary much. Thus whereas in the normal mode of operation of an FET the drain current varies because variations in the gate potential modulate the depth of a conducting channel, in this “barrier mode” the effective channel depth does not vary, but the gate potential modulates the height of a potential barrier between the source and drain. This is analogous to the modulation of the emitter current in a bipolar transistor by the height of the potential barrier at the emitter-base junction, and indeed close formal
1 Substrate
Fig. 1, Schematic representation of the JFET
Fig. 2. Potential distribution throughout the JFET when V,, > VP. 1013
R. J. BREWER
1014
similarities exist between the behaviour of a “barrier mode” JFET and that of a bipolar transistor. 3. COMPUTER MODEL
To find the exact potential distribution within a JFET a numerical method must be used. The electrostatic potential at all points within a semiconductor is determined by the charge distribution according to Poisson’s equation. Also, due to the mobility of the charge carriers, the charge distribution is influenced by the potential distribution, so that an iterative method must be used to find a self-consistent solution. In the case we consider, if the channel is biassed with respect to the source sufficiently for the density of free charge in the channel to be small compared to the density of ionised impurities, the effect of the free carriers on the potential distribution within the depletion regions will be negligible. We may thus specify the charge distribution simply by specifying the shape of the depletion regions and the doping density. The computer program then solves Poisson’s equation to give the potential distribution, using a conventional two-dimensional finite difference method [6]. The solution is then examined for self-consistency, If the electrostatic field perpendicular to the depletion edges does not vanish at the edges, this implies that these boundaries have been incorrectly specified, since the current density in the barrier mode is always expected to be small. If there is no potential barrier, of at least several H/e, between the source and channel, this invalidates the assumption that the free charge in the channel has an effect on the potential distribution which is negligible compared to the fixed charge, and implies that a gate voltage inappropriate to the model has been specified. Adjustments are then made to the dimensions of the depletion regions and the electrode potentials until a self-consistent solution is obtained. The resultant potential distribution is thus approximate, due to the simplifications which have been used, but only needs a relatively simple, well-established computer program, and since it is very difficult to measure the geometry of a real device very accurately, any lack of accuracy in this computational method is believed to be unimportant compared to the likely errors in the input data. The computed potential down the length of the channel for one practical structure is shown in Fig. 3. The device has an annular gate of radius 60 km and length 10 pm. The channel is formed in a layer with a gaussian doping profile with a peak doping of 1.7 x lOI cm-’ in a lightly doped substrate of 10’”cm-‘. The gate junction is coincident with
the peak of the layer doping profile, with a separation of one micron between the gate and substrate junctions. The computation was performed with a gate reverse bias of 2.5 volts. Note the potential barrier between the source and channel, and the limited penetration of the drain field into the channel. 4. THEORY
Very long gate devices Consider a double gate device, as in Fig. 1 with the gate and substrate connected, where the gate length is very much greater than the channel depth. The potential distribution within the channel is then approximately one-dimensional, with a negligible longitudinal field, and the current will flow by diffusion. The barrier height is given by V, = V, - VP where V. is the gate-source reverse bias and V, is the pinch-off voltage. The diffusion current is
where N, and N2 are the free carrier concentrations at the source and drain ends of the channel, L is the channel length, and wcffis the effective channel depth. Now it may be shown that the number of free carriers in a parabolic potential trough is equal to the number in a square-section trough of width (27r)“*L,, where LD is the extrinsic Debye length. So if the channel is uniformly doped and the density of free charge is small compared to the density of fixed charge wefl= (2P)“*Ln = (2z$* where No is the doping concentration and VT= kT/e. Also N,=N,exp
(
--p
.r )
and N2=Noexp
(
-
Thus from the above jZD1 = N,$(2?r)““L,
exp (g)
exp
x[l-exp(-$$)I. Gate
length
Fig. 3. Computed potential profile along the line of potential minimum between the source and drain.
(- y) (1)
1015
The “barriermode” behaviour of a junction FET at low drain currents Note the close formal similarity between this expression and that for the collector current in a bipolar transistor. A similar expression has also been derived and experimeotally verified for the subthreshold region of operation of a MOSFET [2,3]. Short gate devices 10 these devices the fields in the channel will be two-dimensional, so that the current flow is by a mixture of drift and diffusion, and an exact analysis requires a numerical solution to the current transport equations. However, an approximate analytic expression for the device characteristics may be derived from two simple assumptions. The first is that the height of the potential barrier is linearly coupled to both the gate and the drain potentials. By Poisson’s equation, the change in potential at any given point due to a system of fixed charges and electrodes is linearly dependent upon a change in potential of any given electrode. Now when the gate or drain potential in a JFET is changed, this varies both the dimensions of the depletion regions and the position of the potential barrier; however, for small changes in the electrode potentials, so that these movements are small compared to the dimensions of the device, the assumption of linearity is good. Thus AVB = (YAV, +pAV,.
The second assumption is that the drain current varies exponentially with the height of the potential barrier, normalised to kT/e. Although the justification for this assumption is experimental, it appears physically plausible: if the shape of the potential profile in the channel remains substantially constant, the mix of drift and diffusion will not vary, and the current level will just be proportional to the free carrier population, which will vary exponentially with the potential difference between the source and channel. Then by differentiating the exponential function we obtain
AID -+A&, -= ID T
Mv
the barrier height. Secondly, the drain voltage also modulates the dimensions of the gate and substrate depletion regions, so that the coupling between the drain and the potential barrier will be somewhat non-linear. The transcooductaoce, however, should be very close indeed to exponential, since a range of drain currents of several orders of magnitude corresponds to a change in gate potential of only a few hundred millivolts. If the device is operated with the substrate potential fixed, the transcooductaoce will be lower, due to the coupling between the substrate and the potential barrier. This effect may be computed, and may be reduced by increasing the depth of the substrate depletion region. 5. EXPERIMENTAL. RESULTS The transfer and output characteristics at low drain currents of a long gate JFET were measured. The device had an annular gate of radius 60 pm and length 20 pm diffused into an n-type layer formed by a 150KeV phosphorus implant which was driven in for 16 hr at 1100°C:the dose was 8 x 10” ions/cm*. The substrate was p-type with a resistivity of 30&cm. The separation between the gate and layer metallurgical junctions was about 0.4pm, so that the channel length to depth was about 50. The gate and substrate were connected, to simulate a double-gate device. The variation of drain current with gate voltage at two temperatures is shown in Fig. 4. The variation is, as expected, exponential, with measured slopes of 39.1 and 60.4 millivolts per decade,
B
=- 1 -IrhVo~+/3AV,~] G Vr
D
(2)
for small changes in the electrode potentials. The parameters a and /3 may be evaluated numerically by computing the barrier height, using the method described in Section (3), for a closely spaced range of gate and drain voltages. It is found that (Y and /3 are determined primarily by the length to depth ratio of the channel, and with experience may be estimated simply from an inspection of the device geometry. The differeotial conductance and traoscooductance may then be predicted from’eqo (2). This method does not, however, yield an expression for the absolute current level. The variation of drain current with drain voltage will not be exactly exponential for two reasons. First, large variations in the drain voltage will vary the mix of drift and diffusion currents in the channel, so that the drain current will not have an exact exponential dependence on
: 1
01
02
,
03 Gate
04 voltage
05
I
06
07
(V)
Fig. 4. Transfer characteristics for a very long gate device. The solid lines are best fits through the experimental points.
R. J. BREWER
1016
compared to the theoretical values of 39.7 and 595 respectively from eqn (I), which shows that the slope is dependent solely upon the absolute temperature. (No attempt has been made to fit the observed and theoretical absolute current level, since eqn (1) shows it to vary exponentially with VP,which is not known independently to the required accuracy.) The variation of drain current with drain voltage is shown in Fig. 5: the fit between the experimental results and the theoretical curves derived from eqn.(l) is seen to be good. (The drain current has been normalised to give a best fit, since eqn (1) shows that the absolute current level is determined by various device parameters which cannot be measured very accurately in a real device, while the shape of the curve depends solely upon the absolute temperature.) At drain voltages much above about a hundred millivolts, the drain current is substantially constant, increasing only very slowly with increasing voltage. The transfer and output characteristics of a short gate JFET were measured. The device was similar to the long gate device already described, except that the gate length
was 5 pm and the channel deeper, so that the channel length-to-depth ratio was about 2.5. It was operated with the gate and substrate connected together. The device transfer curves at 2W’K and 300°K are shown in Fig. 6: a typical output curve is shown in Fig. 7. From these curves values for (r and ,9 may be derived using eqn (2), and compared with those predicted by the computer simulation (Table (1)). The channel conductance parameter /3 is very sensitive to the length-to-depth ratio of the channel, ranging from -10-l for a very short gate device to a virtually unmeasurable value, - lO4, for a very long gate device, such as that discussed previously, so that it is very difficult to obtain a theoretical prediction accurate to better than a factor two. The transconduc-
1
50 Drain
100 voltage
200
150 CmV)
Fig. 5. Output characteristics for a very long gate device. The lines are theoretical curves from eqn (I): the points are experimental. lo-
*_ .
.
\.
\ . \ .
\.
10 9.
T=300K
T: ZOOK
\
\
.
i
2 F :
\
,o-’ 10.
\ .
.
: u
k
\
b
\ .
.
L 50
‘\
Substrateleakage
51
52 Gate
53 5.4 voltage(V)
I
I
I
5
6
7
Drain
\
10'12
I
4 voltage
(VI
Fig. 7. Output characteristic for a short gate device. The solid line is a best fit through the experimental points. A value for r9 of 3.7 x lo-’ at 5 volts may be derived using eqn (2).
\ .
lo-111
I
3
l1. drolP
/ 5 5
5 6
Fig. 6. Transfer characteristics for a short gate device. The solid lines are best tits through the experimental points. Values for (I of 0.67 at 200°Kand 0.65 at 300°Kmay be derived using eqn (2).
The “barrier mode” behaviour of a junction FET at low drain currents
tance parameter, a, is much less variable, ranging from perhaps 0.5 for a very short gate device to very close to unity for a long gate device, and is thus rather more accurately predictable.
1017
operated in the barrier mode is low, the transconductance per unit drain current rises to a value close to that of a bipolar transistor, while very high input and output impedances are readily attainable. For some applications * this may be a useful combination of properties.
CONCLUSIONS
The transfer and output characteristics of. a junction FET at low drain currents are dominated by the presence of a potential barrier between the source and drain, with free carriers entering the channel by thermal excitation. The barrier height may be modulated by both the gate and drain potentials, although with the usual geometries the barrier is more closely coupled to the gate than to the drain, so that the drain current is more sensitive to the gate potential than to the drain voltage. Although the absolute transconductance of a JFET
Acknowledgements--I would like to acknowledge many useful discussions with J. R. A. Beale and J. M. Shannon. REFERENCES 1. C. K. Kim and E. S. Yang, IEEE Trans. ElectronDevices 17, 120 (1970). 2. M. B. Barron, Solid-St. Electron. 15, 293 (1972). 3. R. R: Troutman, IEEE I. Solid-St. Cir. 9, 55 (1974). 4. L. Evans and K. A. Pullen, Proc. IEEE 54,82 (1%6). 5. E. 0. Johnson, RCA Reo. 34,80 (1973). 6. C. Weber, Philips Tech. Rev. 24, 130 (1%3).
Efecbonics, 1975, Vol. 18, pp. 1013-1017.
Pergamon Press.
Prinkd
in Great Britain
THE “BARRIER MODE” BEHAVIOUR OF A JUNCTION FET AT LOW DRAIN CURRENTS R. J. BREWER Mullard Research Laboratories, Redhill, Surrey, England (Recked 9 January 1975) Abstract-The behaviour of a junction FET with a gate-source reverse bias exceeding the pinch-off voltage is discussed. It is seen that both the transfer and output characteristics have an exponential character, and this is attributed to the presence of a potential barrier between the source and drain, Simple expressions are given for both the conductance and transconductance in terms of parameters which, in the case of long gate devices, may be evaluated analytically, or, in the case of short gate devices, evaluated numerically using a relatively simple computer
model.
1.INTRODUCTION
The behaviour of a junction field-effect transistor (JFET) with the gate-drain reverse bias beyond pinch-off, but with the gate-source reverse bias at or below pinch-off, has been extensively studied [ 11. In this paper, however, we consider the case where the gate-source reverse bias exceeds the pinch-off voltage, which we define as the gate voltage at which, with zero source-drain voltage, the gate and substrate depletion regions just meet in the channel. The drain current under these conditions will be small. Certain of the properties of a JFET at low drain currents have been observed, and remarked upon in the literature [4,5], but no detailed physical or mathematical analysis has previously been attempted. The analogous problem of the behaviour of a MOSFET with a gate voltage short of the classical inversion point has been discussed in detail elsewhere [2,31. 2.PBySlCAL MODEL
Consider the idealised JFET shown schematically in Fig. 1. If initially there is no source-drain voltage, and the gate-source reverse bias equals the pinch-off voltage, the gate and substrate depletion regions will, by definition, just meet in the centre of the channel, and there will be a plane of conducting material at source potential connecting the source and drain. If the gate reverse bias is then increased, the potential in the channel will rise above the source potential, so that free carriers enter the substantially depleted channel by thermal excitation over a potential barrier of height Vs. When the drain voltage, V,, is applied, it induces a screening charge on the drain end of the gate so that the penetration of the drain field into
Source
rt’ n+ I
x
--\--
\
Late 1
1
Negative
t Potential
IDrain 1
P+ _-
“-type
___
P Y
the channel is limited and the potential within the channel remains largely unaffected. The features of the resultant potential distribution within the device are illustrated by Fig. 2. In a more typical asymmetric structure with a heavily doped gate and lightly doped substrate the potential distribution will be relatively complicated, but it will be shown later that the same qualitative physical features occur. Under these conditions, the channel potential will be closely coupled to the gate potential, while it may be shown that the effective depth of the channel will be of the order of the extrinsic Debye length, and will not vary much. Thus whereas in the normal mode of operation of an FET the drain current varies because variations in the gate potential modulate the depth of a conducting channel, in this “barrier mode” the effective channel depth does not vary, but the gate potential modulates the height of a potential barrier between the source and drain. This is analogous to the modulation of the emitter current in a bipolar transistor by the height of the potential barrier at the emitter-base junction, and indeed close formal
1 Substrate
Fig. 1, Schematic representation of the JFET
Fig. 2. Potential distribution throughout the JFET when V,, > VP. 1013
R. J. BREWER
1014
similarities exist between the behaviour of a “barrier mode” JFET and that of a bipolar transistor. 3. COMPUTER MODEL
To find the exact potential distribution within a JFET a numerical method must be used. The electrostatic potential at all points within a semiconductor is determined by the charge distribution according to Poisson’s equation. Also, due to the mobility of the charge carriers, the charge distribution is influenced by the potential distribution, so that an iterative method must be used to find a self-consistent solution. In the case we consider, if the channel is biassed with respect to the source sufficiently for the density of free charge in the channel to be small compared to the density of ionised impurities, the effect of the free carriers on the potential distribution within the depletion regions will be negligible. We may thus specify the charge distribution simply by specifying the shape of the depletion regions and the doping density. The computer program then solves Poisson’s equation to give the potential distribution, using a conventional two-dimensional finite difference method [6]. The solution is then examined for self-consistency, If the electrostatic field perpendicular to the depletion edges does not vanish at the edges, this implies that these boundaries have been incorrectly specified, since the current density in the barrier mode is always expected to be small. If there is no potential barrier, of at least several H/e, between the source and channel, this invalidates the assumption that the free charge in the channel has an effect on the potential distribution which is negligible compared to the fixed charge, and implies that a gate voltage inappropriate to the model has been specified. Adjustments are then made to the dimensions of the depletion regions and the electrode potentials until a self-consistent solution is obtained. The resultant potential distribution is thus approximate, due to the simplifications which have been used, but only needs a relatively simple, well-established computer program, and since it is very difficult to measure the geometry of a real device very accurately, any lack of accuracy in this computational method is believed to be unimportant compared to the likely errors in the input data. The computed potential down the length of the channel for one practical structure is shown in Fig. 3. The device has an annular gate of radius 60 km and length 10 pm. The channel is formed in a layer with a gaussian doping profile with a peak doping of 1.7 x lOI cm-’ in a lightly doped substrate of 10’”cm-‘. The gate junction is coincident with
the peak of the layer doping profile, with a separation of one micron between the gate and substrate junctions. The computation was performed with a gate reverse bias of 2.5 volts. Note the potential barrier between the source and channel, and the limited penetration of the drain field into the channel. 4. THEORY
Very long gate devices Consider a double gate device, as in Fig. 1 with the gate and substrate connected, where the gate length is very much greater than the channel depth. The potential distribution within the channel is then approximately one-dimensional, with a negligible longitudinal field, and the current will flow by diffusion. The barrier height is given by V, = V, - VP where V. is the gate-source reverse bias and V, is the pinch-off voltage. The diffusion current is
where N, and N2 are the free carrier concentrations at the source and drain ends of the channel, L is the channel length, and wcffis the effective channel depth. Now it may be shown that the number of free carriers in a parabolic potential trough is equal to the number in a square-section trough of width (27r)“*L,, where LD is the extrinsic Debye length. So if the channel is uniformly doped and the density of free charge is small compared to the density of fixed charge wefl= (2P)“*Ln = (2z$* where No is the doping concentration and VT= kT/e. Also N,=N,exp
(
--p
.r )
and N2=Noexp
(
-
Thus from the above jZD1 = N,$(2?r)““L,
exp (g)
exp
x[l-exp(-$$)I. Gate
length
Fig. 3. Computed potential profile along the line of potential minimum between the source and drain.
(- y) (1)
1015
The “barriermode” behaviour of a junction FET at low drain currents Note the close formal similarity between this expression and that for the collector current in a bipolar transistor. A similar expression has also been derived and experimeotally verified for the subthreshold region of operation of a MOSFET [2,3]. Short gate devices 10 these devices the fields in the channel will be two-dimensional, so that the current flow is by a mixture of drift and diffusion, and an exact analysis requires a numerical solution to the current transport equations. However, an approximate analytic expression for the device characteristics may be derived from two simple assumptions. The first is that the height of the potential barrier is linearly coupled to both the gate and the drain potentials. By Poisson’s equation, the change in potential at any given point due to a system of fixed charges and electrodes is linearly dependent upon a change in potential of any given electrode. Now when the gate or drain potential in a JFET is changed, this varies both the dimensions of the depletion regions and the position of the potential barrier; however, for small changes in the electrode potentials, so that these movements are small compared to the dimensions of the device, the assumption of linearity is good. Thus AVB = (YAV, +pAV,.
The second assumption is that the drain current varies exponentially with the height of the potential barrier, normalised to kT/e. Although the justification for this assumption is experimental, it appears physically plausible: if the shape of the potential profile in the channel remains substantially constant, the mix of drift and diffusion will not vary, and the current level will just be proportional to the free carrier population, which will vary exponentially with the potential difference between the source and channel. Then by differentiating the exponential function we obtain
AID -+A&, -= ID T
Mv
the barrier height. Secondly, the drain voltage also modulates the dimensions of the gate and substrate depletion regions, so that the coupling between the drain and the potential barrier will be somewhat non-linear. The transcooductaoce, however, should be very close indeed to exponential, since a range of drain currents of several orders of magnitude corresponds to a change in gate potential of only a few hundred millivolts. If the device is operated with the substrate potential fixed, the transcooductaoce will be lower, due to the coupling between the substrate and the potential barrier. This effect may be computed, and may be reduced by increasing the depth of the substrate depletion region. 5. EXPERIMENTAL. RESULTS The transfer and output characteristics at low drain currents of a long gate JFET were measured. The device had an annular gate of radius 60 pm and length 20 pm diffused into an n-type layer formed by a 150KeV phosphorus implant which was driven in for 16 hr at 1100°C:the dose was 8 x 10” ions/cm*. The substrate was p-type with a resistivity of 30&cm. The separation between the gate and layer metallurgical junctions was about 0.4pm, so that the channel length to depth was about 50. The gate and substrate were connected, to simulate a double-gate device. The variation of drain current with gate voltage at two temperatures is shown in Fig. 4. The variation is, as expected, exponential, with measured slopes of 39.1 and 60.4 millivolts per decade,
B
=- 1 -IrhVo~+/3AV,~] G Vr
D
(2)
for small changes in the electrode potentials. The parameters a and /3 may be evaluated numerically by computing the barrier height, using the method described in Section (3), for a closely spaced range of gate and drain voltages. It is found that (Y and /3 are determined primarily by the length to depth ratio of the channel, and with experience may be estimated simply from an inspection of the device geometry. The differeotial conductance and traoscooductance may then be predicted from’eqo (2). This method does not, however, yield an expression for the absolute current level. The variation of drain current with drain voltage will not be exactly exponential for two reasons. First, large variations in the drain voltage will vary the mix of drift and diffusion currents in the channel, so that the drain current will not have an exact exponential dependence on
: 1
01
02
,
03 Gate
04 voltage
05
I
06
07
(V)
Fig. 4. Transfer characteristics for a very long gate device. The solid lines are best fits through the experimental points.
R. J. BREWER
1016
compared to the theoretical values of 39.7 and 595 respectively from eqn (I), which shows that the slope is dependent solely upon the absolute temperature. (No attempt has been made to fit the observed and theoretical absolute current level, since eqn (1) shows it to vary exponentially with VP,which is not known independently to the required accuracy.) The variation of drain current with drain voltage is shown in Fig. 5: the fit between the experimental results and the theoretical curves derived from eqn.(l) is seen to be good. (The drain current has been normalised to give a best fit, since eqn (1) shows that the absolute current level is determined by various device parameters which cannot be measured very accurately in a real device, while the shape of the curve depends solely upon the absolute temperature.) At drain voltages much above about a hundred millivolts, the drain current is substantially constant, increasing only very slowly with increasing voltage. The transfer and output characteristics of a short gate JFET were measured. The device was similar to the long gate device already described, except that the gate length
was 5 pm and the channel deeper, so that the channel length-to-depth ratio was about 2.5. It was operated with the gate and substrate connected together. The device transfer curves at 2W’K and 300°K are shown in Fig. 6: a typical output curve is shown in Fig. 7. From these curves values for (r and ,9 may be derived using eqn (2), and compared with those predicted by the computer simulation (Table (1)). The channel conductance parameter /3 is very sensitive to the length-to-depth ratio of the channel, ranging from -10-l for a very short gate device to a virtually unmeasurable value, - lO4, for a very long gate device, such as that discussed previously, so that it is very difficult to obtain a theoretical prediction accurate to better than a factor two. The transconduc-
1
50 Drain
100 voltage
200
150 CmV)
Fig. 5. Output characteristics for a very long gate device. The lines are theoretical curves from eqn (I): the points are experimental. lo-
*_ .
.
\.
\ . \ .
\.
10 9.
T=300K
T: ZOOK
\
\
.
i
2 F :
\
,o-’ 10.
\ .
.
: u
k
\
b
\ .
.
L 50
‘\
Substrateleakage
51
52 Gate
53 5.4 voltage(V)
I
I
I
5
6
7
Drain
\
10'12
I
4 voltage
(VI
Fig. 7. Output characteristic for a short gate device. The solid line is a best fit through the experimental points. A value for r9 of 3.7 x lo-’ at 5 volts may be derived using eqn (2).
\ .
lo-111
I
3
l1. drolP
/ 5 5
5 6
Fig. 6. Transfer characteristics for a short gate device. The solid lines are best tits through the experimental points. Values for (I of 0.67 at 200°Kand 0.65 at 300°Kmay be derived using eqn (2).
The “barrier mode” behaviour of a junction FET at low drain currents
tance parameter, a, is much less variable, ranging from perhaps 0.5 for a very short gate device to very close to unity for a long gate device, and is thus rather more accurately predictable.
1017
operated in the barrier mode is low, the transconductance per unit drain current rises to a value close to that of a bipolar transistor, while very high input and output impedances are readily attainable. For some applications * this may be a useful combination of properties.
CONCLUSIONS
The transfer and output characteristics of. a junction FET at low drain currents are dominated by the presence of a potential barrier between the source and drain, with free carriers entering the channel by thermal excitation. The barrier height may be modulated by both the gate and drain potentials, although with the usual geometries the barrier is more closely coupled to the gate than to the drain, so that the drain current is more sensitive to the gate potential than to the drain voltage. Although the absolute transconductance of a JFET
Acknowledgements--I would like to acknowledge many useful discussions with J. R. A. Beale and J. M. Shannon. REFERENCES 1. C. K. Kim and E. S. Yang, IEEE Trans. ElectronDevices 17, 120 (1970). 2. M. B. Barron, Solid-St. Electron. 15, 293 (1972). 3. R. R: Troutman, IEEE I. Solid-St. Cir. 9, 55 (1974). 4. L. Evans and K. A. Pullen, Proc. IEEE 54,82 (1%6). 5. E. 0. Johnson, RCA Reo. 34,80 (1973). 6. C. Weber, Philips Tech. Rev. 24, 130 (1%3).