New structure of tunneling carbon nanotube FET with electrical junction in part of drain region and step impurity distribution pattern

Int. J. Electron. Commun. (AEÜ) 117 (2020) 153102

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New structure of tunneling carbon nanotube FET with electrical junction in part of drain region and step impurity distribution pattern Maryam Ghodrati a, Ali Mir a, Ali Naderi b,⇑ a b

Department of Electronics, Faculty of Engineering, Lorestan University, Khorram-Abad, Iran Department of Electrical Engineering, Energy Faculty, Kermanshah University of Technology, Kermanshah, Iran

a r t i c l e

i n f o

Article history: Received 21 October 2019 Accepted 28 January 2020

Keywords: Tunneling carbon nanotube FET Electric field Current ratio NEGF

a b s t r a c t In this paper, by using electrical junction in part of drain region which includes stepwise doping distribution, a new structure is proposed for tunneling carbon nanotube field-effect transistors (T-CNTFETs). The modified device consists of two parts in the drain region, a region without electrical junction and a region having an electrical junction where the n-type impurity is entered stepwise along the drain region. Electronic features of the modified device are simulated by the simultaneous solution of both Schrodinger and Poisson equations in self-consistent routine. Simulation consequences demonstrate that the proposed modifications reduce OFF state current and enhance the ON/OFF ratio in comparison with the conventional structures. Moreover, delay time, the product of delay and power, and subthreshold slope as important features of the T-CNTFET are enhanced. Also, to more assessment of the suggested structure, variations of cut-off frequency parameters, including transconductance and gate capacitance have been investigated. Ó 2020 Elsevier GmbH. All rights reserved.

1. Introduction Reducing the size of semiconductor components, such as the MOS transistors, has been a major focus of researchers in the semiconductor industry in recent years [1–5]. As the size of these components decreases, many problems arise due to physical limitations; the mechanic quantum effects appears in the physical computations which affects the efficiency. In addition, due to the physical limitations of silicon device fabrication, it is not possible to further integrate MOSFETs. Therefore, proper replacement for traditional MOSFETs is necessary [6–13]. Carbon nanotube is one of the most important nano-scale structures which is recently considered by researchers and has the potential to be one of the alternatives for the current MOSFET technology in the future [14–19]. Carbon nanotubes could be conductive or semiconductor, depending on how their graphite plates are assembled. Since carbon nanotubes are able to transmit electricity through electron ballistic transmission (without dispersion of carriers collision), this current is about 100 times higher than the current passing through copper wire, so the carbon nanotubes are proper options for many microelectronic applications [20–28]. Transistor components made of single-walled carbon nanotubes have a performance similar to that ⇑ Corresponding author. E-mail address: [email protected] (A. Naderi). https://doi.org/10.1016/j.aeue.2020.153102 1434-8411/Ó 2020 Elsevier GmbH. All rights reserved.

of silicon transistors except that carbon nanotubes are used instead of silicon in the channel. So far, different types of CNTFETs have been introduced. One of them is tunneling field effect transistor (T-CNTFET) [29–34]. The T-CNTFET action is like a diode (p-i-n) such that its potential in intrinsic region is controlled by gate bias. The T-CNTEFTs have a proper sub-threshold slope, but a low ON state current is one of the major problems of this type of transistors [35–39]. In this regard, various methods have been developed to improve the transistor electrical characteristics. These methods include changing the impurities concentration in the drain area [19], injecting impurities linearly and lightly in the source and drain areas [2], using gate insulators with asymmetric thicknesses [5], and using electrically induced in the drain and source areas [1]. However, these problems have not been fully resolved and new structures are needed to improve their performance. Here, a new T-CNTFET is presented, in which an electrical junction is used in a part of the drain area that is doped stepwise. We involved the non-equilibrium Green’s function (NEGF) to study and simulate a T-CNTFET. In simulations, the Schrodinger equation and the Poisson equation are considered with open boundary conditions in nanotube atomic basis. The simulation outcomes indicate that the proposed structure results in a less OFF state current compared to the conventional structure. In addition, the new structure is characterized by a better current ratio (ON/OFF) beside a higher subthreshold slope (i.e. small subthreshold swing). In the following

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we evaluate and compare this structure. In Section 2, the simulation method and model used to study the behavior of T-CNTFETs is discussed. The third section introduces the proposed device structure. Section 4 describes the transistor electrical properties using simulation results, and comparisons are made. Lastly, conclusion is mentioned in Section 5. 2. Simulation method Since the T-CNTFET size is small, computation of its behavior requires proper quantum computation and numerical methods. Simulating the device and obtaining its current-voltage curve is performed according to the data achieved from the device structure [21,27,28,31]. In this paper, by the NEGF method, the T-CNTFET is simulated which provides an accurate approximation

for simulating nano-scale devices in non-equilibrium state [21,22,29]. The iterative technique is used in which the prementioned equations are solved in the iterative process. The Schrodinger equation and NEGF technique are applied to obtain the density of the electric charge. Then, using the electric charge calculated, the electrostatic potential is obtained by Poisson equation, and the current is achieved after the convergence and error reduction. In the NEGF method, first the Green’s function is reachable by [2,21,22,29,31]:

h X X i1 GðEÞ ¼ ðE þ igþ ÞI  H  S D

ð1Þ

in this relation, RS and RD are the source and drain self-coupling energy, H depicts the Hamiltonian of channel, E denotes the energy, notation g+ shows extremely trivial positive value, and I is the unit

Fig. 1. Cross- sectional view of (a) the conventional T-CNTFET structure and (b) the proposed structure (c) doping profile of the conventional T-CNTFET (solid line) and the proposed structure (dash-line).

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Fig. 2. ID-VDS diagram output feature of proposed and conventional structures at different gate-source voltages.

Fig. 4. Energy band diagram versus position along the device in VDS = 0.4 V and VGS = 0.4 V for the structures (a) T-CNTFET and (b) Proposed. Fig. 3. ID - VGS curve for both structures at different drain-source voltages.

matrix. Given the Green’s function, one can obtain physical parameters such as charge density and current using the NEGF formulation. The charge density within the device is given as follows [19,21,22,28,29]:

Z Q e ¼ ðeÞ

1

    DS f E  EfS þ DD f E  EfD dE

ð2Þ

fer coefficient is T(E). According to [28], while the drain-source electrode is ground, the fermi level is zero, and using an applied voltage, it will cause a difference between them. The transfer coefficient is calculated by relation (3) [15,19,21,28]:

  T ðEÞ ¼ tr CS GCD Gþ

In relation (3), Green’s function is G, and CS (D) represents the extension of the energy determined by (4) [15,27,29,31]:

Ei

This repetitive process will continue until convergence is achieved. The stop criterion for self-consistent process is defined such that the maximum variations in two successive potentials is less than 1 meV. In the above method, after convergence and dropping the error, I is determined by the following equation [19,21,22,28,29]:

I¼

2q h

Z dET ðEÞ½ f ðE  EFS Þ  f ðE  EFD Þ

ð3Þ

in above equations, EFS,D are the Fermi levels, D is local density of states, q is the electron charge, Planck’s constant is h, and the trans-

ð4Þ

CSðDÞ ¼ i

X SðDÞ



! þ X

ð5Þ

SðDÞ

It should be noted that for discretization and numerical modeling of the two-dimensional transistor structure, the mesh sizes are considered 0.25 nm in the Z axis and 0.1 nm in the R axis. In both directions, the mesh is selected uniformly. 3. Device structure The two-dimensional views of the suggested device and the basic structure are shown in Fig. 1. In these structures, a zigzag-

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Fig. 5. Bandstructure along the nanotube for both structures. Fig. 7. Subthreshold swing diagram versus VGS for both structures in VDS = 0.4 V.

Fig. 6. ON/OFF diagram in terms of ON current for proposed and conventional structures in VDS = 0.4 V.

type carbon nanotube (13, 0) with a dielectric of hafnium dioxide with dielectric constant of 16, and 2 nm thickness is considered. The length of gate is 20 nm and the drain (source) length is 30 nm. The impurity in the source side is P-type at fixed value of 1 nm1. The n-type impurity on the drain side is stepwise and part of the drain area near the channel has an electrical junction whose length is considered to be 10 nm. Workfunction of gate metal is equal to intrinsic CNT workfunction while workfunction of electrical junction is 0.3 eV lower than the workfunction of the gate electrode. It should be noted that the amount of step doping from the drain side to the channel area is 1 nm1, 0.8 nm1, 0.6 nm1, 0.4 nm1, 0.2 nm1 and zero, respectively. The length of each step is 5 nm. The device operates at room temperature (300 ◦ K). 4. Simulation results and discussion Here, we investigate the electrical features of T-CNTFET by electrical junction in part of the drain region with a step impurity distribution pattern in comparison with the basic structure. The

Fig. 8. The delay and PDP in terms of saturation current for (a) conventional and (b) proposed structure in VDS = 0.4 V.

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Fig. 9. Cut-off frequency against VGS for proposed and conventional structures in VDS = 0.5 V.

device current diagram based on gate-source biases of 0.5 and 0.6 V for the proposed device and the conventional structure are shown in Fig. 2. Drain-source current diagram versus drainsource voltage is plotted for fixed channel length of 20 nm. As shown in Fig. 2, it is observed that for the given gate-source voltages the saturation current of suggested structure is higher than its basic counterpart. Fig. 3 shows the drain current for the simulated devices at two different voltages of VDS = 0.3 V and VDS = 0.7 V. According to the simulation results, in the suggested structure the OFF current is meaningfully reduced compared with conventional counterpart. The results of simulation show that the Off current and ambipolar behavior in the proposed structure are significantly better than those of the conventional structure. In the proposed structure due to electrical junction in part of drain area, the tunneling barrier is wider in the channel-drain connection. Moreover, in the new structure the position of the Dirac point shifts to a negative VGS and so improves ambipolar behavior. Thus, BTBT probability is reduced and accordingly the leakage current suppressed. As a result, the OFF current in the proposed structure is about six times smaller at VDS = 0.3 V than in the conventional structure. Fig. 4a, b illustrate conduction and valance bands along the nanotube for the studied structures in VDS = 0.4 V and VGS = 0.4 V, to study the tunneling barrier at the channel to drain region interface. As can be seen in Fig. 4, the T-CNTFET by electrical junction part of the drain region with a step impurity distribution pattern improves the potential profile and electric field next to the drain region. This decreases the potential profile variations, and is followed by widening of the barrier. In addition, flattening reduces the possibility of the band to band tunneling (BTBT), which in turn reduces leakage current and modifies the ambipolar behavior. This justification is also evident in Fig. 5. Fig. 6 shows the ON/OFF diagram in terms of saturation current for under study structures in logarithmic scale. It can be observed that maximum current ratio in the conventional structure is about 106 while this value for the suggested structure is more than 108. The current ratio of the modified structure has considerably increased compared with the conventional device. The proposed structure has desired current ratio features due to reduced probability of BTBT. Subthreshold swing (SS) is another important parameter that indicates the power consumption at subthreshold state for

Fig. 10. Transconductance and gate capacitance diagrams versus VGS for (a) basic and (b) modified structure in VDS = 0.5 V.

short-channel devices. The SS theoretical minimum for MOSCNTFETs is 60 mV/dec at 300°K. T-CNTFETs result in a SS smaller than the theoretical limit; thus, these devices are attractive for applications with low power dissipation. The SS is defined by the following formula [15–19]:

SS ¼

 1 dðlog IDS Þ ðmV=decÞ dðV GS Þ

ð6Þ

Fig. 7 shows SS–VGS diagram for both structures in VDS = 0.4 V and the channel length of 20 nm. It is observed that our suggested structure has a lower SS than the basic structure. The SS for both structures in VDS = 0.4 V, VGS = 0.225 V has the values of 33.35 mV/decade and 41.32 mV/decade, respectively. The reason for the reduced subthreshold swing in the proposed structure is its wider tunneling barrier in the drain-channel connection which is resulted by electrical junction in part of drain and stepwise doping. To study the ON-OFF switching behavior of the proposed and conventional structures, the delay (s) and product of power and delay (PDP) are considered. These parameters are calculated as follows [15–21]:

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Fig. 12. ON/OFF diagram in terms of ON current for different lengths of electrical junction in the drain area in VEJ = 0.4 V and VDS = 0.4 V.

For further analysis, the important parameters of transistors such as transconductance (gm), gate capacitance (Cg) and intrinsic cut-off frequency (fT) are evaluated. gm and Cg are defined by Eqs. (9) and (10) [16–19]:

gm ¼

 @Ids  @V gs V ds

ð9Þ

Cg ¼

 @Q g  @V gs V ds

ð10Þ

It is necessary to explain that in Eq. (10) the parameter Qg is the total charge in the gate region. The fT is obtained based on the calculated values of gm and Cg using below equation [16–21]:

Figure Caption Missing

fT ¼

Table 1 Assessment of current ratio, delay time and PDP for a modified device at altered lengths of electrical junction in the drain area. The length of the electrical junction in the drain area

ION =IOFF

5 nm 10 nm 15 nm 20 nm

2.12 7.99 7.01 9.70

   

103 104 106 108

sð fsÞ

PDP ðeV Þ

15,700 18,000 22,600 28,500

1.06 1.25 1.52 1.92

s ¼ ðQ ON  Q OFF Þ=ION

ð7Þ

PDP ¼ ðQ ON  Q OFF ÞV DD

ð8Þ

Fig. 8 illustrates PDP and the delay time diagrams in terms of ON current at VDS = 0.4 V for under study devices. It can be observed that the modified structure has better switching characteristics than the conventional structure. As regards, s and PDP in suggested structure are lower than the conventional structure, it is appropriate for high speed applications and low power consumption.

gm 2pC g

ð11Þ

Cut-off frequency diagram in terms of gate-source voltage is illustrated in Fig. 9 for both structures. According to Fig. 9, it can be observed that the suggested structure has better cut-off frequency than the basic structure. The changes in the cut-off frequency slope are affected by changes in transconductance and gate capacitance versus gate-source voltage. Transconductance and gate capacitance diagrams versus VGS for under study structures with VDS = 0.5 V are presented in Fig. 10(a) and (b). It is perceptible that both structures result in nearly the equal transconductance while the gate capacitance values in the suggested structure are less than the basic structure. Increasing in cut-off frequency value is evidence that the modified structure can be a proper option for high frequency applications in addition to previous improvements. Since the high electric field on the drain-channel affects the device performance and is considered as an undesirable factor, the lower the electric field in the device, the more secure the device. In Fig. 11 the electric field amplitudes are plotted as a function of position along the nanotube for the proposed and basic structure in the various biases. Investigation of the electric field shows that in the proposed structure with electrical junction in a part of the drain region with a step impurity distribution pattern,

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5. Conclusion A new structure of T-CNTFETs, which uses electrical junction in part of drain region with step impurity distribution pattern is introduced. To investigate and simulate the proposed structure, the simultaneous solution of electrostatic and quantum equations by the NEGF formalism are employed. The simulation results demonstrate that the OFF current is meaningfully reduced in comparison with the basic structure. Moreover, the new structure has greater ON/OFF ratio and smaller subthreshold swing. Electrical junction in part of the drain region with stepwise impurity distribution pattern widens the tunneling barrier at the channel region to drain region junction, which improves leakage current parameters, delay time, power delay product and cut-off frequency. Studies show that the suggested structure is a proper nominee for small power dissipation, high speed and high frequency applications.

Appendix A. Supplementary material Supplementary data to this article can be found online at https://doi.org/10.1016/j.aeue.2020.153102.

References

Fig. 13. (a) s and (b) PDP in terms of ON current for different lengths of electrical junction in the drain area in VEJ = 0.4 V and VDS = 0.4 V.

the maximum electric field is reduced in different biases. The hot carrier effect, which is a detrimental effect, is reduced by reduction in the electric field. It is worth mentioning that the electric field is a derivation of potential distribution. The electric field has been obtained from the potential difference between two successive points divided by the distance between those points. To further study and obtain better insight about the proposed device performance, by deviation in the length of the electrical junction of the drain region for 5, 10, 15, and 20 nm length, current ratio, delay time, and PDP are evaluated. The results of the simulation are mentioned in the Table 1. According to Fig. 12, it is seen that in proposed structure, by raise in electrical junction length, ON/OFF ratio is increased significantly. On the other hand, the results obtained in Fig. 13(a) and (b) show that delay and PDP also increased by the growth of electrical junction length of the drain area. Accordingly, it is necessary to make a compromise between the parameters of the device.

[1] Arefinia Z, Orouji AA. Quantum simulation study of a new carbon nanotube field-effect transistor with electrically induced source/drain extension. IEEE Trans Device Mater Reliab 2009;9(9):237–43. [2] Koswatta SO, Nikonov DE, Lundstrom MS. Computational study of carbon nanotube p-i-n tunnel FETs. IEEE IEDM Tech Dig 2005; 518–21. [3] Chin S-K, Seah D, Lam K-T, Samudra GS, Liang G. Device physics and characteristics of graphene nanoribbon tunneling FETs. IEEE Trans Electron Devices 2010;57:3144–52. [4] Moghadam N, Aziziyan M, Moravvej-Farshi MK. Design and simulation of MOSCNT with band engineered source and drain regions. Microelectron Reliab 2013;53:533–9. [5] Gholipour M, Masoumi N, Chen Y, Chen D, Pourfath M. Asymmetric gate Schottky-Barrier graphene nanoribbon FETs for low-power design. IEEE Trans Electron Devices 2014;61(12):4000–6. [6] Naderi A. Double gate graphene nanoribbon field effect transistor with electrically induced junctions for source and drain regions. J Comput Electron 2016;15(2):347–57. [7] Singh A, Khosla M, Raj B. Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM. AEU-Int J Electron Commun 2017;80:67–72. [8] Hsu F, Grinolds H. Structure-enhanced MOSFET degradation due to hot electron injection. IEEE Electron Device Lett 1984;5(3):71–4. [9] Naderi A, Keshavarzi P. Electrically-activated source extension graphenenanoribbon field effect transistor: novel attributes and design considerations for suppressing short channel effect. Superlattices Microstruct 2014;72:305–18. [10] Peng L, Zhang Z, Wang S. Carbon nanotube electronics: recent advances. Mater Today 2014:433–42. [11] Pulfrey D, Chen L. Comparison of p-i-n and n-i-n carbon nanotube FETs regarding high-frequency performance. Solid-State Electron 2009;53:935–9. [12] Sahoo R, Mishra RR. Carbon nanotube field effect transistor: basic characterization and effect of high dielectric material. Int J Recent Trends Eng 2009;2(7). [13] Wang W, Na L, Yuzhou R, Hao L, Lifen Z, Jin L, et al. A computational study of the effects of linear doping profile on the high-frequency and switching performances of hetero-material-gate CNTFETs. J Semicond 2013;34 (12):124002. [14] Wang W, Yang X, Li N, Xiao G, Jiang S, Xia C, et al. Transport study of gate and channel engineering on the surrounding-gate CNTFETs based on NEGF quantum theory. J Comput Electron 2014;13(1):192–7. [15] Yousefi R, Saghafi K, Moravvej-Farshi MK. Numerical study of lightly doped drain and source carbon nanotube field effect transistors. IEEE Trans Electron Devices 2010;57:765–71. [16] Naderi A, Ghodrati M. An efficient structure for T-CNTFETs with intrinsic-ndoped impurity distribution pattern in drain region. Turkish J Electric Eng Comput Sci 2018;26(5):2335–46. [17] Novoselov KS, Geim AK, Morozov SV, Jiang D, Zhang Y, Dubonos SV, et al. Electric field effect in atomically thin carbon films. Science 2004;306:666–9. [18] Jang SK, Jeon J, Jeon SM, Song YJ, Lee S. Effects of dielectric material properties on graphene transistor performance. Solid-State Electron 2015;109:8–11. [19] Naderi A, Ghodrati M. Improving band-to-band tunneling in a tunneling carbon nanotube field effect transistor by multi-level development of impurities in the drain region. Eur Phys J Plus 2017;132(12):510.

8

M. Ghodrati et al. / Int. J. Electron. Commun. (AEÜ) 117 (2020) 153102

[20] KhademHosseini V, Dideban D, Ahmadi MT, Ismail R. An analytical approach to model capacitance and resistance of capped carbon nanotube single electron transistor. AEU-Int J Electron Commun 2018;90:97–102. [21] Datta S. Nanoscale device modeling: the Green’s function method. Superlattices Microstruct 2000;28:253–78. [22] Naderi A, Ghodrati M. Cut off frequency variation by ambient heating in tunneling p-i-n CNTFETs. ECS J Solid State Sci Technol 2018;7(2): M6–M10. [23] Koswatta S, Lundstrom Mark S, Nikonov D. Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling. Nano Lett 2007;7(5):1160–4. [24] Sarvari H, Ghayour R, Dastjerdy E. Frequency analysis of graphene nanoribbon FET by non-equilibrium Green’s function in mode space. Phys. E Low Dimension. Syst. Nanostruct. 2011;43(8):1509–13. [25] Liu L, Mohata D, Datta S. Scaling length theory of double-gate interband tunnel field- effect transistors. IEEE Trans. Electron Device 2012;59:902–8. [26] Ghodrati M, Farmani A, Mir A. Nanoscale sensor-based tunneling carbon nanotube transistor for toxic gases detection: a first-principle study. IEEE Sens J 2019. https://doi.org/10.1109/JSEN.2019.2916850. [27] Datta S. Electronic transport in mesoscopic systems. Cambridge: Cambridge University Press; 1995. [28] Guo J. Carbon nanotube electronics: modeling, physics, and applications. Purdue University, August, 2004. [29] Guo J, Javey A, Dai H, Lundstrom M. Performance analysis and design optimization of near ballistic carbon nanotube field-effect transistor. In: Presented at the IEEE Int Meet. Electron Devices, IEDM; 2004. [30] Jooq MKQ, Mir A, Mirzakuchaki S, Farmani A. Semianalytical modeling of high performance nano-scale complementary logic gates utilizing ballistic carbon

[31]

[32] [33]

[34]

[35]

[36]

[37]

[38]

[39]

nanotube transistors. Phys. E Low Dimension. Syst. Nanostruct. 2018;104:286–96. Koswatta S, Lundstrom Mark S. Performance comparison between p-i-n tunneling transistors and conventional MOSFETs. IEEE Trans. Electron Device 2009;56:456–65. Hashempour H, Lombardi F. Device model for ballistic CNFETs using the first conducting band. IEEE Des Test Comput 2008;25(2):178–86. Kazmierski TJ, Zhou D, Al-Hashimi B. Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density. In: EDAA, Munich, Germany; 2008. pp 146–51. Bayani AH, Dideban D, Akbarzadeh M, Moezi N. Benchmarking performance of a gate-all-around germanium nanotube field effect transistor (GAA-GeNTFET) against GAA-CNTFET. ECS J Solid State Sci Technol 2017;6(4):M24–8. Salimian F, Dideban D. Comparative study of nanoribbon field effect transistors based on silicene and graphene. Mataer Sci Semicond Process 2019;93:92–8. Khademhosseini V, Dideban D, Ahmadi M, Ismail R, Heidari H. Single electron transistor scheme based on multiple quantum dot Islands: carbon nanotube and fullerene. ECS J Solid State Sci Technol 2018;7(10):145–52. Saeidi Mobarakeh M, Moezi N, Vali M, Dideban D. A novel tunneling field effect transistor (GFET) using bandgap engineering. Superlattices Microstruct 2016;100:1221–9. Akbari Eshkalak M, Anvarifard MK. A novel graphene nanoribbon FET with an extra peak electric field (EFP-GNRFET) for enhancing the electrical performances. Phys Lett A 2017;381(16):1379–85. Akbari Eshkalak M, Anvarifard MK. A guideline for achieving the best electrical performance with strategy of halo in graphene nanoribbon field effect transistor. ECS J Solid State Sci Technol 2016;5(12):M141–7.