Noise behavior of ferro electric tunnel FET

Journal Pre-proof Noise behavior of ferro electric tunnel FET B. Das, B. Bhowmick PII:

S0026-2692(18)30830-9

DOI:

https://doi.org/10.1016/j.mejo.2019.104677

Reference:

MEJ 104677

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Microelectronics Journal

Received Date: 27 October 2018 Revised Date:

26 November 2019

Accepted Date: 4 December 2019

Please cite this article as: B. Das, B. Bhowmick, Noise behavior of ferro electric tunnel FET, Microelectronics Journal (2020), doi: https://doi.org/10.1016/j.mejo.2019.104677. This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain. © 2019 Published by Elsevier Ltd.

Noise behavior of Ferro electric Tunnel FET B. Dasa , and B.Bhowmickb a ,b

Department of ECE, NIT Silchar, Assam 788010, India [email protected], [email protected]

Abstract— In this paper the noise behavior of ferroelectric TFET is explored for the first time. The effect of ferro-thickness, gate length, buffer type, and buffer thickness on current noise power spectral Density (SID) and voltage noise power spectral Density (SVG) along with electrical parameters such as memory window, subthreshold swing along with have been investigated. The normalized SID follows 1/SS2 trend, thus signifies the dominancy of BTBT over TAT in Ferro-TFET. Input referred noise PSD, SVG remains constant for whole range of gate voltage deviating from the nature for conventional MOSFET.Power spectral densities experience a sharp rise for frequency above 0.1GHz due to dominancy of diffusion over other source of noise. Index Terms—FTFET, negative capacitance, noise, memory window

1.

Introduction

Memory devices inspires us to explore the prospects of emerging devices. Subthreshold swing (SS) being one of prime factor in determining the efficiency of memory devices, a number of devices have been proposed. Among the many mentioned by ITRS’2015[1] Ferroelectric FET has shown its immense prospects in reduction of SS [2]. SiO2 or high-k dielectric results into positive COX in conventional FET whereas ferroelectric oxides are responsible for negative gate oxide capacitances. This causes an internal voltage amplification resulting into lowering of SS [2-4]. SS of ferroelectric FET depends on charge transport mechanism and total capacitance from silicon body to gate oxide capacitances. Therefore, for efficient reduction of SS, we can use ferroelectric oxide in TFET, where band to band tunneling mechanism of TFET helps us to reach below the Bolzmann limit of 60mV/dec [4-11]. The first ferroelectric Tunnel FET (FTFET) was proposed by Lattazio et al.[12] and observed near threshold, SS of about 880mV/dec using the principles of P(VDE-TrFE). So far, various works have been carried out on studying the effect of scaling [13], different structural improvement on electrical parameters such as SS, Memory Window, ION/IOFF etc [14-21], but analysis of noise has remain unexplored. However, to consider the reliability of semiconductor devices, the effect of noise on the performance of nanoscale geo-metries is important .The behavior of FTFET in presence of noise has not been explored as compared to the analysis of other electrical parameters.This work presents a combined effect of different type of noise such as flicker, diffusion and generationrecombination noise to study the effect of various scaling parameters like ferroelectric oxide thickness, channel length, buffer thickness and buffer type have also investigated. This paper is organized as follows: In section II device structure and simulation setup are discussed. Section III presents the effect of Ferro-thickness, gate length, buffer type, buffer thickness on electrical parameters including noise power spectral densities (PSD). Section IV concludes the paper.

Fig. 1. Structure of the simulated device

2.

DEVICE STRUCTURE AND SIMULATION SETUP

A SOI device structure in Fig.1 is simulated having source(p+) and drain (n) doping concentration of 1×1020 and 5×1018 cm-3

Fig. 2. ID-VG graph for experimental and simulated Fe-TFET (Gate Gate length=350nm,Work function=5eV, Ferrothickness=46nm and drain voltage =0.5V).[19]

TABLE I EXTRACTED PARAMETER VALUE Memory SS ION/IOFF .Type of Variation Window (mV/Dec) (V) 6nm 26.5 1.2 5.426E+6 Ferrothickness 10nm 25.3 1.73 4.531E+6 14nm 26.3 1.86 2.479E+6 1nm 25.3 1.73 4.531E+6 Buffer 3nm 13.6 1.38 2.423E+6 Thickness 5nm 34.1 1.12 1.476E+6 SiO2 56.2 0.51 1.936E+6 Buffer Type Si3N4 20.2 1.42 2.799E+6 HfO2 25.3 1.73 4.531E+6 30nm 35.9 1.72 3.623E+7 Gate Length 40nm 25.3 1.73 4.531E+6 50nm 50.2 0.73 5.714E+4

VTh(V) 1.32 1.68 2.2 1.68 1.99 3.16 2.91 2.18 1.68 1.69 1.68 1.67

respectively, channel thickness of 20nm. The idea of the work is to implement negative capacitance (using ferroelectric as oxide) to improve subthreshold swing and enabling TFET to be implemented as memory device. Along with the oxide, a buffer layer is used between ferroelectric oxide and silicon to reduce lattice mismatch. This structure can have stable state in total energy with negative curvature in Landau energy of ferroelectric as gate bias is applied. Relation between polarization charge density and electric field in ferroelectric oxide are analytically expressed and calculated by Landau equation [22]. The FTFET simulation has been performed on 2D simulator of Sentaurus TCAD[23]. Fermi Dirac Statistics and Effect of bandgap narrowing is applied to consider heavy doping at source and drain. Doping Dependent Mobility Model is used to include the effect of doping concentration and ENormal mobility model to consider effect of polarization in ferroelectric oxides.To consider effect of interband tunneling in TFETs efficiently, Non Local Band-to-Band Tunneling Model along with Shockley-Read-Hall (SRH) Recombination Model is enabled and it uses Wetzel-Kramer-Brillouin (WKB) approximation 3.

RESULT AND DISCUSSION

Here, the conventional gate oxide has been replaced with ferroelectric oxide Si:HfO2 and it is simulated to study the effect of various parameter variation with respect to current and voltage spectral density. For TFETs, the 1/ f noise behavior due to number fluctuations is related to the charges trapping and de-trapping into the gate dielectric above the source junction. By analogy to a MOSFET, the current noise power spectral density (PSD) can be expressed by the following equations [19],

(a)

(d)

(b)

(e) Fig. 3. ID-VG, SID, SVG and transconductance plot with ferrothickess

(c)

(f)

2 SID = IDS

β2 SVG = gm2SVGFB ( β = kT ) (0.1) SS2

TABLE 2 COMPARISONS OF WORKS

Work

q 2 .k.T.N ot (0.2) 2 Cox .W.Leff .α.f γ 2  −B  = I tunneling = A.F .exp   (0.3)  F 

SVGFB = IDS

This Paper [24] [25]

SID (A2/Hz) 1MHz 10GHz ~10-27 ~10-26

SVG (V2/Hz) 1MHz 10GHz ~10-7 ~10-15

~10-14 ~10-12

~10-6 ~10-5

~10-20 ~10-15

~10-14 ~10-11

Where, SID is current noise power spectral density, SVG is voltage noise power spectral density, Not is oxide trap density, γ is ranging from 0.8 to 1.3, SVGFB is power spectral density of flat-band voltage noise,Cox is the oxide capacitance per unit of area, α is a tunneling parameter (≈10-8 cm), W is the transistor width, Leff is the effective channel length, f is the frequency,A(1x1020 (nMOS) and 9.9x1018 (pMOS)) and B (5x104 (nMOS) and 2.4x103 (pMOS)) are empirical parameters to adjust the BTBT generation rate and F is the electric field. The key to negative capacitance effect is that the negative differential capacitance of the Ferroelectric (CFE<0) compensates

(

−1 −1 the positive capacitances (CMOS>0) in the device such that the resulting gate capacitance, C G = C FE + C MOS

)

−1

provides sub

60mV/dec operation [17]. Fig. 2 shows calibration result with experimental parameter [19] and found out to be in accordance with the simulation result. Fig. 3 shows variation of various parameters with respect to ferroelectric film thickness. Memory window depends on coercive field and film thickness, where in observation coercive filed reduces but dominance of film thickness results in increase memory window (shown in Fig.3(a) which is significant criteria for memory devices as it influences data retention time and data detection [17]). The subthreshold swing (SS) value of the device with respect to various parameter variation are shown in table 1, results shows that at 10 nm ferroelectric thickness, 1 nm buffer thickness, HFO2 as buffer type and 40nm gate length gives SS 25.3 mV/dec, 1.73 V memory window, on-off current ratio of 2.4×106 which can be considered as most acceptable value with comparison to other variation. Fig.3 (b) shows SID variation with ferroelectric thickness and it follows (1.1) but as shown in table 2, value is in the range of 10-27 for 1MHz and 10-26 for 10GHz much lower than conventional TFETs [24-25], which establishes the fact that negative capacitance effect reduces noise due to reduction of trapping and de-trapping of charges. But, it is more for 14nm Ferro-thickness, as effective oxide thickness (EOT) increases similar to effect of it on

(a)

(d)

(b)

(e) Fig. 4. ID-VG, SID, SVG and transconductance plot with gate length.

(c)

(f)

(a)

(d)

(b)

(c)

(e) Fig. 5. ID-VG, SID, SVG and transconductance plot with buffer type

(f)

2

MOSFET, where spectral density is proportional to 1/ CEOT . From Fig.3 (e) and Fig.3 (b), it can be observed that trends are coherent to each other for full current range and this infers to less dominance of 1/f noise. Fig. 3(c) shows normalized noise variation with SS and it can be observed that it follows 1/SS2 for the whole SS range which results from enhanced band-to-band tunneling (BTBT) unlike conventional TFETs due to improved electrostatic coupling. SVG in Fig. 3 (d) shows constant value for whole range of representing current is dominantly due to band to band tunneling. Fig. 3 (f) shows that BTB generation rate increases with reduced Ferro- thickness.

(a)

(d)

(b)

(e) Fig. 6. ID-VG, SID, SVG and transconducance plot with buffer thickness.

(c)

(f)

Fig 4. (a) shows with variation in gate length, on state current differs very less but large variation is observed in off state current where off state current reduces with increase of gate length. Fig.4 (b) shows drain current spectral density has been more in 50nm than 30nm due to increase of ambipolarity and a gradual rise has been observed for higher drain current. Fig. 4 (c) shows normalized noise follows 1/SS2 and Fig. 4(d) and 4(e) shows dominance of BTBT over Trap Assisted Tunneling (TAT) as tunneling mechanism keeps SVG constant over the range of gate voltage and normalized gm reduces for whole current range but drops drastically for high current values indicates dominancy of BTBT in current. Fig. 5 shows variation for different types of buffer which reduces large number of defects and lattice mismatch between ferroelectrics and silicon. But, it is detrimental to the memory window requirement due to voltage drop across it resulting in reduction of ferroelectric voltage. To maintain working of device in saturation polarization loop, high ferroelectric voltage is needed which can reduce voltage drop across it [17], thereby maintaining respectable memory window as observed in Fig. 5 (a). In Fig. 5 (b), normalized SID is more for HfO2 buffer because equivalent oxide thickness (EOT) for HfO2 is more and more EOT provide enhanced power spectral density. SVG and normalized gm shown in Fig. 5 (d) and 5 (e), resulting into the fact that BTBT is dominant tunneling mechanism in negative capacitance devices which can be established more with the fact that normalized spectral density varies proportional to 1/SS2 shown in fig. 5 (c), Though lower dielectric does not follow the trend at higher SS due to high voltage drop across buffer layer. In Fig. 6 (a), effects of buffer thickness are shown and it can be observed that as buffer thickness is increased, memory window reduces [17]. Normalized SID in Fig. 6 (b) is more for reduced buffer thickness at lower values of drain current. Normalized spectral density in Fig.6 (c) does not follow 1/SS2 trend due to the increase of voltage drop across it, which reduces ferroelectric voltage, thereby resulting in formation of minor polarization loop. As BTBT reduces with increase of buffer thickness, it leads to increase in SVG though it still can be assumed to be flat due to dominance of BTBT over TAT as tunneling mechanism which can be established from Fig. 6 (d), 6(e) and 6(f).

(a)

(b) Fig. 7. SID and SVG with frequency.

Fig. 7(a) and 7(b) shows the SID and SVG versus frequency plot at VDS= 0.5 V, VGS=2V and ID=0.1µA/µm. In Fig. 7(b), the contribution of different noise components are shown. Correlating Fig. 7(a) and fig 7(b) it can be observed that at low frequency for the range of 10 Hz to 1 KHz both generation-recombination and flicker noise are present. Above 1 KHz, flicker noise dominates others and effect persists till 0.1 GHz after which diffusion noise have larger dominancy over other noise sources which is represented through rise in current and voltage spectral density above 0.1 GHz, this happens largely due to charge trapping and de-trapping at the oxide-semiconductor interface. 4. CONCLUSION In this paper the analysis of electrical noise behavior is performed in Ferroelectric TFET for the first time. Improved noise

performance has been achieved. The negative capacitance effect in FTFET reduces noise due to reduction of trapping and detrapping of charges. The drain current spectral density is more with the increase in gate length due to increased ambipolarity. High-k buffers provide better memory window but more normalized SID and proportional to1/SS2. Moreover, Ferro-TFET operating in high frequency region will be affected by diffusion noise.

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Author Statement Basab Das: Conceptualization, Methodology, Software, Visualization, Investigation, WritingOriginal draft preparation. Brinda Bhowmick: Resources, Supervision, Validation, Writing- Reviewing and Editing

Conflict of Interest:

The authors declare that they have no known competing financial interests or personal relationships which have, or could be perceived to have, influenced the work reported in this article.