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Electrical noise in Circular Gate Tunnel FET in presence of interface traps
Superlattices and Microstructures 86 (2015) 342–354
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Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Electrical noise in Circular Gate Tunnel FET in presence of interface traps Rupam Goswami ⇑, Brinda Bhowmick, Srimanta Baishya Department of Electronics & Communication Engineering, National Institute of Technology Silchar, Assam 788010, India
a r t i c l e
i n f o
Article history: Received 21 July 2015 Accepted 29 July 2015 Available online 30 July 2015 Keywords: Tunnel FET Flicker noise Diffusion noise Generation–recombination noise TCAD
a b s t r a c t This paper presents a novel architecture of Tunnel Field Effect Transistor (TFET) with a circular gate and reports the effect of electrical noise on the device by comparing the results with a hetero-junction TFET. TCAD simulations involving uniform and Gaussian trap distribution conclude that the proposed Circular Gate TFET shows lesser values of noise spectral density than hetero-junction TFET. At lower frequencies, both generation–recombination noise and flicker noise dominate; at mid frequencies, only flicker noise contributes and at higher frequencies, diffusion noise dominates. Drain current in Circular Gate TFET is more prone to traps than Hetero-Junction TFET. The use of gate–drain underlap enhances the cut-off frequency of the CG-TFET in presence of Gaussian traps and makes it suitable for digital applications. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction The semiconductor industry has been on lookout for devices that can withstand the much demanded miniaturization without degradation in electrical parameters. Tunnel Field Effect Transistors (TFETs) have, in course of time, become formidable competitors in the race to replace Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) [1] due to their low leakage current and sub-kT/q Subthreshold Swing [2–4]. TFETs are gated reverse biased p–i–n diodes; they operate by mechanism of interband tunneling in contrast to thermionic conduction in MOSFETs [4–6]. But, low on-current in TFETs has been a concern for their utility in lower power applications [4]. Various geometries and structural modifications of TFETs have been proposed in order to improve the on-current. These include Double Gate TFET (DG TFET) [7,8], Silicon-on-Insulator TFET (SOI) [9–12], Hetero-Gate Dielectric TFET (HG TFET) [13], Dual Material Gate TFET (DMG TFET) [14] and bandgap engineered TFET [15]. However, the impact of noise on TFETs is less frequently reported as compared to other electrical parameters. It is now a challenge to understand the behavior of TFETs in presence of noise. A few works have been reported and modeled the impact of noise on TFETs [16–18], but extensive studies on various structures of TFETs are yet to be done. Analysis of low frequency noise in MOSFET owes its basis to the two models of fluctuation theory: (a) fluctuating free carrier based McWhorter’s fluctuation theory (1955) [19], and (b) mobility fluctuation based Hooge’s fluctuation theory (1962) [20,21]. In n-TFETs, the carriers are generated by Band-to-Band Tunneling from source to channel at the tunnel junction, which supposedly is in accordance with both the theories, as mobility fluctuations are correlated to fluctuations in free carriers [19].
⇑ Corresponding author. E-mail address: [email protected] (R. Goswami). http://dx.doi.org/10.1016/j.spmi.2015.07.064 0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.
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Fig. 1. 2D structure of (a) CG-TFET showing center of circular gate at (0, 0) for explanation of Eq. (3), and (b) HJ-TFET.
Table 1 Parameters of trap distribution. Parameter
Definition
Value
N0 E0 ES
Maximum concentration of traps in a Gaussian distribution or concentration of traps in uniform distribution EnergyMid in a Gaussian distribution EnergySig in a Gaussian distribution
1014 eV1 cm2 0 eV 0.1 eV
In this paper, a novel structure of TFET with a circular gate is proposed, and the effects of various forms of electrical noise are analyzed and compared with a hetero-junction TFET in presence and absence of traps. The noise spectral densities extracted from TCAD simulator are compared at two frequencies: 1 MHz and 10 GHz. The 2D geometries and doping specifications of the two TFETs are described in Section 2. Section 3 presents the simulation set-up. The results are stated and discussed in Section 4. Section 5 concludes the paper. 2. Device structure This work includes two different structures of Tunnel-FETs with the same dimensions and doping parameters as shown in Fig. 1. The first structure is a Silicon Tunnel FET with a Circular Gate, whereas the second structure is a Silicon Tunnel FET with a dpþ Si1xGex layer at the source-channel tunnel junction. Each device has a length of 100 nm, and a height of 30 nm. The source and drain regions are 30 nm long each, and the region between source and drain is 40 nm long. The gate of the first structure being circular, the radius of the gate is 20 nm, whereas that of the circular portion of the dielectric has a radius of 16 nm. Of the 40 nm, the second structure has a 5 nm long dpþ Si1xGex layer followed by 35 nm long Silicon. The doping specifications are: p+ source (1021 cm3), n+ drain (5 1019 cm3), channel (1016 cm3) and dpþ Si1xGex (1019 cm3). The Ge-mole fraction (x) of the Si1xGex layer is taken to be 0.5. In this work, the first structure has been referred to as Circular Gate Tunnel FET (CG-TFET) due to its circular gate, and the second as Hetero Junction Tunnel FET (HJ-TFET) due to the presence of a dpþ Si1-xGex strip in the Si-based device. 3. Simulation setup The results of the noise analysis of the TFETs have been obtained from simulation on Sentaurus TCAD [22]. Due to degenerate source and drain regions of the devices, Fermi Dirac Statistics has been employed instead of Boltzmann Statistics [22]. High doping concentration in a semiconductor causes narrowing of its bandgap. In TFETs, bandgap plays a major role in
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tunneling of carriers, and so, the Bandgap Narrowing Model has been activated. Since the doping concentrations in the regions are different, Doping Dependent Mobility Model has been used so that the effect of doping concentration on mobility of carriers is taken into account. Non Local Band-to-Band Tunneling Model has been used to signify the interband tunneling in TFETs. SRH Recombination Model has also been used. Regarding traps at the semiconductor–insulator interface, two distributions are considered: uniform and Gaussian [22], which are defined as follows.
DUNI ¼ N0 for E0 0:5ES < E < E0 þ 0:5ES
DGAU ¼ N0 exp
jE E0 j2
ð1Þ
! ð2Þ
2E2S
Of the two trap distributions, it has been discovered that Gaussian interface traps find the best fit when compared with experimental data [23]. The parameters of the trap distributions are mentioned in Table 1.
4. Results and discussion The various results associated with the noise analysis of the TFETs are discussed in sections here.
Table 2a Comparison of on and off drain currents of CG-TFET and HJ-TFET for different gate–drain underlap lengths in presence and absence of interface traps. G/D Underlap
No Traps
0 nm 4 nm 8 nm 0 nm 4 nm 8 nm
ION (lA) 5.213 10.314 7.223 42.6489 42.6321 42.5616
CG-TFET
HJ-TFET
Uniform Traps IOFF (nA) 0.852 2.569 9.169 0.3602 0.3588 0.3576
ION (lA) 0.752 1.061 1.015 37.3266 37.3207 37.2935
Gaussian Traps IOFF (pA) 2.368 1.185 3.217 103.51 100.53 100.29
ION (nA) 0.374 0.657 1.559 4969.07 4969.06 4968.73
IOFF (pA) 22.973 0.123 0.145 50.223 77.264 36.330
Table 2b Comparison of Subthreshold Swings (mV/dec) of CG-TFET and HJ-TFET for different gate–drain underlap lengths in presence and absence of interface traps. G/D underlap
No traps
Uniform
Gaussian
CG-TFET
0 nm 4 nm 8 nm
25.383 62.721 52.164
26.452 150.4693 136.965
111.701 180.102 164.1503
HJ-TFET
0 nm 4 nm 8 nm
62.179 55.659 51.661
66.262 63.615 60.823
134.055 75.089 83.007
Fig. 2. Uniform and Gaussian trap distribution as a function of energy.
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Fig. 3. Comparison of ID VGS characteristics of CG-TFET and HJ-TFET for various gate–drain underlap lengths for: (a) no traps, (b) uniform traps and (c) Gaussian traps.
4.1. Effect of traps on ID VGS characteristics of CG-TFET and HJ-TFET The current in TFET is mainly dependent on the Band-to-Band Tunneling at the tunnel junction [4] as the tunnel junction is responsible for maximum band bending owing to the change in doping concentration. Due to the circular structure of the gate, the thickness near the tunnel junction is less (marked in yellow1 circle in Fig. 1), thus employing much influence of the gate on the tunnel junction. By optimizing the gate-source overlap, the current can be improved. The dielectric thickness in a circular gate is associated with the length of the gate.
tox ¼
1
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi r 2 x2
For interpretation of color in Fig. 1, the reader is referred to the web version of this article.
ð3Þ
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Fig. 4. Sid versus VGS plots of CG-TFET for three drain voltage (VDS), 0.1 V, 0.3 V and 0.5 V at 4 nm gate–drain underlap length, at 1 MHz and 10 GHz for Gaussian trap distribution.
where tox is the dielectric thickness as a function of gate radius, r and channel position, x for a circular gate structure centered at (0, 0). The gate–drain proximity is a cause of ambipolar current in TFETs [24,25]. From Eq. (3), it is evident that by changing the gate radius, both the dielectric thickness at the tunnel junction as well as ambipolar current arising out of gate–drain proximity can be reduced. Thus in a CG-TFET, a change in radius leads to two modifications in the structure: increase in gate–drain underlap and reduction of dielectric thickness near tunnel junction. This is, in fact, an advantage of CG-TFET over HJ-TFET. The effect of traps on transfer characteristics of the two TFETs are discussed in this section. The characteristics are shown in Fig. 3 for the two structures for different Gate–Drain (G/D) underlap lengths in presence and absence of traps in order to understand the effects. Table 2a lists the various on and off currents, whereas Table 2b compares the Subthreshold Swing (SS) of the two structures. Using gate–drain underlap reduces the unwanted drain current which is detrimental to circuit applications of the devices. This is concluded from Fig. 3 where the structures with gate–drain underlap of 0 nm possesses the highest ambipolar current which reduces when the gate–drain underlap is increased (4 nm and 8 nm). Both the structures exhibit improved characteristics in absence of traps as compared to those in presence of traps. Gaussian traps degrade the characteristics more than uniform traps when compared to the case without traps. But, drain current of HJ-TFET remains less dependent on traps as compared to CG-TFET. The trapping and de-trapping of carriers at Si/HfO2 interface cause a lowering of drain current in presence of traps. However, it is observed that the ID VGS plots of HJ-TFET are almost similar to one another for different underlap lengths, as compared to those of CG-TFET in each case of trap distribution. This is because in CG-TFET, with the change in underlap length, the gate dielectric thickness also changes throughout the length under the gate owing to its circular structure. This causes a significant effect on the tunneling of carriers and hence, observable variation in drain current. On the other hand, in case of HJ-TFET, although the G/D underlap is changed, the gate dielectric thickness remains constant at 2 nm. Moreover, for a rectangular gate, reduction in gate length does not affect much the tunnel current, because the Band-To-Band tunneling occurs at the tunnel junction and a gate long enough to cause bending at the junction is sufficient. This shows that in rectangular gate TFETs, the device is independent of channel length modulation- an advantage over conventional MOSFETs. It is observed from Table 2b that the Subthreshold Swing is dependent on the nature of traps. In each case of G/D underlap for both the structures, SS increases in the ascending order: no traps, uniform traps and Gaussian traps. This can be associated with Fig. 2, where Gaussian traps exhibit variable trap density with energy as compared to a constant trap density in case of uniform traps. Absence of traps shows excellent results, where CG-TFET produces the best value of SS at G/D underlap of 0 nm. The plot of drain current versus gate voltage in Fig. 3(a) exhibits a steep slope at low VGS, which gradually reduces as VGS increases. Since SS is related to the differentiation of logarithmic drain current (ID) with respect to gate voltage (VGS) by
SS ¼
1 @ðlog10 ID Þ @V GS
ð4Þ
so, in absence of traps as in Fig. 3(a), a steep slope results in a low SS. In presence of traps, the SS degrades considerably. As evident from Fig. 3, the use of traps has resulted in irregularities, i.e, unexpected change in gradient of the ID VGS plots of CG-TFET for the case of no underlap for Gaussian traps. This has been explained with the help of energy band diagram of CG-TFET (inset) extracted from the device simulator. The bands have been shown at four points on the ID VGS curve at values of gate-source voltage, 0.35 V, 0.55 V, 0.80 V and 0.84 V where the curve changes slope. As gate voltage increases, the bands at the source-channel tunnel junction bend. The presence of Gaussian nature of traps cause fluctuation of carriers in the channel resulting in reduced surface potential. The circular structure of the gate and the presence of Gaussian traps result in a ‘hump’ form of barrier in the channel. As a consequence, the electrons tunneling from conduction band of source to valence band of channel find it difficult to acquire the energy to cross the energy barrier (hump) shown in the inset. In case of other underlap lengths, with the increase in underlap length, the radius of the gate reduces, causing reduction in dielectric
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Fig. 5. Comparison of net electron noise voltage spectral density versus VGS between CG-TFET and HJ-TFET at 1 MHz and 10 GHz, and 4 nm G/D underlap for three cases of trap distribution: (a) no traps, (b) uniform, and (c) Gaussian.
thickness at each point along the gate and hence, easy transmission of electrons over the hump-barrier even in presence of traps. 4.2. Drain current noise spectral density (Sid) of CG-TFET As VGS is increased in Fig. 4, the drain current noise spectral density involving Gaussian traps shows an increasing trend at 1 MHz, whereas, at 10 GHz, the spectral density gradually increases till VGS = 0.5 V, after which it shows a non-uniform descend. The presence of semiconductor–insulator interface traps causes fluctuation in the number of carriers in the channel. As VDS is increased, the lateral electric field at the tunnel junction increases, affecting trapping and de-trapping of carriers in the channel. So, the drain current noise increases. Drain current noise follows an inversely proportional relationship with frequency; hence, it has reduced values at 10 GHz than at 1 MHz. The flicker current noise follows the equation [16]
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Fig. 6. Comparison of drain current noise spectral density versus VGS between CG-TFET and HJ-TFET at 4 nm G/D underlap and frequencies, 1 MHz and 10 GHz for Gaussian trap distribution.
Fig. 7. Comparison of transconductance versus VGS between CG-TFET and HJ-TFET at 4 nm G/D underlap for three cases of trap distribution: no traps, uniform and Gaussian.
Sid ðf Þ ¼
2 B q2 I2D Nt ðEFN Þ þ 2 F F e2ox WL0 af c
ð5Þ
where F is the electric field, B is a constant, Nt (EFN) is the interface trap, eox is the gate dielectric constant, W is the width of the device fixed at 1 lm, LI is the effective gate length, a is the attenuation factor, f is the frequency, and c is the factor that governs the dependence of Sid on frequency. 4.3. Noise voltage spectral density of CG-TFET and HJ-TFET The gate voltage noise spectral densities of CG-TFET and HJ-TFET are reported and elaborated in this section for three cases: uniform, Gaussian and no traps. The results are compared at 1 MHz and 10 GHz at gate–drain underlap of 4 nm in both the structures. Since the TFETs operate in n-mode, so, the electron noise voltage spectral densities are plotted. The net and flicker noise voltage spectral densities are shown for the three cases of traps whereas, the diffusion and generation– recombination noise voltage spectral densities are compared for Gaussian trap distribution only. 4.3.1. Net electron gate voltage noise spectral density (SvgeeNET) It is observed from Fig. 5, that at 10 GHz and extremely low VGS, values of input-referred noise voltage spectral density of CG-TFET are closer to those of HJ-TFET, but as VGS is increased, CG-TFET shows much reduced values than HJ-TFET. At 1 MHz, HJ-TFET has reduced values than CG-TFET at low VGS in absence of traps, but at higher voltages greater than 0.4 V, SvgeeNET of CG-TFET reduces with a large slope. For the case of uniform trap distribution at 1 MHz, the values of net voltage noise spectral density of CG-TFET are almost comparable to those of HJ-TFET at low voltage till 0.4 V; however, the CG-TFET shows improved characteristics at voltages above 0.4 V but with lesser gradient as compared to the case of no traps. For the case of Gaussian trap distribution at 1 MHz, the SvgeeNET versus VGS plots in Fig. 5 (c) depict that CG-TFET has better values than
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Fig. 8. Comparison of flicker electron noise voltage spectral density versus VGS between CG-TFET and HJ-TFET at 1 MHz and 10 GHz, and 4 nm G/D underlap for three cases of trap distribution: (a) no traps, (b) uniform, and (c) Gaussian.
HJ-TFET. The gate voltage noise spectral density is directly dependent on Sid and inversely dependent on the square of transconductance (gm) [16]. The inverted peaks in input-referred noise spectral density in HJ-TFET at 1 MHz is due to the presence of a notch-like feature in the plot of Sid versus VGS shown in Fig. 6. The plots of transconductance in Fig. 7 show an increasing trend as gate voltage increases. At 10 GHz too, at low voltage a notch can be observed, but it is not significant as compared to that at 1 MHz.
4.3.2. Flicker G-R electron noise voltage spectral density (SvgeeFLICKG-R) The most realistic consideration of flicker noise is the additive effect of the various generation–recombination noises produced by subbands of impurities or defects, or mobility fluctuations [26]. Since BTBT generation is the prime mechanism by which TFETs operate, this paper considers flicker noise caused by generation–recombination of carriers. It has been observed in Fig. 8 that the HJ TFET has better noise characteristics for both 1 MHz and 10 GHz for a low range of voltage. After that, noise in HJ TFET dominates the CG TFET at both the frequencies.
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Fig. 9. Comparison of diffusion electron noise voltage spectral density versus VGS between CG-TFET and HJ-TFET at 1 MHz and 10 GHz, and 4 nm G/D underlap for Gaussian trap distribution.
Fig. 10. Comparison of generation–recombination electron noise voltage spectral density versus VGS between CG-TFET and HJ-TFET at 1 MHz and 10 GHz, and 4 nm G/D underlap for Gaussian trap distribution.
4.3.3. Diffusion electron noise voltage spectral density (SvgeeDIFF) Diffusion component of the channel current gives rise to diffusion noise. The lateral electric field in TFET causes the band to band tunneling generated carrier near the source to diffuse through the channel toward the drain [27]. The diffusion current is proportional to mobility of electrons. The diffusion noise is widely used for modeling in a subthreshold region, but it has never been used for devices in strong inversion. TFET actually works in weak inversion. It has been observed in Fig. 9 that at high frequency, the diffusion noise component is more pronounced as compared to flicker. Moreover, with the increasing gate voltage, HJ-TFET has more diffusion noise compared to CG-TFET. In case of TFETs, the ID VGS characteristics are diffusion-limited at higher gate voltages when the values of drain current start to saturate [27]. In this paper, the devices have been considered at low voltages, the maximum value of VGS being 1 V. The effect of diffusion current on Svg at high frequency is dramatic. Svg increases with VGS because drain current increases with VGS. 4.3.4. Generation–recombination electron noise voltage spectral density (SvgeeG-R) The plot of electron voltage spectral density due to generation–recombination versus gate voltage is shown in Fig. 10. From an overall perspective, CG-TFET depicts lower noise than HJ-TFET. Generation–recombination noise is due to the fluctuations of number of carriers in the channel; in TFETs, the carriers are determined by Band-to-Band generation rate. The location of traps at the tunnel junction affects the generation–recombination process in TFET, mostly governed by BTBT. Electrons possessing energy close to the quasi Fermi level undergo trapping and de-trapping at the Si/SiO2 interface [17]. This causes changes in the junction electric field, which in turn, affects the generation–recombination rate, because the generation–recombination, G has a dependence on electric field, E given by [21,28]
jEj2 E1:5 G¼A exp B G EG jEj
! ð6Þ
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Fig. 11. Band-to-Band generation rate in (a) CG-TFET and (b) HJ-TFET, extracted from the simulator, in case of Gaussian trap distribution for gate–drain underlap of 4 nm at VDS = 0.5 V and VGS = 1 V.
Fig. 12. Drain current noise spectral density versus frequency of CG-TFET for gate–drain underlap of 4 nm at VDS = 0.5 V, and drain current 1 lA/lm in presence of uniform traps.
where A and B are constants, and EG is the band gap of the semiconductor. The contour plot of Band-to-Band (BTB) generation rate in CG-TFET and HJ-TFET extracted from TCAD simulator are shown in Fig. 11(a) and (b) respectively. The BTB generation rate in both the devices is concentrated around the source-channel tunnel junction where the tunneling occurs. The maximum value of BTB Generation rate in CG-FET is lesser than that in HJ-TFET when considering Gaussian traps. Moreover, the BTB Generation spreads over a larger area in HJ-TFET than in CG-TFET. This is because the HJ-TFET has low bandgap material, Si0.5Ge0.5 at the tunnel junction, thus increasing the tunneling probability.
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Fig. 13. Cut-off frequency as a function of VGS for CG-TFET in case of 4 nm G/D underlap in presence of Gaussian trap distribution.
Fig. 14. Total gate capacitance (CGG) versus VGS plots of CG-TFET for three drain voltage (VDS), 0.1 V, 0.3 V and 0.5 V at 4 nm gate–drain underlap length, at 1 MHz and 10 GHz for Gaussian trap distribution.
4.4. Variation of drain current noise spectral density versus frequency The variation of drain current noise spectral density with frequency for both the devices in presence of uniform traps is shown in Fig. 12. HJ-TFET shows higher drain current noise than CG-TFET at all frequencies. The drain current noise negligibly decreases in the lower frequencies from 10 Hz to 1 MHz; however, after 1 MHz, the curves attain a descending slope. After 100 MHz, the values of the current noise spectral density in HJ-TFET are of the same order of magnitude, whereas in CG-TFET, there is a slight change of slope at 1 GHz. Up to 1 MHz, the current noise spectral density is the result of contribution of generation–recombination noise, and flicker noise caused due to generation–recombination as observed from the plots of gate voltage noise spectral density. Beyond 1 MHz, the noise current spectral density is mainly dominated by flicker noise, as evident from the slope of the plot. At higher frequencies, diffusion noise dominates as observed in the plot of input-referred noise; the plot of noise spectral density in HJ-TFET follows a negligible change with frequency whereas, in CG-TFET, the values reduce considerably. 4.5. Cut-off frequency of CG-TFET The cut-off frequency of CG-TFET increases with VGS. The cut-off frequency (fT) depends on the ratio of gm (transconductance) and CGG (gate-to-gate capacitance) given by
fT ¼
gm 2pC GG
ð7Þ
Plotted in Fig. 13, up to a gate voltage of 0.65 V, the cut-off frequency increases, after which the values tend to saturate. This is explained with the help of Fig. 14. The plot of CGG for gate–drain underlap of 4 nm attains a rising trend at around 0.65 V. For values above 0.65 V, CGG in Eq. (5) increases by a greater factor than the numerator. However, there is an overall increasing nature of cut-off frequency as a function of VGS. The gate–drain underlap of 4 nm in CG-TFET has contributed to
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reduced gate–drain capacitance (CGD), thus lowering the value of CGG as compared to the case where there is no underlap [28]. This has enhanced the cut-off frequency of the device. In TFETs, CGD is the dominant capacitance which causes overshoot in transient response of digital inverter circuit. Reduction of CGD is necessary to prevent the undesired overshoot. The lowering of CGD and hence CGG in CG-TFET has made the cut-off frequency of Fig. 13 vary in a similar manner as that in MOSFET [29]. 5. Conclusion The proposed CG-TFET is less prone to noise as compared to HJ-TFET as observed in case of various trap distributions. At high frequency, the drain current noise spectral density is reduced, and decreases with frequency, unlike HJ-TFET. The diffusion noise component of the gate voltage noise spectral density is dominant at high frequency, whereas the generation– recombination noise contributes more at low frequency. The use of gate–drain underlap improves the cut-off frequency of the CG-TFET in presence of Gaussian traps and makes it suitable for digital applications as well as low noise analog RF design at low supply voltage. The effect of interface traps on transfer characteristics of CG-TFET is, however, more significant as compared to HJ-TFET owing to the circular structure of the gate. Acknowledgement The authors would like to acknowledge the Microelectronics Computational Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology Silchar for providing all the facilities for carrying out the work. References [1] S. Sarangi, S. Bhushan, A. Santra, S. Dubey, S. Jit, P.K. Tiwari, A rigorous simulation based study of gate misalignment effects in gate engineered doublegate (DG) MOSFETs, Superlattices Microstruct. 60 (2013) 263–279, http://dx.doi.org/10.1016/j.spmi.2013.05.009. [2] S.O. Koswatta, M.S. Lundstrom, D.E. Nikonov, Performance comparison between p–i–n tunneling transistors and conventional MOSFETs, IEEE Trans. Electron Devices 56 (2009) 456–465, http://dx.doi.org/10.1109/TED.2008.2011934. [3] W.Y. Choi, B.G. Park, J.D. Lee, T.J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Device Lett. 28 (2007) 743–745, http://dx.doi.org/10.1109/LED.2007.901273. [4] C. Le Royer, F. Mayer, Exhaustive experimental study of tunnel field effect transistors (TFETs): from materials to architecture, in: Proc. 10th Int. Conf. Ultim. Integr. Silicon, ULIS 2009 (2009), pp. 53–56, doi: 10.1109/ULIS.2009.4897537. [5] S. Banerjee, W. Richardson, J. Coleman, a. Chatterjee, A new three-terminal tunnel device, IEEE Electron Device Lett. 8 (1987) 347–349, http:// dx.doi.org/10.1109/EDL.1987.26655. [6] K.K. Bhuwalka, J. Schulze, I. Eisele, Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering, IEEE Trans. Electron Devices 52 (2005) 909–917, http://dx.doi.org/10.1109/TED.2005.846318. [7] K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-k gate dielectric, IEEE Trans. Electron Devices 54 (2007) 1725–1733, http://dx.doi.org/ 10.1109/TED.2007.899389. [8] K. Boucart, A.M. Ionescu, Double gate tunnel FET with ultrathin silicon body and high-K gate dielectric, in: Proceedings of the 36th European Solid-State Device Research Conference, ESSDER 2006 (2006) pp. 383–386, doi: 10.1109/ESSDER.2006.307718. [9] A. Biswas, S.S. Dan, C. Le Royer, W. Grabinski, A.M. Ionescu, TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model, Microelectron. Eng. 98 (2012) 334–337, http://dx.doi.org/10.1016/j.mee.2012.07.077. [10] A. Guo, P. Matheu, T.J.K. Liu, SOI TFET ION/IOFF enhancement via back biasing, IEEE Trans. Electron Devices 58 (2011) 3283–3285, http://dx.doi.org/ 10.1109/TED.2011.2161480. [11] J. Wan, C. Le Royer, A. Zaslavsky, S. Cristoloveanu, Tunneling FETs on SOI: suppression of ambipolar leakage low-frequency noise behavior, and modeling, Solid State Electron. 65–66 (2011) 226–233, http://dx.doi.org/10.1016/j.sse.2011.06.012. [12] S. Chander, B. Bhowmick, S. Baishya, Heterojunction fully depleted SOI-TFET with oxide/source overlap, Superlattices Microstruct. 86 (2015) 43–50, http://dx.doi.org/10.1016/j.spmi.2015.07.030. [13] W.Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field-effect transistors, IEEE Trans. Electron Devices 57 (2010) 2317–2319, http://dx.doi.org/ 10.1109/TED.2010.2052167. [14] S. Saurabh, M.J. Kumar, Novel attributes of a dual material gate nanoscale tunnel field-effect transistor, IEEE Trans. Electron Devices 58 (2011) 404– 410, http://dx.doi.org/10.1109/TED.2010.2093142. [15] M. Luisier, G. Klimeck, Investigation of InxGa1xAs ultra-thin-body tunneling FETs using a full-band and atomistic approach, in: International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2009 (2009) pp. 1–4, doi: 10.1109/SISPAD.2009.5290248. [16] R. Pandey, B. Rajamohanan, H. Liu, V. Narayanan, S. Datta, Electrical noise in heterojunction interband tunnel FETs, IEEE Trans. Electron Devices 61 (2014) 552–560, http://dx.doi.org/10.1109/TED.2013.2293497. [17] Q. Huang, R. Huang, C. Chen, C. Wu, J. Wang, C. Wang, et al., Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering s c, in: 2014 Symposium on VLSI Technology: Digest of Technical Papers (2014) pp.1–2, doi: 10.1109/VLSIT.2014.6894371. [18] R. Bijesh, D.K. Mohata, H. Liu, S. Datta, Flicker noise characterization and analytical modeling of homo and hetero-junction III–V tunnel FETs, Device Res. Conf. – Conf. Dig. DRC 37 (2012) 203–204, http://dx.doi.org/10.1109/DRC.2012.6257032. [19] A.P. Van Der Wel, E.aM. Klumperink, J.S. Kolhatkar, E. Hoekstra, M.F. Snoeij, C. Salm, et al, Low-frequency noise phenomena in switched MOSFETs, IEEE J. Solid-State Circuits 42 (2007) 540–549, http://dx.doi.org/10.1109/JSSC.2006.891714. [20] F.N. Hooge, 1/F noise sources, IEEE Trans. Electron Devices 41 (1994) 1926–1935, http://dx.doi.org/10.1109/16.333808. [21] J. Xu, J. Deen, MOSFET 1/F noise model based on mobility fluctuation in linear region, Electron. Lett. 38 (2002) 429–431, http://dx.doi.org/10.1049/ el:20020282. [22] Sentaurus Device User, Synopsys, (2009) 2009. [23] W. Wang, J. Hwang, Y. Xuan, P.D. Ye, Analysis of electron mobility in inversion-mode MOSFETs, IEEE Trans. Electron Devices 58 (2011) 1972–1978, http://dx.doi.org/10.1109/TED.2011.2146255. [24] Hraziia, A. Vladimirescu, A. Amara, C. Anghel, An analysis on the ambipolar current in Si double-gate tunnel FETs, Solid-State Electron. 70 (2012) 67– 72, http://dx.doi.org/10.1016/j.sse.2011.11.009. [25] A.S. Verhulst, W.G. Vandenberghe, K. Maex, G. Groeseneken, Tunnel field-effect transistor without gate–drain overlap, Appl. Phys. Lett. 91 (2007), http://dx.doi.org/10.1063/1.2757593.
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[26] J.P. Nougier, Fluctuations and noise of hot carriers in semiconductor materials and devices, IEEE Trans. Electron Devices 41 (1994) 2034–2049, http:// dx.doi.org/10.1109/16.333821. [27] S. Mookerjea, D. Mohata, Temperature-dependent-characteristics of a vertical tunnel FET, Device Lett. IEEE 31 (2010) 564–566.. [28] M.G. Bardon, H.P. Neves, R. Puers, C. Van Hoof, Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions, IEEE Trans. Electron Devices 57 (2010) 827–834, http://dx.doi.org/10.1109/TED.2010.2040661. [29] R. Narang, M. Saxena, R.S. Gupta, M. Gupta, Device and circuit level performance comparison of tunnel FET architectures and impact of heterogeneous gate dielectric, J. Semicond. Technol. Sci. 13 (2013) 224–236, http://dx.doi.org/10.5573/JSTS.2013.13.3.224.
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Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Electrical noise in Circular Gate Tunnel FET in presence of interface traps Rupam Goswami ⇑, Brinda Bhowmick, Srimanta Baishya Department of Electronics & Communication Engineering, National Institute of Technology Silchar, Assam 788010, India
a r t i c l e
i n f o
Article history: Received 21 July 2015 Accepted 29 July 2015 Available online 30 July 2015 Keywords: Tunnel FET Flicker noise Diffusion noise Generation–recombination noise TCAD
a b s t r a c t This paper presents a novel architecture of Tunnel Field Effect Transistor (TFET) with a circular gate and reports the effect of electrical noise on the device by comparing the results with a hetero-junction TFET. TCAD simulations involving uniform and Gaussian trap distribution conclude that the proposed Circular Gate TFET shows lesser values of noise spectral density than hetero-junction TFET. At lower frequencies, both generation–recombination noise and flicker noise dominate; at mid frequencies, only flicker noise contributes and at higher frequencies, diffusion noise dominates. Drain current in Circular Gate TFET is more prone to traps than Hetero-Junction TFET. The use of gate–drain underlap enhances the cut-off frequency of the CG-TFET in presence of Gaussian traps and makes it suitable for digital applications. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction The semiconductor industry has been on lookout for devices that can withstand the much demanded miniaturization without degradation in electrical parameters. Tunnel Field Effect Transistors (TFETs) have, in course of time, become formidable competitors in the race to replace Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) [1] due to their low leakage current and sub-kT/q Subthreshold Swing [2–4]. TFETs are gated reverse biased p–i–n diodes; they operate by mechanism of interband tunneling in contrast to thermionic conduction in MOSFETs [4–6]. But, low on-current in TFETs has been a concern for their utility in lower power applications [4]. Various geometries and structural modifications of TFETs have been proposed in order to improve the on-current. These include Double Gate TFET (DG TFET) [7,8], Silicon-on-Insulator TFET (SOI) [9–12], Hetero-Gate Dielectric TFET (HG TFET) [13], Dual Material Gate TFET (DMG TFET) [14] and bandgap engineered TFET [15]. However, the impact of noise on TFETs is less frequently reported as compared to other electrical parameters. It is now a challenge to understand the behavior of TFETs in presence of noise. A few works have been reported and modeled the impact of noise on TFETs [16–18], but extensive studies on various structures of TFETs are yet to be done. Analysis of low frequency noise in MOSFET owes its basis to the two models of fluctuation theory: (a) fluctuating free carrier based McWhorter’s fluctuation theory (1955) [19], and (b) mobility fluctuation based Hooge’s fluctuation theory (1962) [20,21]. In n-TFETs, the carriers are generated by Band-to-Band Tunneling from source to channel at the tunnel junction, which supposedly is in accordance with both the theories, as mobility fluctuations are correlated to fluctuations in free carriers [19].
⇑ Corresponding author. E-mail address: [email protected] (R. Goswami). http://dx.doi.org/10.1016/j.spmi.2015.07.064 0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.
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Fig. 1. 2D structure of (a) CG-TFET showing center of circular gate at (0, 0) for explanation of Eq. (3), and (b) HJ-TFET.
Table 1 Parameters of trap distribution. Parameter
Definition
Value
N0 E0 ES
Maximum concentration of traps in a Gaussian distribution or concentration of traps in uniform distribution EnergyMid in a Gaussian distribution EnergySig in a Gaussian distribution
1014 eV1 cm2 0 eV 0.1 eV
In this paper, a novel structure of TFET with a circular gate is proposed, and the effects of various forms of electrical noise are analyzed and compared with a hetero-junction TFET in presence and absence of traps. The noise spectral densities extracted from TCAD simulator are compared at two frequencies: 1 MHz and 10 GHz. The 2D geometries and doping specifications of the two TFETs are described in Section 2. Section 3 presents the simulation set-up. The results are stated and discussed in Section 4. Section 5 concludes the paper. 2. Device structure This work includes two different structures of Tunnel-FETs with the same dimensions and doping parameters as shown in Fig. 1. The first structure is a Silicon Tunnel FET with a Circular Gate, whereas the second structure is a Silicon Tunnel FET with a dpþ Si1xGex layer at the source-channel tunnel junction. Each device has a length of 100 nm, and a height of 30 nm. The source and drain regions are 30 nm long each, and the region between source and drain is 40 nm long. The gate of the first structure being circular, the radius of the gate is 20 nm, whereas that of the circular portion of the dielectric has a radius of 16 nm. Of the 40 nm, the second structure has a 5 nm long dpþ Si1xGex layer followed by 35 nm long Silicon. The doping specifications are: p+ source (1021 cm3), n+ drain (5 1019 cm3), channel (1016 cm3) and dpþ Si1xGex (1019 cm3). The Ge-mole fraction (x) of the Si1xGex layer is taken to be 0.5. In this work, the first structure has been referred to as Circular Gate Tunnel FET (CG-TFET) due to its circular gate, and the second as Hetero Junction Tunnel FET (HJ-TFET) due to the presence of a dpþ Si1-xGex strip in the Si-based device. 3. Simulation setup The results of the noise analysis of the TFETs have been obtained from simulation on Sentaurus TCAD [22]. Due to degenerate source and drain regions of the devices, Fermi Dirac Statistics has been employed instead of Boltzmann Statistics [22]. High doping concentration in a semiconductor causes narrowing of its bandgap. In TFETs, bandgap plays a major role in
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tunneling of carriers, and so, the Bandgap Narrowing Model has been activated. Since the doping concentrations in the regions are different, Doping Dependent Mobility Model has been used so that the effect of doping concentration on mobility of carriers is taken into account. Non Local Band-to-Band Tunneling Model has been used to signify the interband tunneling in TFETs. SRH Recombination Model has also been used. Regarding traps at the semiconductor–insulator interface, two distributions are considered: uniform and Gaussian [22], which are defined as follows.
DUNI ¼ N0 for E0 0:5ES < E < E0 þ 0:5ES
DGAU ¼ N0 exp
jE E0 j2
ð1Þ
! ð2Þ
2E2S
Of the two trap distributions, it has been discovered that Gaussian interface traps find the best fit when compared with experimental data [23]. The parameters of the trap distributions are mentioned in Table 1.
4. Results and discussion The various results associated with the noise analysis of the TFETs are discussed in sections here.
Table 2a Comparison of on and off drain currents of CG-TFET and HJ-TFET for different gate–drain underlap lengths in presence and absence of interface traps. G/D Underlap
No Traps
0 nm 4 nm 8 nm 0 nm 4 nm 8 nm
ION (lA) 5.213 10.314 7.223 42.6489 42.6321 42.5616
CG-TFET
HJ-TFET
Uniform Traps IOFF (nA) 0.852 2.569 9.169 0.3602 0.3588 0.3576
ION (lA) 0.752 1.061 1.015 37.3266 37.3207 37.2935
Gaussian Traps IOFF (pA) 2.368 1.185 3.217 103.51 100.53 100.29
ION (nA) 0.374 0.657 1.559 4969.07 4969.06 4968.73
IOFF (pA) 22.973 0.123 0.145 50.223 77.264 36.330
Table 2b Comparison of Subthreshold Swings (mV/dec) of CG-TFET and HJ-TFET for different gate–drain underlap lengths in presence and absence of interface traps. G/D underlap
No traps
Uniform
Gaussian
CG-TFET
0 nm 4 nm 8 nm
25.383 62.721 52.164
26.452 150.4693 136.965
111.701 180.102 164.1503
HJ-TFET
0 nm 4 nm 8 nm
62.179 55.659 51.661
66.262 63.615 60.823
134.055 75.089 83.007
Fig. 2. Uniform and Gaussian trap distribution as a function of energy.
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Fig. 3. Comparison of ID VGS characteristics of CG-TFET and HJ-TFET for various gate–drain underlap lengths for: (a) no traps, (b) uniform traps and (c) Gaussian traps.
4.1. Effect of traps on ID VGS characteristics of CG-TFET and HJ-TFET The current in TFET is mainly dependent on the Band-to-Band Tunneling at the tunnel junction [4] as the tunnel junction is responsible for maximum band bending owing to the change in doping concentration. Due to the circular structure of the gate, the thickness near the tunnel junction is less (marked in yellow1 circle in Fig. 1), thus employing much influence of the gate on the tunnel junction. By optimizing the gate-source overlap, the current can be improved. The dielectric thickness in a circular gate is associated with the length of the gate.
tox ¼
1
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi r 2 x2
For interpretation of color in Fig. 1, the reader is referred to the web version of this article.
ð3Þ
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Fig. 4. Sid versus VGS plots of CG-TFET for three drain voltage (VDS), 0.1 V, 0.3 V and 0.5 V at 4 nm gate–drain underlap length, at 1 MHz and 10 GHz for Gaussian trap distribution.
where tox is the dielectric thickness as a function of gate radius, r and channel position, x for a circular gate structure centered at (0, 0). The gate–drain proximity is a cause of ambipolar current in TFETs [24,25]. From Eq. (3), it is evident that by changing the gate radius, both the dielectric thickness at the tunnel junction as well as ambipolar current arising out of gate–drain proximity can be reduced. Thus in a CG-TFET, a change in radius leads to two modifications in the structure: increase in gate–drain underlap and reduction of dielectric thickness near tunnel junction. This is, in fact, an advantage of CG-TFET over HJ-TFET. The effect of traps on transfer characteristics of the two TFETs are discussed in this section. The characteristics are shown in Fig. 3 for the two structures for different Gate–Drain (G/D) underlap lengths in presence and absence of traps in order to understand the effects. Table 2a lists the various on and off currents, whereas Table 2b compares the Subthreshold Swing (SS) of the two structures. Using gate–drain underlap reduces the unwanted drain current which is detrimental to circuit applications of the devices. This is concluded from Fig. 3 where the structures with gate–drain underlap of 0 nm possesses the highest ambipolar current which reduces when the gate–drain underlap is increased (4 nm and 8 nm). Both the structures exhibit improved characteristics in absence of traps as compared to those in presence of traps. Gaussian traps degrade the characteristics more than uniform traps when compared to the case without traps. But, drain current of HJ-TFET remains less dependent on traps as compared to CG-TFET. The trapping and de-trapping of carriers at Si/HfO2 interface cause a lowering of drain current in presence of traps. However, it is observed that the ID VGS plots of HJ-TFET are almost similar to one another for different underlap lengths, as compared to those of CG-TFET in each case of trap distribution. This is because in CG-TFET, with the change in underlap length, the gate dielectric thickness also changes throughout the length under the gate owing to its circular structure. This causes a significant effect on the tunneling of carriers and hence, observable variation in drain current. On the other hand, in case of HJ-TFET, although the G/D underlap is changed, the gate dielectric thickness remains constant at 2 nm. Moreover, for a rectangular gate, reduction in gate length does not affect much the tunnel current, because the Band-To-Band tunneling occurs at the tunnel junction and a gate long enough to cause bending at the junction is sufficient. This shows that in rectangular gate TFETs, the device is independent of channel length modulation- an advantage over conventional MOSFETs. It is observed from Table 2b that the Subthreshold Swing is dependent on the nature of traps. In each case of G/D underlap for both the structures, SS increases in the ascending order: no traps, uniform traps and Gaussian traps. This can be associated with Fig. 2, where Gaussian traps exhibit variable trap density with energy as compared to a constant trap density in case of uniform traps. Absence of traps shows excellent results, where CG-TFET produces the best value of SS at G/D underlap of 0 nm. The plot of drain current versus gate voltage in Fig. 3(a) exhibits a steep slope at low VGS, which gradually reduces as VGS increases. Since SS is related to the differentiation of logarithmic drain current (ID) with respect to gate voltage (VGS) by
SS ¼
1 @ðlog10 ID Þ @V GS
ð4Þ
so, in absence of traps as in Fig. 3(a), a steep slope results in a low SS. In presence of traps, the SS degrades considerably. As evident from Fig. 3, the use of traps has resulted in irregularities, i.e, unexpected change in gradient of the ID VGS plots of CG-TFET for the case of no underlap for Gaussian traps. This has been explained with the help of energy band diagram of CG-TFET (inset) extracted from the device simulator. The bands have been shown at four points on the ID VGS curve at values of gate-source voltage, 0.35 V, 0.55 V, 0.80 V and 0.84 V where the curve changes slope. As gate voltage increases, the bands at the source-channel tunnel junction bend. The presence of Gaussian nature of traps cause fluctuation of carriers in the channel resulting in reduced surface potential. The circular structure of the gate and the presence of Gaussian traps result in a ‘hump’ form of barrier in the channel. As a consequence, the electrons tunneling from conduction band of source to valence band of channel find it difficult to acquire the energy to cross the energy barrier (hump) shown in the inset. In case of other underlap lengths, with the increase in underlap length, the radius of the gate reduces, causing reduction in dielectric
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Fig. 5. Comparison of net electron noise voltage spectral density versus VGS between CG-TFET and HJ-TFET at 1 MHz and 10 GHz, and 4 nm G/D underlap for three cases of trap distribution: (a) no traps, (b) uniform, and (c) Gaussian.
thickness at each point along the gate and hence, easy transmission of electrons over the hump-barrier even in presence of traps. 4.2. Drain current noise spectral density (Sid) of CG-TFET As VGS is increased in Fig. 4, the drain current noise spectral density involving Gaussian traps shows an increasing trend at 1 MHz, whereas, at 10 GHz, the spectral density gradually increases till VGS = 0.5 V, after which it shows a non-uniform descend. The presence of semiconductor–insulator interface traps causes fluctuation in the number of carriers in the channel. As VDS is increased, the lateral electric field at the tunnel junction increases, affecting trapping and de-trapping of carriers in the channel. So, the drain current noise increases. Drain current noise follows an inversely proportional relationship with frequency; hence, it has reduced values at 10 GHz than at 1 MHz. The flicker current noise follows the equation [16]
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Fig. 6. Comparison of drain current noise spectral density versus VGS between CG-TFET and HJ-TFET at 4 nm G/D underlap and frequencies, 1 MHz and 10 GHz for Gaussian trap distribution.
Fig. 7. Comparison of transconductance versus VGS between CG-TFET and HJ-TFET at 4 nm G/D underlap for three cases of trap distribution: no traps, uniform and Gaussian.
Sid ðf Þ ¼
2 B q2 I2D Nt ðEFN Þ þ 2 F F e2ox WL0 af c
ð5Þ
where F is the electric field, B is a constant, Nt (EFN) is the interface trap, eox is the gate dielectric constant, W is the width of the device fixed at 1 lm, LI is the effective gate length, a is the attenuation factor, f is the frequency, and c is the factor that governs the dependence of Sid on frequency. 4.3. Noise voltage spectral density of CG-TFET and HJ-TFET The gate voltage noise spectral densities of CG-TFET and HJ-TFET are reported and elaborated in this section for three cases: uniform, Gaussian and no traps. The results are compared at 1 MHz and 10 GHz at gate–drain underlap of 4 nm in both the structures. Since the TFETs operate in n-mode, so, the electron noise voltage spectral densities are plotted. The net and flicker noise voltage spectral densities are shown for the three cases of traps whereas, the diffusion and generation– recombination noise voltage spectral densities are compared for Gaussian trap distribution only. 4.3.1. Net electron gate voltage noise spectral density (SvgeeNET) It is observed from Fig. 5, that at 10 GHz and extremely low VGS, values of input-referred noise voltage spectral density of CG-TFET are closer to those of HJ-TFET, but as VGS is increased, CG-TFET shows much reduced values than HJ-TFET. At 1 MHz, HJ-TFET has reduced values than CG-TFET at low VGS in absence of traps, but at higher voltages greater than 0.4 V, SvgeeNET of CG-TFET reduces with a large slope. For the case of uniform trap distribution at 1 MHz, the values of net voltage noise spectral density of CG-TFET are almost comparable to those of HJ-TFET at low voltage till 0.4 V; however, the CG-TFET shows improved characteristics at voltages above 0.4 V but with lesser gradient as compared to the case of no traps. For the case of Gaussian trap distribution at 1 MHz, the SvgeeNET versus VGS plots in Fig. 5 (c) depict that CG-TFET has better values than
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Fig. 8. Comparison of flicker electron noise voltage spectral density versus VGS between CG-TFET and HJ-TFET at 1 MHz and 10 GHz, and 4 nm G/D underlap for three cases of trap distribution: (a) no traps, (b) uniform, and (c) Gaussian.
HJ-TFET. The gate voltage noise spectral density is directly dependent on Sid and inversely dependent on the square of transconductance (gm) [16]. The inverted peaks in input-referred noise spectral density in HJ-TFET at 1 MHz is due to the presence of a notch-like feature in the plot of Sid versus VGS shown in Fig. 6. The plots of transconductance in Fig. 7 show an increasing trend as gate voltage increases. At 10 GHz too, at low voltage a notch can be observed, but it is not significant as compared to that at 1 MHz.
4.3.2. Flicker G-R electron noise voltage spectral density (SvgeeFLICKG-R) The most realistic consideration of flicker noise is the additive effect of the various generation–recombination noises produced by subbands of impurities or defects, or mobility fluctuations [26]. Since BTBT generation is the prime mechanism by which TFETs operate, this paper considers flicker noise caused by generation–recombination of carriers. It has been observed in Fig. 8 that the HJ TFET has better noise characteristics for both 1 MHz and 10 GHz for a low range of voltage. After that, noise in HJ TFET dominates the CG TFET at both the frequencies.
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Fig. 9. Comparison of diffusion electron noise voltage spectral density versus VGS between CG-TFET and HJ-TFET at 1 MHz and 10 GHz, and 4 nm G/D underlap for Gaussian trap distribution.
Fig. 10. Comparison of generation–recombination electron noise voltage spectral density versus VGS between CG-TFET and HJ-TFET at 1 MHz and 10 GHz, and 4 nm G/D underlap for Gaussian trap distribution.
4.3.3. Diffusion electron noise voltage spectral density (SvgeeDIFF) Diffusion component of the channel current gives rise to diffusion noise. The lateral electric field in TFET causes the band to band tunneling generated carrier near the source to diffuse through the channel toward the drain [27]. The diffusion current is proportional to mobility of electrons. The diffusion noise is widely used for modeling in a subthreshold region, but it has never been used for devices in strong inversion. TFET actually works in weak inversion. It has been observed in Fig. 9 that at high frequency, the diffusion noise component is more pronounced as compared to flicker. Moreover, with the increasing gate voltage, HJ-TFET has more diffusion noise compared to CG-TFET. In case of TFETs, the ID VGS characteristics are diffusion-limited at higher gate voltages when the values of drain current start to saturate [27]. In this paper, the devices have been considered at low voltages, the maximum value of VGS being 1 V. The effect of diffusion current on Svg at high frequency is dramatic. Svg increases with VGS because drain current increases with VGS. 4.3.4. Generation–recombination electron noise voltage spectral density (SvgeeG-R) The plot of electron voltage spectral density due to generation–recombination versus gate voltage is shown in Fig. 10. From an overall perspective, CG-TFET depicts lower noise than HJ-TFET. Generation–recombination noise is due to the fluctuations of number of carriers in the channel; in TFETs, the carriers are determined by Band-to-Band generation rate. The location of traps at the tunnel junction affects the generation–recombination process in TFET, mostly governed by BTBT. Electrons possessing energy close to the quasi Fermi level undergo trapping and de-trapping at the Si/SiO2 interface [17]. This causes changes in the junction electric field, which in turn, affects the generation–recombination rate, because the generation–recombination, G has a dependence on electric field, E given by [21,28]
jEj2 E1:5 G¼A exp B G EG jEj
! ð6Þ
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Fig. 11. Band-to-Band generation rate in (a) CG-TFET and (b) HJ-TFET, extracted from the simulator, in case of Gaussian trap distribution for gate–drain underlap of 4 nm at VDS = 0.5 V and VGS = 1 V.
Fig. 12. Drain current noise spectral density versus frequency of CG-TFET for gate–drain underlap of 4 nm at VDS = 0.5 V, and drain current 1 lA/lm in presence of uniform traps.
where A and B are constants, and EG is the band gap of the semiconductor. The contour plot of Band-to-Band (BTB) generation rate in CG-TFET and HJ-TFET extracted from TCAD simulator are shown in Fig. 11(a) and (b) respectively. The BTB generation rate in both the devices is concentrated around the source-channel tunnel junction where the tunneling occurs. The maximum value of BTB Generation rate in CG-FET is lesser than that in HJ-TFET when considering Gaussian traps. Moreover, the BTB Generation spreads over a larger area in HJ-TFET than in CG-TFET. This is because the HJ-TFET has low bandgap material, Si0.5Ge0.5 at the tunnel junction, thus increasing the tunneling probability.
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Fig. 13. Cut-off frequency as a function of VGS for CG-TFET in case of 4 nm G/D underlap in presence of Gaussian trap distribution.
Fig. 14. Total gate capacitance (CGG) versus VGS plots of CG-TFET for three drain voltage (VDS), 0.1 V, 0.3 V and 0.5 V at 4 nm gate–drain underlap length, at 1 MHz and 10 GHz for Gaussian trap distribution.
4.4. Variation of drain current noise spectral density versus frequency The variation of drain current noise spectral density with frequency for both the devices in presence of uniform traps is shown in Fig. 12. HJ-TFET shows higher drain current noise than CG-TFET at all frequencies. The drain current noise negligibly decreases in the lower frequencies from 10 Hz to 1 MHz; however, after 1 MHz, the curves attain a descending slope. After 100 MHz, the values of the current noise spectral density in HJ-TFET are of the same order of magnitude, whereas in CG-TFET, there is a slight change of slope at 1 GHz. Up to 1 MHz, the current noise spectral density is the result of contribution of generation–recombination noise, and flicker noise caused due to generation–recombination as observed from the plots of gate voltage noise spectral density. Beyond 1 MHz, the noise current spectral density is mainly dominated by flicker noise, as evident from the slope of the plot. At higher frequencies, diffusion noise dominates as observed in the plot of input-referred noise; the plot of noise spectral density in HJ-TFET follows a negligible change with frequency whereas, in CG-TFET, the values reduce considerably. 4.5. Cut-off frequency of CG-TFET The cut-off frequency of CG-TFET increases with VGS. The cut-off frequency (fT) depends on the ratio of gm (transconductance) and CGG (gate-to-gate capacitance) given by
fT ¼
gm 2pC GG
ð7Þ
Plotted in Fig. 13, up to a gate voltage of 0.65 V, the cut-off frequency increases, after which the values tend to saturate. This is explained with the help of Fig. 14. The plot of CGG for gate–drain underlap of 4 nm attains a rising trend at around 0.65 V. For values above 0.65 V, CGG in Eq. (5) increases by a greater factor than the numerator. However, there is an overall increasing nature of cut-off frequency as a function of VGS. The gate–drain underlap of 4 nm in CG-TFET has contributed to
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reduced gate–drain capacitance (CGD), thus lowering the value of CGG as compared to the case where there is no underlap [28]. This has enhanced the cut-off frequency of the device. In TFETs, CGD is the dominant capacitance which causes overshoot in transient response of digital inverter circuit. Reduction of CGD is necessary to prevent the undesired overshoot. The lowering of CGD and hence CGG in CG-TFET has made the cut-off frequency of Fig. 13 vary in a similar manner as that in MOSFET [29]. 5. Conclusion The proposed CG-TFET is less prone to noise as compared to HJ-TFET as observed in case of various trap distributions. At high frequency, the drain current noise spectral density is reduced, and decreases with frequency, unlike HJ-TFET. The diffusion noise component of the gate voltage noise spectral density is dominant at high frequency, whereas the generation– recombination noise contributes more at low frequency. The use of gate–drain underlap improves the cut-off frequency of the CG-TFET in presence of Gaussian traps and makes it suitable for digital applications as well as low noise analog RF design at low supply voltage. The effect of interface traps on transfer characteristics of CG-TFET is, however, more significant as compared to HJ-TFET owing to the circular structure of the gate. Acknowledgement The authors would like to acknowledge the Microelectronics Computational Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology Silchar for providing all the facilities for carrying out the work. References [1] S. Sarangi, S. Bhushan, A. Santra, S. Dubey, S. Jit, P.K. Tiwari, A rigorous simulation based study of gate misalignment effects in gate engineered doublegate (DG) MOSFETs, Superlattices Microstruct. 60 (2013) 263–279, http://dx.doi.org/10.1016/j.spmi.2013.05.009. [2] S.O. Koswatta, M.S. Lundstrom, D.E. Nikonov, Performance comparison between p–i–n tunneling transistors and conventional MOSFETs, IEEE Trans. Electron Devices 56 (2009) 456–465, http://dx.doi.org/10.1109/TED.2008.2011934. [3] W.Y. Choi, B.G. Park, J.D. Lee, T.J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Device Lett. 28 (2007) 743–745, http://dx.doi.org/10.1109/LED.2007.901273. [4] C. Le Royer, F. Mayer, Exhaustive experimental study of tunnel field effect transistors (TFETs): from materials to architecture, in: Proc. 10th Int. Conf. Ultim. Integr. Silicon, ULIS 2009 (2009), pp. 53–56, doi: 10.1109/ULIS.2009.4897537. [5] S. Banerjee, W. Richardson, J. Coleman, a. Chatterjee, A new three-terminal tunnel device, IEEE Electron Device Lett. 8 (1987) 347–349, http:// dx.doi.org/10.1109/EDL.1987.26655. [6] K.K. Bhuwalka, J. Schulze, I. Eisele, Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering, IEEE Trans. Electron Devices 52 (2005) 909–917, http://dx.doi.org/10.1109/TED.2005.846318. [7] K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-k gate dielectric, IEEE Trans. Electron Devices 54 (2007) 1725–1733, http://dx.doi.org/ 10.1109/TED.2007.899389. [8] K. Boucart, A.M. Ionescu, Double gate tunnel FET with ultrathin silicon body and high-K gate dielectric, in: Proceedings of the 36th European Solid-State Device Research Conference, ESSDER 2006 (2006) pp. 383–386, doi: 10.1109/ESSDER.2006.307718. [9] A. Biswas, S.S. Dan, C. Le Royer, W. Grabinski, A.M. Ionescu, TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model, Microelectron. Eng. 98 (2012) 334–337, http://dx.doi.org/10.1016/j.mee.2012.07.077. [10] A. Guo, P. Matheu, T.J.K. Liu, SOI TFET ION/IOFF enhancement via back biasing, IEEE Trans. Electron Devices 58 (2011) 3283–3285, http://dx.doi.org/ 10.1109/TED.2011.2161480. [11] J. Wan, C. Le Royer, A. Zaslavsky, S. Cristoloveanu, Tunneling FETs on SOI: suppression of ambipolar leakage low-frequency noise behavior, and modeling, Solid State Electron. 65–66 (2011) 226–233, http://dx.doi.org/10.1016/j.sse.2011.06.012. [12] S. Chander, B. Bhowmick, S. Baishya, Heterojunction fully depleted SOI-TFET with oxide/source overlap, Superlattices Microstruct. 86 (2015) 43–50, http://dx.doi.org/10.1016/j.spmi.2015.07.030. [13] W.Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field-effect transistors, IEEE Trans. Electron Devices 57 (2010) 2317–2319, http://dx.doi.org/ 10.1109/TED.2010.2052167. [14] S. Saurabh, M.J. Kumar, Novel attributes of a dual material gate nanoscale tunnel field-effect transistor, IEEE Trans. Electron Devices 58 (2011) 404– 410, http://dx.doi.org/10.1109/TED.2010.2093142. [15] M. Luisier, G. Klimeck, Investigation of InxGa1xAs ultra-thin-body tunneling FETs using a full-band and atomistic approach, in: International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2009 (2009) pp. 1–4, doi: 10.1109/SISPAD.2009.5290248. [16] R. Pandey, B. Rajamohanan, H. Liu, V. Narayanan, S. Datta, Electrical noise in heterojunction interband tunnel FETs, IEEE Trans. Electron Devices 61 (2014) 552–560, http://dx.doi.org/10.1109/TED.2013.2293497. [17] Q. Huang, R. Huang, C. Chen, C. Wu, J. Wang, C. Wang, et al., Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering s c, in: 2014 Symposium on VLSI Technology: Digest of Technical Papers (2014) pp.1–2, doi: 10.1109/VLSIT.2014.6894371. [18] R. Bijesh, D.K. Mohata, H. Liu, S. Datta, Flicker noise characterization and analytical modeling of homo and hetero-junction III–V tunnel FETs, Device Res. Conf. – Conf. Dig. DRC 37 (2012) 203–204, http://dx.doi.org/10.1109/DRC.2012.6257032. [19] A.P. Van Der Wel, E.aM. Klumperink, J.S. Kolhatkar, E. Hoekstra, M.F. Snoeij, C. Salm, et al, Low-frequency noise phenomena in switched MOSFETs, IEEE J. Solid-State Circuits 42 (2007) 540–549, http://dx.doi.org/10.1109/JSSC.2006.891714. [20] F.N. Hooge, 1/F noise sources, IEEE Trans. Electron Devices 41 (1994) 1926–1935, http://dx.doi.org/10.1109/16.333808. [21] J. Xu, J. Deen, MOSFET 1/F noise model based on mobility fluctuation in linear region, Electron. Lett. 38 (2002) 429–431, http://dx.doi.org/10.1049/ el:20020282. [22] Sentaurus Device User, Synopsys, (2009) 2009. [23] W. Wang, J. Hwang, Y. Xuan, P.D. Ye, Analysis of electron mobility in inversion-mode MOSFETs, IEEE Trans. Electron Devices 58 (2011) 1972–1978, http://dx.doi.org/10.1109/TED.2011.2146255. [24] Hraziia, A. Vladimirescu, A. Amara, C. Anghel, An analysis on the ambipolar current in Si double-gate tunnel FETs, Solid-State Electron. 70 (2012) 67– 72, http://dx.doi.org/10.1016/j.sse.2011.11.009. [25] A.S. Verhulst, W.G. Vandenberghe, K. Maex, G. Groeseneken, Tunnel field-effect transistor without gate–drain overlap, Appl. Phys. Lett. 91 (2007), http://dx.doi.org/10.1063/1.2757593.
354
R. Goswami et al. / Superlattices and Microstructures 86 (2015) 342–354
[26] J.P. Nougier, Fluctuations and noise of hot carriers in semiconductor materials and devices, IEEE Trans. Electron Devices 41 (1994) 2034–2049, http:// dx.doi.org/10.1109/16.333821. [27] S. Mookerjea, D. Mohata, Temperature-dependent-characteristics of a vertical tunnel FET, Device Lett. IEEE 31 (2010) 564–566.