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Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
Microelectronic Engineering 215 (2019) 111005
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Research paper
Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
T
⁎
Renan Trevisolia, , Rodrigo Trevisoli Doriab, Sylvain Barraudc, Marcelo Antonio Pavanellob CECS – Universidade Federal do ABC, Avenida dos Estados, 5001, CEP 09210-580 Santo André, Brazil Department of Electrical Engineering, Centro Universitário FEI, Av. Humberto de Alencar Castelo Branco, 3972, CEP 09850-901 Sao Bernardo do Campo, Brazil c University of Grenoble Alpes, CEA, LETI, Minatec Campus, 38054 Grenoble, France a
b
A R T I C LE I N FO
A B S T R A C T
Keywords: Junctionless nanowire transistors Low-frequency noise Interface trap density Semi-analytical model
The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the traprelated noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability.
1. Introduction Multiple gate devices have recently been adopted by the industry for the sub-14 nm technological nodes [1] owing to the better electrostatic control of the channel charges by the gate, which reduces the shortchannel effects (SCEs) occurrence [2]. However, the formation of the drain and source regions may be a cumbersome task due to the conditions necessary to avoid dopants diffusion into the channel [3]. To simplify the fabrication process, devices with a heavy constant doping concentration, so called Junctionless Nanowire Transistors (JNTs), have been proposed [3,4]. These devices have also shown some advantages as lower SCEs influence [5] and reduced low frequency noise (LFN) [6] in relation to their inversion-mode counterparts. LFN is a key parameter in analog circuits since it can limit the circuit performance. Also, low frequency noise techniques have been used for the analysis of the gate dielectric quality of JNTs by several works [6–10]. However, to the best of our knowledge, no mathematical correlation between the trap density in triple-gate JNTs and low-frequency noise, considering that these devices operate differently from inversion mode transistors, has been performed so far. Junctionless transistors and inversion mode devices present different conduction mechanisms such that the interface trap contribution to LFN is expected to be different. The former works mainly in the partial depletion condition and can be also used with the formation of an accumulation layer, whereas in the latter the current flows through an inversion layer [5]. When
⁎
Corresponding author. E-mail address: [email protected] (R. Trevisoli).
https://doi.org/10.1016/j.mee.2019.111005 Received 15 April 2019; Accepted 20 May 2019 Available online 22 May 2019 0167-9317/ © 2019 Elsevier B.V. All rights reserved.
operating only with bulk conduction (partial depletion), the surface potential (ΦS) may be distant from the conduction band edge, reducing the occupied trap density and, therefore, its correlated noise. When the device is in accumulation, ΦS approaches the conduction band edge, increasing the occupied trap density. Therefore, the aim of this work is to propose an analytical model for the estimation of the trap density-related low-frequency noise. The work is based on a surface-potential based drain current model, which has been modified to include the trap density influence on the static behavior. The modeled results are compared to both simulated and experimental devices aiming to demonstrate the effectiveness of the proposed methodology. Section 2 describes the analytical model, whereas Section 3 presents the comparison to the simulated data. In Section 4 the analysis of experimental devices are shown and, finally, Section 5 presents the conclusions of this work. 2. Analytical model basis The proposed model is based on the surface potential-based drain current (ID) model for triple gate JNTs described in [11], which includes the influence of short-channel effects. According to [11], the surface potential can be obtained by the sum of two potentials related to the depletion condition (ΦS,depl) and to the accumulation layer regime (ΦS,acc):
ΦS = ΦS, depl + ΦS, acc
(1)
Microelectronic Engineering 215 (2019) 111005
R. Trevisoli, et al.
ΦS, depl = VG2 − VFB + Vy − α /2 +
(α /2)2 − α (VG3 − VFB )
ΦS, acc = ϕt ln[1 + (VG − VG2 )2 /(αϕt )]
(2) (3)
where α = εSi q ND (2H + W) /CoxW , VG2 and VG3 are used to control the transitions to accumulation and off-state regimes, VFB is the flatband voltage, Vy represents the potential either at the source or at the drain, ϕt is the thermal voltage, CoxW is the gate dielectric capacitance per unit of length, W and H are the nanowire width and height, respectively, ND is the doping concentration, εSi and q have their usual meaning. To include the trap density influence on the static drain current of triple gate JNTs, a modification is proposed in [12] to the model of [11] through the sum of an occupied trap density-related voltage (VIT) to the flatband voltage in the surface potential calculation. It is worth noting that VG2 also depends on the flatband voltage and, therefore, is altered by VIT. To obtain VIT, the occupied traps equations, which are dependent on the interface traps energetic distribution, are solved self consistently with the surface potential calculation [12]. The occupied trap density-related voltage is given by VIT = QIT/Cox, where QIT is the occupied trap density and Cox is the gate dielectric capacitance per unit of area. For the modification proposed in [12], the traps below the surface energy level (E) were considered as occupied ones whereas above it they were considered as empty ones. The occupied trap density is obtained by integrating the total interface trap density from the valence band edge energy (EV) up to the surface energy. In the case of the traps distribution in discrete levels, which is the case in this work, Eq. (4) is used for the occupied trap density calculation. In this case, Nn is the trap concentration at each energy level and f0(E) is the probability of occupation (Fermi-Dirac distribution) given by Eq. (5) [13], where ET is the energy of each trap level and g is the degeneracy factor, which has been considered as 1 [14]. 2
2
QIT = q ∑ Nn f0 (E ) f0 (E ) =
Fig. 1. Drain current in linear and logarithmic scales as a function of the gate voltage for devices with different trap configurations comparing simulated and modeled results.
It is worth noting that both the electron density and the transconductance are obtained through the analytical model of [11], including the traps influence following [12], which is solved numerically.
SId = SVg gm 2
3. Simulated results For the analysis of the model capability in describing triple gate JNTs low frequency noise, 3D numerical simulations have been performed using Synopsys tools considering the impedance field method [17]. The simulated devices present nanowire width and height of 10 nm, doping concentration of 1019 cm−3 and gate oxide thickness of 1.3 nm. Devices of two channel lengths (30 and 100 nm) were considered. In Fig. 1, the drain current for a device with L = 100 nm is presented as a function of the gate voltage (VGS) comparing simulations and analytical model considering and neglecting the traps influence. When considering interface traps, the parameter ΔE represents the distance of a discrete trap level from the minimum of the conduction band. When ΔE is increased (trap level deep inside the bandgap), the influence of the interface traps occurs for lower VGS. From the Fig. 1, it can be noted that the traps influence on the static behavior of the simulated devices has been adequately considered. In Fig. 2, the current noise spectral density is shown versus the frequency (f) for different gate overdrive voltages (VGT = VGS – VT, where VT is the threshold voltage) and ΔE. The modeled results have demonstrated an excellent agreement with the simulated ones. In Fig. 3 (top), SID is presented as a function of the frequency for different ΔE for a fixed gate overdrive voltage, whereas the influence of different drain biases is exhibited in Fig. 3 (bottom). The current noise spectral density has shown to increase with the drain bias, due to the drain current increase. The modeled results have demonstrated a good agreement with the simulated results for any bias condition and ΔE. In Figs. 1–3, long channel Junctionless Nanowire Transistors have been considered. To extend the analysis of the proposed model, short channel triple-gate JNTs with L = 30 nm have also been simulated. In Fig. 4, the drain current for the device with L = 30 nm is presented comparing the analytical model and the simulated results. Similarly to the longer devices, when ΔE is increased (deeper trap levels), the influence of the interface traps starts to occur for lower gate voltages. The results of Fig. 4 demonstrate that the traps influence on the static behavior of these shorter devices is also adequately reproduced. The analysis of the drain current noise spectral density for these shorter devices is shown in Fig. 5, where SID is exhibited as a function of the frequency for different gate overdrives voltages, considering two
(4)
1 . 1 + g exp[(ET − E )/ kT ]
(5)
For the low frequency noise calculation, the traps have been considered as distributed in discrete levels, such that the total drain current noise spectral density is obtained through the sum of the noise of each trap level [15]. The drain current is firstly calculated for fixed gate and drain biases, considering the traps influence on the static behavior following [11,12], which requires the numerical solution of Eqs. (1)–(5). Next, the potential variation induced by changing a single charge at the gate electrode (ΔV = q/CG, where CG is the gate capacitance) is used to obtain the gate voltage noise spectral density (SVg) through
SVg = nNit ∆V 2f0 (E ) (1 − f0 (E ))
4τ (E ) 1 + (2πfτ (E ))2
(6)
where nNit is the number of traps for a specific energy level (obtained through the integral of the interface trap density at an energy level in the gate interface area) and τ(Ε) is the mean time constant for a change in the traps occupation [15]. τ(E) is obtained through 1/τ(E) = 1/ τc(E) + 1/τe(E), where τc(E) and τe(E) are the capture and emission times, obtained by the SRH statistics [16]:
τc (E ) =
1 σ vth n
(7)
τe (E ) =
τc (E ) ⎛− ETkT− E ⎞ ⎠ e⎝ g
(8)
(9)
where σ is the trap cross section, vth is the mean thermal velocity and n the electron density. The gate voltage noise spectral density calculated from (6) is related to a trap in a discrete level. The total noise is obtained by the sum of the noise of every trap level. After SVg, the drain current noise spectral density (SID) can be obtained by (9), where gm is the transconductance. 2
Microelectronic Engineering 215 (2019) 111005
R. Trevisoli, et al.
Fig. 2. Current noise spectral density (SID) as a function of the frequency for a JNT at different gate ovedrive voltages considering (top) ΔE = 0 (bottom) ΔE = 0.1 eV.
Fig. 5. Current noise spectral density as a function of the frequency for a shortchannel JNT at different gate ovedrive voltages considering (top) ΔE = 0 (bottom) ΔE = 0.1 eV.
4. Experimental devices In this section, the modeled results have been compared to the experimental data of [18] to demonstrate the model applicability. The devices were fabricated in CEA-Leti following [19] and present nanowire height of 9 nm, effective oxide thickness of 1.5 nm, channel length of 100 nm and doping concentration of 5 × 1018 cm−3. The measurement was performed for a drain bias of 50 mV and different substrate biases (VBS). In Fig. 6(top), the drain current is presented as a function of the gate voltage for different substrate biases, demonstrating that the drain current model has been adequately calibrated. The drain current noise spectral density is presented in Fig. 6(bottom) comparing the proposed model with experimental data. An excellent agreement for the low frequency noise can be observed. It is worth noting that when considering a single trap level with a fixed cross section, the noise spectral density presents a constant value up to a corner frequency and, then, decreases by a 1/f 2 rate. As it can be observed in Fig. 6, the noise of the experimental devices follows a 1/f rate, which can be obtained by the sum of several traps with different corner frequencies [15]. In the proposed model, the corner frequencies
Fig. 3. Current noise spectral density as a function of the frequency for a JNT considering the traps at different ΔE (top) and for different VDS (bottom).
Fig. 4. Drain current as a function of the gate voltage for short-channel devices with different trap configurations comparing simulated and modeled results.
values of ΔE. Once more, an excellent agreement can be observed. By comparing the results in Fig. 5 to the ones in Fig. 2, it can be observed that the noise spectral density increases for the shorter devices, as expected.
Fig. 6. Drain current as a function of the gate voltage (top) and SId as a function of the frequency (bottom) comparing experimental data of [18] and the analytical model. 3
Microelectronic Engineering 215 (2019) 111005
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Acknowledgements This work was partially supported by the Brazilian Funding Agencies CAPES, CNPq and São Paulo Research Foundation (FAPESP, grant #2014/18041-8). References [1] http://newsroom.intel.com/docs/DOC-5677. [2] J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008, p. 340p. [3] J.-P. Colinge, C.W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, R. Murphy, Nanowire transistors without junctions, Nat. Nanotechnol. 5 (2010) 225–229. [4] J.-P. Colinge, C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, R. Murphy, SOI gated resistor: CMOS without junctions, Proceedings of IEEE International SOI Conference, 2009, pp. 1–2. [5] C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, J.-P. Colinge, Junctionless multigate field-effect transistor, Appl. Phys. Lett. 94 (2009) 053 511. [6] P. Singh, N. Singh, J. Miao, W.-T. Park, D.-L. Kwong, Gate-all-around Junctionless nanowire MOSFET with improved low-frequency noise behavior, IEEE Electron Device Lett. 32 (2011) 1752–1754. [7] R.T. Doria, R.D. Trevisoli, M. de Souza, M.A. Pavanello, Trap density characterization through low-frequency noise in Junctionless transistors, Microelectron. Eng. 109 (2013) 79–82. [8] R.T. Doria, R. Trevisoli, M. de Souza, M.A. Pavanello, Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors, Solid State Electron. 96 (2014) 22–26. [9] D.-Y. Jeon, S.J. Park, M. Mouis, S. Barraud, G.-T. Kim, G. Ghibaudo, Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors, Solid State Electron. 81 (2013) 101–104. [10] D. Jang, J.W. Lee, C.-W. Lee, J.-P. Colinge, L. Montès, J.I. Lee, G.T. Kim, G. Ghibaudo, Low-frequency noise in junctionless multigate transistors, Appl. Phys. Lett. 98 (2011) 133 502. [11] R. Trevisoli, R.T. Doria, M. de Souza, S. Das, I. Ferain, M.A. Pavanello, IEEE Transactions on Electron Devices, “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors”, vol. 59, (2012), pp. 3510–3518. [12] R. Trevisoli, R.T. Doria, M. de Souza, M.A. Pavanello, Modeling the interface trap density influence on junctionless nanowire transistors behavior, Proceedings of IEEE International SOI Conference, 2018. [13] E.H. Nicollian, J.R. Brews, MOS Physics and Technology, (1982). [14] M. Haartman, M. Östling, Low-Frequency Noise in Advanced MOS Devices, Springer, 2007. [15] G.I. Wirth, J. Koh, R. da Silva, R. Thewes, R. Brederlow, Modeling of statistical lowfrequency noise of deep-submicrometer MOSFETs, IEEE Trans. Electron Devices 52 (2005) 1576–1588. [16] W. Shockley, W.T. Read Jr., Statistics of the recombinations of holes and electrons, Phys. Rev. 87 (1952) 835–842. [17] Sentaurus Device User Guide, Synopsys, (2016). [18] R.T. Doria, R. Trevisoli, M. de de Souza, S. Barraud, M. Vinet, O. Faynot, M.A. Pavanello, Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization, Microelectron. Eng. 178 (2017) 17–20. [19] S. Barraud, M. Berthomé, R. Coquand, M. Cassé, T. Ernst, M.-P. Samson, P. Perreau, K.K. Bourdelle, O. Faynot, T. Poiroux, Scaling of Trigate Junctionless nanowire MOSFET with gate length down to 13 nm, IEEE Electron Device Lett. 33 (2012) 1225–1227.
Fig. 7. Drain current noise spectral density normalized by the squared drain current as a function of the frequency for the modeled devices.
can be adjusted by the trap cross section in the capture time term. To fit the experimental results, three trap densities (2 × 1012, 1 × 1012, 0.5 × 1012 cm−2) were considered with ΔE = 0, i.e. close to the conduction band minimum, with different cross-sections (2 × 10−24, 0.1 × 10−24 and 0.6 × 10−25 cm2). The first trap level was defined near 1 kHz due to the change in the LFN slope from ~1/f to ~1/f 2. The other two levels were defined for lower frequencies to obtain a ~1/f slope in this region. Finally, in Fig. 7, the normalized SId is exhibited as a function of the frequency for the modeled data. The modeled normalized SId follows the same trends shown in [18], worsening for lower VBS. Therefore, the proposed model successfully reproduces the behavior of experimental transistors. 5. Conclusions This work has proposed an analytical model for the trap-related low frequency noise in triple-gate Junctionless Nanowire Transistors. The model has been validated with simulated results considering devices with different channel lengths at several biases conditions. Different positions of the trap levels in the bandgap have been considered. For all conditions, an excellent agreement between the model and the simulated values could be observed. It has also been demonstrated that the proposed model could adequately reproduce the 1/f behavior of the experimental devices noise spectral density for different bias conditions, including variation in the substrate bias.
4
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Research paper
Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
T
⁎
Renan Trevisolia, , Rodrigo Trevisoli Doriab, Sylvain Barraudc, Marcelo Antonio Pavanellob CECS – Universidade Federal do ABC, Avenida dos Estados, 5001, CEP 09210-580 Santo André, Brazil Department of Electrical Engineering, Centro Universitário FEI, Av. Humberto de Alencar Castelo Branco, 3972, CEP 09850-901 Sao Bernardo do Campo, Brazil c University of Grenoble Alpes, CEA, LETI, Minatec Campus, 38054 Grenoble, France a
b
A R T I C LE I N FO
A B S T R A C T
Keywords: Junctionless nanowire transistors Low-frequency noise Interface trap density Semi-analytical model
The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the traprelated noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability.
1. Introduction Multiple gate devices have recently been adopted by the industry for the sub-14 nm technological nodes [1] owing to the better electrostatic control of the channel charges by the gate, which reduces the shortchannel effects (SCEs) occurrence [2]. However, the formation of the drain and source regions may be a cumbersome task due to the conditions necessary to avoid dopants diffusion into the channel [3]. To simplify the fabrication process, devices with a heavy constant doping concentration, so called Junctionless Nanowire Transistors (JNTs), have been proposed [3,4]. These devices have also shown some advantages as lower SCEs influence [5] and reduced low frequency noise (LFN) [6] in relation to their inversion-mode counterparts. LFN is a key parameter in analog circuits since it can limit the circuit performance. Also, low frequency noise techniques have been used for the analysis of the gate dielectric quality of JNTs by several works [6–10]. However, to the best of our knowledge, no mathematical correlation between the trap density in triple-gate JNTs and low-frequency noise, considering that these devices operate differently from inversion mode transistors, has been performed so far. Junctionless transistors and inversion mode devices present different conduction mechanisms such that the interface trap contribution to LFN is expected to be different. The former works mainly in the partial depletion condition and can be also used with the formation of an accumulation layer, whereas in the latter the current flows through an inversion layer [5]. When
⁎
Corresponding author. E-mail address: [email protected] (R. Trevisoli).
https://doi.org/10.1016/j.mee.2019.111005 Received 15 April 2019; Accepted 20 May 2019 Available online 22 May 2019 0167-9317/ © 2019 Elsevier B.V. All rights reserved.
operating only with bulk conduction (partial depletion), the surface potential (ΦS) may be distant from the conduction band edge, reducing the occupied trap density and, therefore, its correlated noise. When the device is in accumulation, ΦS approaches the conduction band edge, increasing the occupied trap density. Therefore, the aim of this work is to propose an analytical model for the estimation of the trap density-related low-frequency noise. The work is based on a surface-potential based drain current model, which has been modified to include the trap density influence on the static behavior. The modeled results are compared to both simulated and experimental devices aiming to demonstrate the effectiveness of the proposed methodology. Section 2 describes the analytical model, whereas Section 3 presents the comparison to the simulated data. In Section 4 the analysis of experimental devices are shown and, finally, Section 5 presents the conclusions of this work. 2. Analytical model basis The proposed model is based on the surface potential-based drain current (ID) model for triple gate JNTs described in [11], which includes the influence of short-channel effects. According to [11], the surface potential can be obtained by the sum of two potentials related to the depletion condition (ΦS,depl) and to the accumulation layer regime (ΦS,acc):
ΦS = ΦS, depl + ΦS, acc
(1)
Microelectronic Engineering 215 (2019) 111005
R. Trevisoli, et al.
ΦS, depl = VG2 − VFB + Vy − α /2 +
(α /2)2 − α (VG3 − VFB )
ΦS, acc = ϕt ln[1 + (VG − VG2 )2 /(αϕt )]
(2) (3)
where α = εSi q ND (2H + W) /CoxW , VG2 and VG3 are used to control the transitions to accumulation and off-state regimes, VFB is the flatband voltage, Vy represents the potential either at the source or at the drain, ϕt is the thermal voltage, CoxW is the gate dielectric capacitance per unit of length, W and H are the nanowire width and height, respectively, ND is the doping concentration, εSi and q have their usual meaning. To include the trap density influence on the static drain current of triple gate JNTs, a modification is proposed in [12] to the model of [11] through the sum of an occupied trap density-related voltage (VIT) to the flatband voltage in the surface potential calculation. It is worth noting that VG2 also depends on the flatband voltage and, therefore, is altered by VIT. To obtain VIT, the occupied traps equations, which are dependent on the interface traps energetic distribution, are solved self consistently with the surface potential calculation [12]. The occupied trap density-related voltage is given by VIT = QIT/Cox, where QIT is the occupied trap density and Cox is the gate dielectric capacitance per unit of area. For the modification proposed in [12], the traps below the surface energy level (E) were considered as occupied ones whereas above it they were considered as empty ones. The occupied trap density is obtained by integrating the total interface trap density from the valence band edge energy (EV) up to the surface energy. In the case of the traps distribution in discrete levels, which is the case in this work, Eq. (4) is used for the occupied trap density calculation. In this case, Nn is the trap concentration at each energy level and f0(E) is the probability of occupation (Fermi-Dirac distribution) given by Eq. (5) [13], where ET is the energy of each trap level and g is the degeneracy factor, which has been considered as 1 [14]. 2
2
QIT = q ∑ Nn f0 (E ) f0 (E ) =
Fig. 1. Drain current in linear and logarithmic scales as a function of the gate voltage for devices with different trap configurations comparing simulated and modeled results.
It is worth noting that both the electron density and the transconductance are obtained through the analytical model of [11], including the traps influence following [12], which is solved numerically.
SId = SVg gm 2
3. Simulated results For the analysis of the model capability in describing triple gate JNTs low frequency noise, 3D numerical simulations have been performed using Synopsys tools considering the impedance field method [17]. The simulated devices present nanowire width and height of 10 nm, doping concentration of 1019 cm−3 and gate oxide thickness of 1.3 nm. Devices of two channel lengths (30 and 100 nm) were considered. In Fig. 1, the drain current for a device with L = 100 nm is presented as a function of the gate voltage (VGS) comparing simulations and analytical model considering and neglecting the traps influence. When considering interface traps, the parameter ΔE represents the distance of a discrete trap level from the minimum of the conduction band. When ΔE is increased (trap level deep inside the bandgap), the influence of the interface traps occurs for lower VGS. From the Fig. 1, it can be noted that the traps influence on the static behavior of the simulated devices has been adequately considered. In Fig. 2, the current noise spectral density is shown versus the frequency (f) for different gate overdrive voltages (VGT = VGS – VT, where VT is the threshold voltage) and ΔE. The modeled results have demonstrated an excellent agreement with the simulated ones. In Fig. 3 (top), SID is presented as a function of the frequency for different ΔE for a fixed gate overdrive voltage, whereas the influence of different drain biases is exhibited in Fig. 3 (bottom). The current noise spectral density has shown to increase with the drain bias, due to the drain current increase. The modeled results have demonstrated a good agreement with the simulated results for any bias condition and ΔE. In Figs. 1–3, long channel Junctionless Nanowire Transistors have been considered. To extend the analysis of the proposed model, short channel triple-gate JNTs with L = 30 nm have also been simulated. In Fig. 4, the drain current for the device with L = 30 nm is presented comparing the analytical model and the simulated results. Similarly to the longer devices, when ΔE is increased (deeper trap levels), the influence of the interface traps starts to occur for lower gate voltages. The results of Fig. 4 demonstrate that the traps influence on the static behavior of these shorter devices is also adequately reproduced. The analysis of the drain current noise spectral density for these shorter devices is shown in Fig. 5, where SID is exhibited as a function of the frequency for different gate overdrives voltages, considering two
(4)
1 . 1 + g exp[(ET − E )/ kT ]
(5)
For the low frequency noise calculation, the traps have been considered as distributed in discrete levels, such that the total drain current noise spectral density is obtained through the sum of the noise of each trap level [15]. The drain current is firstly calculated for fixed gate and drain biases, considering the traps influence on the static behavior following [11,12], which requires the numerical solution of Eqs. (1)–(5). Next, the potential variation induced by changing a single charge at the gate electrode (ΔV = q/CG, where CG is the gate capacitance) is used to obtain the gate voltage noise spectral density (SVg) through
SVg = nNit ∆V 2f0 (E ) (1 − f0 (E ))
4τ (E ) 1 + (2πfτ (E ))2
(6)
where nNit is the number of traps for a specific energy level (obtained through the integral of the interface trap density at an energy level in the gate interface area) and τ(Ε) is the mean time constant for a change in the traps occupation [15]. τ(E) is obtained through 1/τ(E) = 1/ τc(E) + 1/τe(E), where τc(E) and τe(E) are the capture and emission times, obtained by the SRH statistics [16]:
τc (E ) =
1 σ vth n
(7)
τe (E ) =
τc (E ) ⎛− ETkT− E ⎞ ⎠ e⎝ g
(8)
(9)
where σ is the trap cross section, vth is the mean thermal velocity and n the electron density. The gate voltage noise spectral density calculated from (6) is related to a trap in a discrete level. The total noise is obtained by the sum of the noise of every trap level. After SVg, the drain current noise spectral density (SID) can be obtained by (9), where gm is the transconductance. 2
Microelectronic Engineering 215 (2019) 111005
R. Trevisoli, et al.
Fig. 2. Current noise spectral density (SID) as a function of the frequency for a JNT at different gate ovedrive voltages considering (top) ΔE = 0 (bottom) ΔE = 0.1 eV.
Fig. 5. Current noise spectral density as a function of the frequency for a shortchannel JNT at different gate ovedrive voltages considering (top) ΔE = 0 (bottom) ΔE = 0.1 eV.
4. Experimental devices In this section, the modeled results have been compared to the experimental data of [18] to demonstrate the model applicability. The devices were fabricated in CEA-Leti following [19] and present nanowire height of 9 nm, effective oxide thickness of 1.5 nm, channel length of 100 nm and doping concentration of 5 × 1018 cm−3. The measurement was performed for a drain bias of 50 mV and different substrate biases (VBS). In Fig. 6(top), the drain current is presented as a function of the gate voltage for different substrate biases, demonstrating that the drain current model has been adequately calibrated. The drain current noise spectral density is presented in Fig. 6(bottom) comparing the proposed model with experimental data. An excellent agreement for the low frequency noise can be observed. It is worth noting that when considering a single trap level with a fixed cross section, the noise spectral density presents a constant value up to a corner frequency and, then, decreases by a 1/f 2 rate. As it can be observed in Fig. 6, the noise of the experimental devices follows a 1/f rate, which can be obtained by the sum of several traps with different corner frequencies [15]. In the proposed model, the corner frequencies
Fig. 3. Current noise spectral density as a function of the frequency for a JNT considering the traps at different ΔE (top) and for different VDS (bottom).
Fig. 4. Drain current as a function of the gate voltage for short-channel devices with different trap configurations comparing simulated and modeled results.
values of ΔE. Once more, an excellent agreement can be observed. By comparing the results in Fig. 5 to the ones in Fig. 2, it can be observed that the noise spectral density increases for the shorter devices, as expected.
Fig. 6. Drain current as a function of the gate voltage (top) and SId as a function of the frequency (bottom) comparing experimental data of [18] and the analytical model. 3
Microelectronic Engineering 215 (2019) 111005
R. Trevisoli, et al.
Acknowledgements This work was partially supported by the Brazilian Funding Agencies CAPES, CNPq and São Paulo Research Foundation (FAPESP, grant #2014/18041-8). References [1] http://newsroom.intel.com/docs/DOC-5677. [2] J.-P. Colinge, FinFETs and Other Multi-Gate Transistors, Springer, 2008, p. 340p. [3] J.-P. Colinge, C.W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, R. Murphy, Nanowire transistors without junctions, Nat. Nanotechnol. 5 (2010) 225–229. [4] J.-P. Colinge, C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, R. Murphy, SOI gated resistor: CMOS without junctions, Proceedings of IEEE International SOI Conference, 2009, pp. 1–2. [5] C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, J.-P. Colinge, Junctionless multigate field-effect transistor, Appl. Phys. Lett. 94 (2009) 053 511. [6] P. Singh, N. Singh, J. Miao, W.-T. Park, D.-L. Kwong, Gate-all-around Junctionless nanowire MOSFET with improved low-frequency noise behavior, IEEE Electron Device Lett. 32 (2011) 1752–1754. [7] R.T. Doria, R.D. Trevisoli, M. de Souza, M.A. Pavanello, Trap density characterization through low-frequency noise in Junctionless transistors, Microelectron. Eng. 109 (2013) 79–82. [8] R.T. Doria, R. Trevisoli, M. de Souza, M.A. Pavanello, Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors, Solid State Electron. 96 (2014) 22–26. [9] D.-Y. Jeon, S.J. Park, M. Mouis, S. Barraud, G.-T. Kim, G. Ghibaudo, Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors, Solid State Electron. 81 (2013) 101–104. [10] D. Jang, J.W. Lee, C.-W. Lee, J.-P. Colinge, L. Montès, J.I. Lee, G.T. Kim, G. Ghibaudo, Low-frequency noise in junctionless multigate transistors, Appl. Phys. Lett. 98 (2011) 133 502. [11] R. Trevisoli, R.T. Doria, M. de Souza, S. Das, I. Ferain, M.A. Pavanello, IEEE Transactions on Electron Devices, “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors”, vol. 59, (2012), pp. 3510–3518. [12] R. Trevisoli, R.T. Doria, M. de Souza, M.A. Pavanello, Modeling the interface trap density influence on junctionless nanowire transistors behavior, Proceedings of IEEE International SOI Conference, 2018. [13] E.H. Nicollian, J.R. Brews, MOS Physics and Technology, (1982). [14] M. Haartman, M. Östling, Low-Frequency Noise in Advanced MOS Devices, Springer, 2007. [15] G.I. Wirth, J. Koh, R. da Silva, R. Thewes, R. Brederlow, Modeling of statistical lowfrequency noise of deep-submicrometer MOSFETs, IEEE Trans. Electron Devices 52 (2005) 1576–1588. [16] W. Shockley, W.T. Read Jr., Statistics of the recombinations of holes and electrons, Phys. Rev. 87 (1952) 835–842. [17] Sentaurus Device User Guide, Synopsys, (2016). [18] R.T. Doria, R. Trevisoli, M. de de Souza, S. Barraud, M. Vinet, O. Faynot, M.A. Pavanello, Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization, Microelectron. Eng. 178 (2017) 17–20. [19] S. Barraud, M. Berthomé, R. Coquand, M. Cassé, T. Ernst, M.-P. Samson, P. Perreau, K.K. Bourdelle, O. Faynot, T. Poiroux, Scaling of Trigate Junctionless nanowire MOSFET with gate length down to 13 nm, IEEE Electron Device Lett. 33 (2012) 1225–1227.
Fig. 7. Drain current noise spectral density normalized by the squared drain current as a function of the frequency for the modeled devices.
can be adjusted by the trap cross section in the capture time term. To fit the experimental results, three trap densities (2 × 1012, 1 × 1012, 0.5 × 1012 cm−2) were considered with ΔE = 0, i.e. close to the conduction band minimum, with different cross-sections (2 × 10−24, 0.1 × 10−24 and 0.6 × 10−25 cm2). The first trap level was defined near 1 kHz due to the change in the LFN slope from ~1/f to ~1/f 2. The other two levels were defined for lower frequencies to obtain a ~1/f slope in this region. Finally, in Fig. 7, the normalized SId is exhibited as a function of the frequency for the modeled data. The modeled normalized SId follows the same trends shown in [18], worsening for lower VBS. Therefore, the proposed model successfully reproduces the behavior of experimental transistors. 5. Conclusions This work has proposed an analytical model for the trap-related low frequency noise in triple-gate Junctionless Nanowire Transistors. The model has been validated with simulated results considering devices with different channel lengths at several biases conditions. Different positions of the trap levels in the bandgap have been considered. For all conditions, an excellent agreement between the model and the simulated values could be observed. It has also been demonstrated that the proposed model could adequately reproduce the 1/f behavior of the experimental devices noise spectral density for different bias conditions, including variation in the substrate bias.
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