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Noise modeling in fully depleted SOI MOSFETs
Solid-State Electronics 48 (2004) 813–825 www.elsevier.com/locate/sse
Noise modeling in fully depleted SOI MOSFETs G. Pailloncy
a,*
, B. Iniguez b, G. Dambrine a, J.-P. Raskin c, F. Danneville
a
a
Institut d’Electronique, de Microelectronique et de Nanotechnologie (IEMN), UMR CNRS 8520, Av. Poincare, BP 69, 59652 Villeneuve d’Ascq, France b Department of Electrical, Electronic and Automatic Engineering, Universitat Rovira i Virgili, Avinguda dels Paisos Catalans, 26 43007 Tarragona, Spain c Universite catholique de Louvain-la-Neuve (UCL), Maxwell Building, Place du Levant 3, B-1348 Louvain la Neuve, Belgium Received 18 December 2003; accepted 22 December 2003
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract In this paper, we are presenting a noise modeling technique in fully depleted (FD) SOI MOSFET. Starting from a physical compact model which allows us to capture the physics in such devices, an original microscopic noise model, suitable to calculate the noise performance of any field effect transistor, is developed. The method is applied to study the noise properties of FD SOI MOSFETs (0.25 lm physical gate length, 0.16 lm effective gate length); this includes a discussion at a microscopic level, the calculation of the usual P , R, C parameters (close to the device physics) and of the noise performances, taking into account extrinsic elements. To conclude, a discussion related to the noise performances as a function of the down-scaling is proposed. 2004 Elsevier Ltd. All rights reserved. Keywords: SOI; MOSFETs; High frequency noise; Active line
1. Introduction The use of low power, low noise devices for future telecommunication applications becomes more and more important. Especially, SOI devices are excellent candidates to become an alternative to conventional bulk CMOS, for they are presenting lower parasitic junction capacitance, higher drive current, higher transconductance, smaller short channel effects [1]. All of this makes their high frequency performances to be higher than for bulk CMOS, which is of primary importance for the development of future wireless telecommunication circuits. Though these devices present such good characteristics, their noise performance have
* Corresponding author. Tel.: +33-320-19-79-79; fax: +33320-19-78-92. E-mail address: [email protected] (G. Pailloncy).
not been studied intensively [2], unlike bulk CMOS [3– 5]. Thus, a rigorous microscopic approach allowing to calculate the overall noise correlation matrix of the transistor in any useful representation is necessary. In this paper, based on the active line method to take into account the distributed nature of the channel, we are calculating the high frequency noise performance of FD SOI MOSFETs. The first point required in order to develop a noise modeling is obviously to capture the physics, which has been carried out using a physical compact model developed by I~ niguez et al. [6]. In Section 3, starting from this physical model, the path allowing to define the local small signal equivalent circuit (SSEC) of the active line is presented. Taking into account the contributions of each section along the channel, one can define the elements which constitute the conventional p equivalent circuit of the FET. Then, special emphasis is made towards the way the microscopic noise sources distributed along the channel are defined, and an original method, developed to calculate
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.12.032
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
Nomenclature P R C NFmin Rn Copt Dc0 Dgm Dg0 hi2n i q leff W nðxÞ h cof Id a Dx Vth l0 Dr0 Drsat V ðxÞ vsat Leff Vds Vdsat ld cb cob Sin De S Qnf k Ta El Ec b xsat CHg Cag j x * CH0g Ca0g Ys Gm f Cgs
diffusion noise parameter related to hi2d i diffusion noise parameter related to hi2g i normalized correlation coefficient between hi2g i and hi2d i minimum noise figure equivalent noise resistance optimum reflexion coefficient local gate-to-channel capacitance local transconductance local channel conductance local diffusion noise source electron charge effective mobility channel width local inversion carrier density per unit area at position x mobility degradation parameter front oxide capacitance DC drain-to-source current body effect parameter section length thermal voltage zero-bias mobility local channel resistance contribution of the channel length modulation to the local resistance channel potential at position x saturation velocity effective channel length DC drain-to-source voltage saturation voltage characteristic length film capacitance back oxide capacitance noise spectral density local diffusion coefficient effective channel section charge density Boltzmann constant room temperature lateral electrical field critical lateral electrical field local diffusion coefficient parameter carrier velocity saturation channel position local equivalent chain matrix in common gate configuration local noise correlation matrix associated to CHg imaginary term pulsation conjugate of a complex equivalent chain matrix of the entire channel in common gate configuration noise correlation matrix associated to CH0g admittance matrix in common source configuration transconductance frequency gate-to-source capacitance
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
Cgd Ri s T t
hi2g i hi2d i hig id i Df Vgs CH0s Ca0s detð Þ jj R I gopt bopt Yopt fc fmax Vsg Is Vdg Ig CHs Cas Rgd Cds Gd Zs Rg Rs Rd Ls Zs0 CZs CZs0 Ys0 Cpg Cpd Ys00 CYs0 Zs00 Lg Ld Zs000 CZs00
815
gate-to-drain capacitance intrinsic resistance delay Time transform matrix transposed conjugate of matrix gate diffusion noise current source in short-circuit representation at input and output drain diffusion noise current source in short-circuit representation at input and output diffusion noise sources cross-correlation of hi2g i and hi2d i frequency bandwidth DC gate-to-source voltage equivalent chain matrix in common source configuration considering extrinsic elements noise correlation matrix associated to CH0s matrix determinant complex modulus real part of a complex imaginary part of a complex optimum noise conductance optimum noise susceptance optimum noise admittance intrinsic cut-off frequency maximum oscillation frequency DC source-to-gate voltage DC source current DC drain-to-gate voltage DC gate current chain matrix in common source configuration noise correlation matrix associated to CHs gate-to-drain resistance drain-to-source capacitance drain-to-source conductance equivalent impedance matrix of the entire channel in common source configuration gate access resistance source access resistance drain access resistance parasitic source inductance equivalent impedance matrix in common source configuration considering Rg , Rs , Rd and Ls noise correlation matrix associated to Zs noise correlation matrix associated to Zs0 equivalent admittance matrix calculated from Zs0 gate parasitic capacitance drain parasitic capacitance equivalent admittance matrix in common source configuration considering Rg , Rs , Rd , Ls , Cpg and Cpd noise correlation matrix associated to Ys00 equivalent impedance matrix calculated from Ys000 gate parasitic inductance drain parasitic inductance equivalent impedance matrix in common source configuration considering all the extrinsic elements noise correlation matrix associated to Zs000
the influence of all the microscopic noise sources at the device electrodes, is presented. In Section 4, the results obtained for several FD SOI MOSFETs are presented (long channels, 0.16 and 0.10 lm effective gate length devices). In a current–current
representation [7], the noise properties are studied in detail: it goes from the distribution of the noise sources to the bias dependency of the usual noise parameters such as P , R and C. Then the noise performance calculations of FD SOI MOSFET (in terms of NFmin , Rn and
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Copt ) are undertaken and compared with the experimental ones. To conclude, a discussion related to the down-scaling on SOI MOSFETs is proposed.
microscopic noise sources are defined, a noise modeling can be carried out. 2.1. Determination of the active line elements (Dc0 (x), Dgm (x), Dg0 (x)) and of hi2n (x)i
2. An original noise modeling method for FD SOI MOSFETs A complete modeling of the noise performance of a device requires calculating the small signal parameters and the associated two noise sources (completely defined by their spectral densities and their complex correlation). For this purpose, the use of an accurate electrical model allowing to capture the physics of the device is required, and we have used a well established model, intended to FD SOI MOS devices [6]. This model is based on a linear, physics-based relationship between the inversion charge density and the surface potential, which is physically justified in FD SOI MOSFETs. This allows us to obtain expressions of the drain current and total charges in terms of the inversion charge densities at the source and drain ends of the channel. The use of explicit expressions of the inversion charge densities in terms of the applied voltages leads to a compact model for the FD SOI MOSFET, which has an infinite order of continuity through all operating regimes. This last point is particularly important for it allows us to calculate the noise performance from small to strong inversion operation. In order to develop a noise modeling close to the device physics in a MOSFET, one has to take into account the distributed nature of the channel; for this issue, we have considered the device as a noisy active line [4,8]. It requires the determination of three electrical parameters Dc0 ðxÞ, Dgm ðxÞ, Dg0 ðxÞ of the local small signal equivalent circuit which can be deduced from the physical quantities varying along the channel (sheet carrier density, electrical field, etc. . .), but also the calculation of the local noise (current) source hi2n ðxÞi (Fig. 1). Once the local elements of the line and the
The local small-signal parameters of FD SOI MOSFETs are calculated as [6]: qleff W ðnðxÞ nðx þ DxÞÞ Dgm ðxÞ ¼ leff V ðxÞ Dx a 1 þ 2Dxvsat 2 qns hcof Id leff eSi qnðxÞ þ acof Vth l0 2 1 Dx l V ðxÞ ¼ Dr0 ðxÞ ¼ 1 þ eff Dg0 ðxÞ W 2Dxvsat 1 ! þ Drsat cof leff aV ðxÞ2 leff qnðxÞ 4Dxvsat
Dc0 ðxÞ ¼ cof W Dx
qnðxÞ acof Vth þ qnðxÞ
ð1Þ
ð2Þ
ð3Þ
where leff is the effective mobility, l0 the zero-bias mobility, nðxÞ the local inversion carrier density (per unit area), Vth the thermal voltage, q the electronic charge, W the channel width, Id the drain current, vsat the saturation velocity, h the mobility degradation parameter and cof the front oxide capacitance. Moreover, the other parameters are calculated as: V ðxÞ ¼ q
Drsat ¼
nðxÞ nðx þ DxÞ acof
Leff 2vsat l ðVds Vdsat Þ 1 þ eff Id leff 2ld vsat
a¼1þ
cb cob cof ðcob þ cb Þ
Fig. 1. MOS SOI channel in active line representation.
ð4Þ
ð5Þ
ð6Þ
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
where cob is the back oxide capacitance and cb the film capacitance. The above expressions for the local small-signal parameters include themselves the effect of velocity saturation. The definition of the microscopic noise sources hi2n i distributed along the channel is a key point of the modeling. The noise processes under investigation are related to carrier velocity fluctuations (e.g. diffusion noise). Consequently the spectral density Sin ðxÞ of hi2n i is given by: SðxÞ Sin ðxÞ ¼ 4 q2 nðxÞ De ðxÞ Dx SðxÞ ð7Þ ¼ 4 q Qnf ðxÞ De ðxÞ Dx where Dx is the length of the section. Qnf ðxÞ, De ðxÞ and SðxÞ are respectively the charge density in the channel (calculated by the physical model), the local lateral diffusion coefficient and the section of the effective channel at position x. In order to obtain Sin ðxÞ, we need an expression of the lateral diffusion coefficient. Considering the generalized Einstein relation, De ðxÞ is formulated as [9]:
De ðxÞ ¼
ðk Ta Þ leff ðxÞ q b !b1 b El ðxÞ 1þ Ec
ð8Þ
where k is the Boltzmann constant, Ec the lateral critical electrical field, Ta the room temperature, El ðxÞ the lateral electrical field at position x, and b is a coefficient set to 1.3 yielding realistic values for the electron diffusivity coefficient. Note that leff ðxÞ depends on the transversal gateto-electric field in self consistence with the physical model [6]. Eq. (8) includes basically hot carrier effects (which may have importance in the case of short channel). At this step, let us highlight the conditions for which the noise performances are calculated. Actually, the noisy channel under consideration is chosen from the source until the particular abscissa x ¼ xsat for which the carrier velocity saturates, e.g. the area for which the velocity is constant has been neglected. Nevertheless, xsat depends on the bias conditions, e.g. channel length modulation is taken into account, which corresponds to the work carried out in [3,5]. As a conclusion, the above considerations make our noise modeling to be fully consistent with the physical model [6] (once b is set, no additional parameter is required to perform the calculation).
817
in(x) ∆go(x) I1
V1
x
V(x)
x+dx
gm(x).V(x)
∆C0(x)
I2
V2
Fig. 2. Noisy intrinsic equivalent circuit in common gate configuration.
The general idea is taken from classical noise theory in circuits [10], applied to the local noisy equivalent circuits defined in Section 2.1. If we consider the noisy small signal equivalent circuit of one element of the active line in common gate configuration (Fig. 2), we can calculate its equivalent chain matrix CHg and its associated noise correlation matrix Cag [10]: 1 CHg ¼ Dgm ðxÞ þ Dg0 ðxÞ Dg0 ðxÞ 1 : j Dc0 ðxÞ x Dg0 ðxÞ Dgm ðxÞ þ Dg0 ðxÞ þ j Dc0 ðxÞ x
ð9Þ Cag ¼ ¼
he0 e0 i he0 i0 i hi0 e0 i hi0 i0 i
Sin ðxÞ ðDgm ðxÞ þ Dg0 ðxÞÞ2 1 j Dc0 ðxÞ x j Dc0 ðxÞ x ðDc0 xÞ2
ð10Þ
where corresponds to the conjugate. By cascading all the elements of the active line (see Appendix A as example the cascade of two successive local chain four poles), we obtain the equivalent chain CH0g and noise correlation matrixes Ca0g for the entire channel in common gate configuration. Note that the calculations are carried out using one hundred local equivalent circuits, e.g. the effective channel is divided into 100 elementary sections, to ensure the accuracy of the results [4]. By the end, we are using a path to recover the chain matrix CHs and its associated noise correlation matrix Cas in the usual common source configuration (Appendix B).
3. Results 2.2. An original noise modeling method The method which is described below allows basically to perform the AC and noise performances of any FET.
In the previous section, the noise modeling approach used to calculate the noise performance of SOI MOSFET has been presented, as well as the conditions for
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
which the calculation is carried out. In this section, we are going to comment the results obtained with the model. It goes from a description of the microscopic processes (distribution of the noise sources) using different representations, followed by a discussion on the bias dependency of the usual noise parameters such as P , R and C. Then the RF noise performances are performed and compared with measurements in the case of a FD SOI n-MOSFET (LETI technology) owing 0.25 lm physical gate length and 25 lm width (Fig. 3) [11]. A useful discussion related to the impact of down-scaling on the noise performances of MOSFETs concludes the section. All the results presented in this section assume that the back gate (due to the buried oxide) is biased to 0 V, i.e. the back channel is in depletion.
Cgd
Rgd
G
Cgs
D
V Cds
Gme-j. .τ. .V Ri
Gd
S
Fig. 4. Intrinsic equivalent circuit in common source configuration.
12
3.1. Small signal parameters Considering the admittance matrix Ys , calculated from CHs using Table 1, the intrinsic elements of the equivalent small signal circuit in common source configuration (Fig. 4) can then be obtained (Appendix C). Fig. 5 shows the simulated transconductance Gm versus frequency f compared with the experimental one. Good agreement is observed between the simulation and experimental data.
Gm (mS)
10 8 6
simulation experiment 4 2 0 0
Silicidation
Oxide
20
30
40
LDD( n
LOCOS OCOS Buried Oxide Substrate( p) Diffusion(n+ )
Fig. 3. Structure of the simulated and measured devices.
Figs. 6 and 7 show, respectively, the gate-to-source capacitance Cgs and drain to source capacitance Cgd versus frequency f . They are compared to experimental results. The results show a constant difference between simulations and experiments in the two cases, which is explained by the fact that the overlap capacitances have not been considered in this simulation. We have presented the results for the main elements of the small equivalent circuit, e.g. Gm and Cgs . Ri , the
Table 1 Transform of electrical equivalent matrix from one representation to another one To
From
Z
Z
Y CH
Z11 Z12 Z21 Z22 1 Z22 Z12 jZj Z21 Z11 1 Z11 detðZÞ Z22 Z21 1
50
Fig. 5. Transconductance Gm versus frequency (Vgs ¼ 1 V, Vds ¼ 1:5 V).
-)
LOCOSL LOCOS
10
Frequency (GHz)
Polysilicon
Y
1 Y22 Y12 jY j Y21 Y11 Y11 Y12 Y21 Y22 1 Y22 1 Y21 detðY Þ Y11
CH
1 CH11 detðCHÞ 1 CH22 CH21 1 CH22 detðCHÞ : 1 CH11 CH21 CH11 CH12 CH21 CH22
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
819
35
simulation experiment
30
Cgs (fF)
25 20 15 10 5 0 0
10
20
30
40
50
Frequency (GHz)
Fig. 6. Gate-to-source capacitance Cgs versus frequency (Vgs ¼ 1 V, Vds ¼ 1:5 V).
C
14 12
simulation experiment
Cgd (fF)
10
ig 8
[Y] Noiseless Intrinsic component
id
6
Fig. 8. Intrinsic equivalent circuit in current–current representation.
4 2 0 0
10
20
30
40
50
Frequency (GHz)
Fig. 7. Gate-to-drain capacitance Cgd versus frequency (Vgs ¼ 1 V, Vds ¼ 1:5 V).
intrinsic resistance or s, the delay time, are also calculated; these elements characterize nonquasi static effects which are usually not calculated using classical quasi static modeling. 3.2. Distribution of the current noise sources The noise correlation matrix Cys considering a ½Y representation provides the noise currents hi2g i and hi2d i
and their complex correlation hig id i in a current representation (Fig. 8). It is given by: C0 ¼ T C T t
ð11Þ
where T is a transform matrix given in Table 2 and superscript t stands for the transposed conjugate. At this point, we can have interest in the contribution of each local noise source distributed along the channel on the noise current hi2g i and hi2d i and their correlation hig id i (Fig. 9). The distribution of hi2d i is almost independent of the position x, while those of hi2g i is varying strongly along the channel (Fig. 9a). Furthermore, the distribution of the correlation hig id i is mainly imaginary (Fig. 9b), which confirms the capacitive coupling (presence of the oxide) existing between the gate and the channel [7].
Table 2 Transform of noise correlation matrix from one representation to another one From C To C
0
Admittance CY Impedance CZ Chain CA
Admittance CY 1 0 0 1 Z11 Z12 Z21 Z22 0 CH12 1 CH22
Impedance CZ Y11 Y12 Y21 Y22 1 0 0 1 1 CH11 0 CH21
Chain CA Y11 1 Y21 0 1 Z11 0 Z21 1 0 0 1
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825 R(/sqrt(.)) R(/sqrt(.))
0.02
0.045 0.04
0.015
/ / ig /
0.035
I(/sqrt(.)) I(/sqrt(.))
0.01
0.03
0.005
0.025
0
0.02
-0.005
0.015 0.01
-0.01
0.005
-0.015
0
-0.02 0
(a)
0.05 0.1 0.15 channel position (µm)
0
(b)
0.05 0.1 0.15 channel position (µm)
Fig. 9. Normalized distribution of hi2g i and hi2d i (a) and of their correlation hig id i (b) along the active channel (Vgs ¼ 1 V, Vds ¼ 1:5 V, f ¼ 6 GHz).
3.3. Intrinsic noise parameters P , R and C (current– current representation)
1
In order to discuss the variations of the noise sources, it is useful to define the usual noise parameters P , R and C from the noise current sources hi2g i, hi2d i and their correlation hig id i:
0.75
hi2d i ¼ 4 k Ta P Gm Df hi2g i ¼ 4 k Ta R
2 Cgs
0.8
P R C
0.6
0.5
0.4
0.25
0.2
ð12Þ
2
x Df Gm
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi hig id i ¼ j C hi2g i hi2d i
ð13Þ 0
0 0
ð14Þ
where Gm and Cgs are the transconductance and the gate-to-source capacitance extracted from the Y -matrix of the active line. Though the physical model has been optimized for short channel SOI MOSFET, it is interesting to simulate first a long SOI MOSFET channel (Fig. 10), and for that purpose, we did simply change the physical gate length. We observe the parameters P , R and C to be almost independent of the biasing conditions. The value of P (referenced to Gm in (12)) is equal to 0.9 and is consistent with the value of c (referenced to the conductance Gd at Vds ¼ 0 V) equal to (2/3) originally calculated by Van Der Ziel [7]. Indeed, in our simulation case, the transconductance Gm in saturation is slightly different to the conductance Gd at Vds ¼ 0 V, which actually gives P to be a little bit different of c for the simulation. The value of R is found to be equal to 0.2 and the value of the correlation coefficient C is found to be around 0.4 (0.395 in [7]). All of these results are con-
10
20
30
40
50
60
70
Id (mA/mm) Fig. 10. P , R and C parameters versus DC bias current Id for a 1 lm gate length device (Vds ¼ 5 V, f ¼ 6 GHz).
sistent with those published in the literature in the case of long channel MOSFET’s. The values of P , R and C in the case of a 0.25 lm physical gate length SOI MOSFET versus the DC bias current Id are presented in Fig. 11 (f ¼ 6 GHz, Vds ¼ 1:5 V, Vgs varying from the threshold voltage to 1.5 V). We observe quite low values for C (lower than 0.4 over the entire biasing range), which are physically related to the very different distributions of hi2d i and hi2g i (Fig. 9a). The decrease of C along the increase of Id is related to short channel effect (unlike what occurs in the case of long channel, Fig. 10). P is found to be strongly bias dependent (as compared to long channel, Fig. 10), which means that hi2d i is sensitive to short channel effect [5] and to an increase of the noise temperature (hot carrier effect) in the channel
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825 2
0.8
0.4
1.8
0.36
1.6
0.32
821
0.7
0.28
P R C
1.2 1
0.24 0.2
0.8
0.16
0.6
0.12
0.4
0.08
0.2
0.04
0 0
50
100
150
200
250
300
350
Nfmin (dB)
0.6
1.4
0.5 0.4 0.3
simulation without overlap simulation with overlap experiment
0.2 0.1
0 400
0 0
50
100
Id (mA/mm)
150
200
250
300
350
Id (mA/mm)
Fig. 11. P , R and C parameters versus DC bias current Id for a 0.25 lm gate length device (Vds ¼ 1:5 V, f ¼ 6 GHz).
Fig. 12. Minimum Noise Figure NFmin versus DC bias current Id (Vds ¼ 1:5 V, f ¼ 6 GHz).
[12]. Finally, R is almost independent of Id , leading hi2g i to be mainly determined by the values of the small signal parameters Cgs and Gm .
Though the variations of the theoretical and experimental minimum noise figure NFmin versus the DC bias current Id are well reproduced, the theoretical values ( ) are lower than the experimental ones (––) (Fig. 12). If the parasitic overlap capacitances, in conjunction with the access resistances, are taking into account (– –), the comparison is much better (Fig. 12). There is still some discrepancy on Rn (Fig. 13) either on the magnitude of Copt (Fig. 14) that might be improved by a better description of the diffusion coefficient (8). Nevertheless, we preferred to let go the simulation because of the excellent agreement on the minimum noise figure NFmin and on the phase of Copt (Fig. 14).
3.4. Noise performances In order to perform the calculation of the noise parameters NFmin , the minimum noise figure, Rn , the equivalent noise resistance, and Copt , the optimum reflection coefficient, the noisy access resistances (with related thermal noise), have been added to the intrinsic part of the SOI MOSFET (e.g. the noiseless small signal equivalent circuit derived from the active line associated to the calculated noise sources hi2g i, hi2d i). The method is described in Appendix D. The usual noise parameters NFmin , Rn and Copt are calculated from the noise correlation matrix Ca0s associated to the equivalent chain matrix CH0s of the component with its extrinsic elements, using these formulations:
gcor ¼ Rðycor Þ; gopt ¼
ð15Þ
300
ycor ¼
Ca0s21 Ca0s11
bcor ¼ Iðycor Þ
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 b2 ; yopt opt
350
Rn (ohms)
yopt
The model has been used also for a FD SOI MOSFETs of 0.13 lm physical gate length and 25 lm gate
400
jCa0s11 j Rn ¼ 4 k T0 Df vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u 0 u Ca ¼ t s22 ; Ca0s11
3.5. Noise properties and performance of up-coming FD SOI MOSFET generation
250 200 150 simulation experiment
100 50
bopt ¼ bcor
0 0
Yopt ¼ gopt þ j bopt
ð16Þ
NFmin ¼ 10 log10 ð1 þ 2 Rn ðgopt þ gcor ÞÞ
ð17Þ
50
100
150
200
250
300
350
Id (mA/mm)
Fig. 13. Noise equivalent resistance Rn versus DC bias current Id (Vds ¼ 1:5 V, f ¼ 6 GHz).
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825 10 9
0.96
8
0.94
7
0.92
6
0.9
5
0.88
4
0.86
simulation experiment
0.84 0.82
|Gammaopt|
1 0.98
3 2 1
0.8 0
50
100
150
200
250
300
0 350
Ids (mA/mm)
Fig. 14. Optimum reflexion coefficient Copt versus DC bias current Id (Vds ¼ 1:5 V, f ¼ 6 GHz).
2
To summarize, the above comments let think that the noise performance of future FD SOI MOSFETs will be closely related to the intrinsic small-signal elements. In particular, with the increase of the intrinsic cut-off frequency ðfc Þ one may expect better noise performances. Nevertheless, this expected improvement will be counterbalanced by the influence of extrinsic elements such as the access resistances (mainly the gate resistance for which the noise will be more and more preponderant comparing to those of the induced gate noise, which will keep on decreasing) [3]. Note as well that the increase of overlap capacitances (Miller effect) will have more and more importance for the future technology nodes; indeed, these elements limit the maximum oscillation frequency fmax , and consequently, NFmin (which is highly dependent of fmax ) [13].
0.4
1.8
0.36
1.6 1.4
0.28 L = 0.25 µm L = 0.12 µm
1.2 C
1
0.24 0.2
0.8
0.16
0.6
0.12
0.4
0.08
R
0.2
0.04
0 0
100
4. Conclusion
0.32
P
200
300
0 400
Id (mA/mm) Fig. 15. Comparison of P , R and C parameters versus DC bias current Id for two different gate lengths: 0.13 lm ( ) and 0.25 lm (––) (Vds ¼ 1:5 V, f ¼ 6 GHz).
width. The P , R and C parameters are shown in Fig. 15, and compared with the previous results obtained with the 0.25 lm gate length FD SOI MOSFETs. These results clearly show that the next generation of FD SOI MOSFETs will present few variations of the P , R and C parameters. Eqs. (12) and (13) allow a useful discussion upon the variations of the noise sources along the down scaling in MOSFETs. Indeed, from one technology node to another one (corresponding to a lower channel size), the transconductance Gm increases while the capacitance Cgs keeps on relatively constant, leading to the following features (if the channel length is decreasing): • The drain noise current will increase (12), phenomena amplified by short channel effects ðP Þ. • The induced gate noise current will decrease (13), for R is kept constant. Note that these results are fully consistent with the variations observed experimentally [3,5].
An original noise modeling for fully depleted SOI MOSFETs has been developed. This noise modeling is based on the active line method, using the chain matrixes in common gate configuration, prior operating a path to obtain both the electrical and noise parameters in the more usual common source configuration. This noise modeling is fully consistent with the physical compact model developed in [6]. It has been used first to study the way the microscopic noise sources distributed along the channel propagate to the electrodes. Then, the usual noise parameters P , R and C have been calculated, showing the influence of short channel effects on the drain noise current and the correlation coefficient. Taking into account the extrinsic elements, the usual noise parameters NFmin , Copt and Rn have been calculated and compared to experimental results, showing a quite good agreement. Finally, it has been shown that the P , R and C parameters for up-to-date FD SOI MOSFETs generation were slightly modified, leading the noise performance ðNFmin Þ of future FD SOI MOSFETs node to be highly sensitive to fmax .
Acknowledgement Part of this work was funded by the Conseil Regional du Nord Pas de Calais, France.
Appendix A. Cascading two elements of the active line using chain matrixes in common gate configuration In order to obtain the chain matrix of the whole channel in common gate configuration, we must cascade each element of the active line one after the other. To be
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
823
e’’
e’ I1
I2
V1
i’
[CHg2]
I3
V2
i’’
[CHg1]
V3
Fig. 16. Cascade of two elements in chain representation and common gate configuration.
consistent with the physical model [6], we perform those cascades from the drain side of the channel to the source side. With each element described with its equivalent chain matrix and its associated noise correlation matrix, we can calculate the equivalent chain matrix CH0g of two cascaded elements (Fig. 16), using this equation: CH0g ¼ ½CHg2 ½CHg1
ðA:1Þ
In the same time, the equivalent noise correlation matrix Ca0g is given by: he e i he i i 0 Cag ¼ hi e i hi i i ¼ ½CHg2 ½Cag1 ½CHg2 t þ ½Cag2
ðA:2Þ
Appendix B. Transformation of chain matrix and its associated noise correlation matrix from common gate configuration to common source configuration As the electrical and noise properties of two-port FETs are generally given in a common source configuration, we need to transform both electrical CH0g and noise Ca0g matrixes obtained in a common gate configuration to that usual configuration. Considering the common gate configuration, we have: e V Vsg ¼ ½CH0g : dg þ B ðB:1Þ Is Id iB In common source configuration, we should have: Vgs e Vds ¼ ½CHs þ A ðB:2Þ Ig Id iA
In the same time, considering Is ¼ Id þ Ig , Eq. (B.4) can be reformulated to: Ig ¼ CH0g21 ðVds Vgs Þ ð1 CH0g22 Þ Id iB
ðB:6Þ
Including Eq. (B.5) in Eq. (B.6), we obtain: Ig ¼
1 ðCH0g21 Vds ðCH0g11 þ CH0g22 CH0g11 1 1 detðCH0g ÞÞ Id Þ þ
CH0g21 eB i B CH0g11 1
ðB:7Þ
where detð Þ is the determinant of the matrix. By collecting Eqs. (B.5) and (B.7) into a matrix representation, we obtain: Vgs 1 ¼ 0 CH Ig g11 1 " # CH0g12 CH0g11 CH0g21 CH0g11 þ CH0g22 1 detðCH0g Þ 2 3 eB 0 6 CH 1 7 g11 Vds 6 7 þ6 ðB:8Þ 7 0 4 CHg21 eB 5 Id iB 0 CHg11 1 Comparing Eqs. (B.2) and (B.8), we can then define the its associated chain matrix CH s and noise correlation heA eA i heA iA i matrix Cas ¼ in common source hiA eA i hiA iA i configuration: CHs ¼
1 CH0g11 1 CH0g11 CH0g12 CH0g21 CH0g11 þ CH0g22 1 detðCH0g Þ
By expanding Eq. (B.1), we obtain: Vgs ¼
CH0g11
Vdg
CH0g12
Id þ eB
Is ¼ CH0g21 Vdg CH0g22 Id þ iB
ðB:9Þ ðB:3Þ ðB:4Þ
Considering Vgs ¼ Vsg and Vdg ¼ Vds þ Vsg Eq. (B.3) can be rewritten to: Vgs ¼
1 CH0g11 1
ðCH0g11 Vds CH0g12 Id þ eB Þ
ðB:5Þ
2
Ca0g11
g11
3 Ca0 CH0 g121 g11 0 7 7 jCH0g21 j2 Ca0g11 CHg21 Ca0g12 5 0 0 2 þ Cag22 2 R 0 CH 1 jCH 1j CH0 Ca0g11 g21
jCH0g11 1j2 6 Cas ¼ 6 4 CH0g21 Ca0g11 Ca0 CH0 g211 jCH0 1j2 g11
jCH0g11 1j2
g11
g11
ðB:10Þ
where jj is the modulus of the complex and R stands for real part.
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Appendix C. Extracting the intrinsic elements of the equivalent small signal circuit from Admittance matrix Considering the admittance matrix Y of the entire channel in common source configuration, the different elements of the small signal equivalent circuit in such a configuration are calculated using these formulations: 2 ! IðY12 Þ RðY12 Þ Cgd ¼ 1þ ðC:1Þ 2x IðY12 Þ
Rgd ¼
RðY12 Þ IðY12 Þ Cgd x
ðC:2Þ
½CZ0 s ¼ ½CZs þ 4 k Ta Df Rg þ Rs Rs Rs Rd þ Rs
ðD:2Þ
where CZs is the noise correlation matrix associated to the impedance matrix Zs , and is calculated from Cys using Eq. (11). Next, we take into account the parasitic capacitances using: 0 j Cpg x 00 0 ½Ys ¼ ½Ys þ ðD:3Þ 0 j Cpd x
ðC:4Þ
where Ys0 is the admittance matrix, calculated from the impedance matrix Zs0 . Cpg and Cpd are respectively the gate and drain parasitic capacitances. As the electrical behavior of the device changes, we must calculate the associated noise correlation matrix CYs0 using Eq. (11). Next, we consider the two last extrinsic elements which are the gate and drain parasitic self Lg and Ld with:
IðY22 Þ þ IðY12 Þ Cds ¼ 2x
ðC:5Þ
½Zs000 ¼ ½Zs00 þ
Gd ¼ RðY22 Þ þ RðY12 Þ
ðC:6Þ
where Zs00 is the impedance matrix, calculated from the admittance matrix Ys00 using Eq. (11). One more time, we must calculate the associated noise correlation CZs00 using Eq. (11). Finally, we transform the impedance matrix Zs000 into the chain matrix CH0s using Table 1 and we calculate its associated noise correlation matrix Ca0s using Table 2.
IðY11 Þ þ IðY12 Þ 1þ Cgs ¼ 2x
RðY11 Þ þ RðY12 Þ IðY11 Þ þ IðY12 Þ
2 !
ðC:3Þ Ri ¼
1 RðY11 Þ þ RðY12 Þ 2 x IðY11 Þ þ IðY12 Þ
RðY11 Þ þ RðY12 Þ Gm ¼ ðY21 Y12 Þ 1 þ j IðY Þ þ IðY Þ 11
s¼
ðC:7Þ
12
1 RðY11 Þ þ RðY12 Þ angle ðY21 Y12 Þ 1 þ j 2x IðY11 Þ þ IðY12 Þ
j Lg x 0 0 j Ld x
ðD:4Þ
ðC:8Þ References Appendix D. Completion of the noisy equivalent smallsignal circuit with the extrinsic elements To calculate the noise performances of the component, we have to take into account its extrinsic elements such as its noisy access resistances. Considering the Impedance matrix Zs , calculated from the Admittance matrix Ys using Table 1, the access resistances and the source parasitic self are taken into account using: Rg þ Rs þ j Ls x Rs þ j Ls x ½Zs0 ¼ ½Zs þ Rs þ j Ls x Rd þ Rs þ j Ls x ðD:1Þ where Rg , Rs and Rd are respectively the gate, source and drain access resistance and Ls is the parasitic source self. As the access resistances are noisy elements, the excess noise is given by:
[1] Colinge JP. Silicon-on-insulator technology: materials to VLSI, 2nd ed. Kluwer Academic Publishers. [2] Jin W, Chan PCH, Lau J. A physical thermal noise model for SOI MOSFET. IEEE Trans Electron Dev 2000;47(4): 768–73. [3] Scholten AJ, Tiemeijer LF, Van Langevelde R, Havens RJ, Zegers-van Duijnhoven ATA, Venezia VC. Noise modeling for RF CMOS circuit simulation. IEEE Trans Electron Dev 2003;50(3):618–32. [4] Goo J-S, Choi C-H, Danneville F, Morifuji E, Momose HS, Zhiping Y, et al. An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs. IEEE Trans Electron Dev 2000;47(12): 2410–9. [5] Chen CH, Deen MJ. Channel noise modeling of deep submicron MOSFETs. IEEE Trans Electron Dev 2002; 49(8):1484–7. [6] I~ nıguez B, Ferreira LF, Gentinne B, Flandre D. A physically-based c1 -continuous fully-depleted SOI MOSFET
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[7] [8]
[9]
[10]
model for analog applications. IEEE Trans Electron Dev 1996;43(4):568–75. Van Der Ziel A. Thermal noise in field effect transistor. Proc IRE 1962;50:1808–12. Cappy A, Heinrich W. High-frequency FET noise performance: a new approach. IEEE Trans Electron Dev 1989; 36(2):403–9. Ali Omar M, Reggiani L. Drift and diffusion of charge carriers in silicon and their empirical relation to the electric field. Solid-State Electron 1987;30:693–7. Hillbrand H, Russer P. An efficient method for computer aided noise analysis of linear amplifier networks. IEEE Trans Circuits Syst 1976;23(4):235–8.
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[11] Vanmackelberg M et al. 0.25 lm fully depleted SOI MOSFETs for RF mixed analog–digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters. Solid-State Electron 2002;46:379–86. [12] Danneville F, Happy H, Dambrine G, Belquin JM, Cappy A. Microscopic noise modeling and macroscopic noise models: how good a connection? IEEE Trans Electron Dev 1994;41(5):779–86. [13] Dambrine G, Raynaud C, Lederer D, Dehan M, Rozeaux O, Vanmackelberg M, et al. What are the limiting parameters of deep-submicron MOSFETs for high frequency applications? IEEE Electron Dev Lett 2003;24(3): 189–91.
Noise modeling in fully depleted SOI MOSFETs G. Pailloncy
a,*
, B. Iniguez b, G. Dambrine a, J.-P. Raskin c, F. Danneville
a
a
Institut d’Electronique, de Microelectronique et de Nanotechnologie (IEMN), UMR CNRS 8520, Av. Poincare, BP 69, 59652 Villeneuve d’Ascq, France b Department of Electrical, Electronic and Automatic Engineering, Universitat Rovira i Virgili, Avinguda dels Paisos Catalans, 26 43007 Tarragona, Spain c Universite catholique de Louvain-la-Neuve (UCL), Maxwell Building, Place du Levant 3, B-1348 Louvain la Neuve, Belgium Received 18 December 2003; accepted 22 December 2003
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract In this paper, we are presenting a noise modeling technique in fully depleted (FD) SOI MOSFET. Starting from a physical compact model which allows us to capture the physics in such devices, an original microscopic noise model, suitable to calculate the noise performance of any field effect transistor, is developed. The method is applied to study the noise properties of FD SOI MOSFETs (0.25 lm physical gate length, 0.16 lm effective gate length); this includes a discussion at a microscopic level, the calculation of the usual P , R, C parameters (close to the device physics) and of the noise performances, taking into account extrinsic elements. To conclude, a discussion related to the noise performances as a function of the down-scaling is proposed. 2004 Elsevier Ltd. All rights reserved. Keywords: SOI; MOSFETs; High frequency noise; Active line
1. Introduction The use of low power, low noise devices for future telecommunication applications becomes more and more important. Especially, SOI devices are excellent candidates to become an alternative to conventional bulk CMOS, for they are presenting lower parasitic junction capacitance, higher drive current, higher transconductance, smaller short channel effects [1]. All of this makes their high frequency performances to be higher than for bulk CMOS, which is of primary importance for the development of future wireless telecommunication circuits. Though these devices present such good characteristics, their noise performance have
* Corresponding author. Tel.: +33-320-19-79-79; fax: +33320-19-78-92. E-mail address: [email protected] (G. Pailloncy).
not been studied intensively [2], unlike bulk CMOS [3– 5]. Thus, a rigorous microscopic approach allowing to calculate the overall noise correlation matrix of the transistor in any useful representation is necessary. In this paper, based on the active line method to take into account the distributed nature of the channel, we are calculating the high frequency noise performance of FD SOI MOSFETs. The first point required in order to develop a noise modeling is obviously to capture the physics, which has been carried out using a physical compact model developed by I~ niguez et al. [6]. In Section 3, starting from this physical model, the path allowing to define the local small signal equivalent circuit (SSEC) of the active line is presented. Taking into account the contributions of each section along the channel, one can define the elements which constitute the conventional p equivalent circuit of the FET. Then, special emphasis is made towards the way the microscopic noise sources distributed along the channel are defined, and an original method, developed to calculate
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.12.032
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
Nomenclature P R C NFmin Rn Copt Dc0 Dgm Dg0 hi2n i q leff W nðxÞ h cof Id a Dx Vth l0 Dr0 Drsat V ðxÞ vsat Leff Vds Vdsat ld cb cob Sin De S Qnf k Ta El Ec b xsat CHg Cag j x * CH0g Ca0g Ys Gm f Cgs
diffusion noise parameter related to hi2d i diffusion noise parameter related to hi2g i normalized correlation coefficient between hi2g i and hi2d i minimum noise figure equivalent noise resistance optimum reflexion coefficient local gate-to-channel capacitance local transconductance local channel conductance local diffusion noise source electron charge effective mobility channel width local inversion carrier density per unit area at position x mobility degradation parameter front oxide capacitance DC drain-to-source current body effect parameter section length thermal voltage zero-bias mobility local channel resistance contribution of the channel length modulation to the local resistance channel potential at position x saturation velocity effective channel length DC drain-to-source voltage saturation voltage characteristic length film capacitance back oxide capacitance noise spectral density local diffusion coefficient effective channel section charge density Boltzmann constant room temperature lateral electrical field critical lateral electrical field local diffusion coefficient parameter carrier velocity saturation channel position local equivalent chain matrix in common gate configuration local noise correlation matrix associated to CHg imaginary term pulsation conjugate of a complex equivalent chain matrix of the entire channel in common gate configuration noise correlation matrix associated to CH0g admittance matrix in common source configuration transconductance frequency gate-to-source capacitance
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
Cgd Ri s T t
hi2g i hi2d i hig id i Df Vgs CH0s Ca0s detð Þ jj R I gopt bopt Yopt fc fmax Vsg Is Vdg Ig CHs Cas Rgd Cds Gd Zs Rg Rs Rd Ls Zs0 CZs CZs0 Ys0 Cpg Cpd Ys00 CYs0 Zs00 Lg Ld Zs000 CZs00
815
gate-to-drain capacitance intrinsic resistance delay Time transform matrix transposed conjugate of matrix gate diffusion noise current source in short-circuit representation at input and output drain diffusion noise current source in short-circuit representation at input and output diffusion noise sources cross-correlation of hi2g i and hi2d i frequency bandwidth DC gate-to-source voltage equivalent chain matrix in common source configuration considering extrinsic elements noise correlation matrix associated to CH0s matrix determinant complex modulus real part of a complex imaginary part of a complex optimum noise conductance optimum noise susceptance optimum noise admittance intrinsic cut-off frequency maximum oscillation frequency DC source-to-gate voltage DC source current DC drain-to-gate voltage DC gate current chain matrix in common source configuration noise correlation matrix associated to CHs gate-to-drain resistance drain-to-source capacitance drain-to-source conductance equivalent impedance matrix of the entire channel in common source configuration gate access resistance source access resistance drain access resistance parasitic source inductance equivalent impedance matrix in common source configuration considering Rg , Rs , Rd and Ls noise correlation matrix associated to Zs noise correlation matrix associated to Zs0 equivalent admittance matrix calculated from Zs0 gate parasitic capacitance drain parasitic capacitance equivalent admittance matrix in common source configuration considering Rg , Rs , Rd , Ls , Cpg and Cpd noise correlation matrix associated to Ys00 equivalent impedance matrix calculated from Ys000 gate parasitic inductance drain parasitic inductance equivalent impedance matrix in common source configuration considering all the extrinsic elements noise correlation matrix associated to Zs000
the influence of all the microscopic noise sources at the device electrodes, is presented. In Section 4, the results obtained for several FD SOI MOSFETs are presented (long channels, 0.16 and 0.10 lm effective gate length devices). In a current–current
representation [7], the noise properties are studied in detail: it goes from the distribution of the noise sources to the bias dependency of the usual noise parameters such as P , R and C. Then the noise performance calculations of FD SOI MOSFET (in terms of NFmin , Rn and
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
Copt ) are undertaken and compared with the experimental ones. To conclude, a discussion related to the down-scaling on SOI MOSFETs is proposed.
microscopic noise sources are defined, a noise modeling can be carried out. 2.1. Determination of the active line elements (Dc0 (x), Dgm (x), Dg0 (x)) and of hi2n (x)i
2. An original noise modeling method for FD SOI MOSFETs A complete modeling of the noise performance of a device requires calculating the small signal parameters and the associated two noise sources (completely defined by their spectral densities and their complex correlation). For this purpose, the use of an accurate electrical model allowing to capture the physics of the device is required, and we have used a well established model, intended to FD SOI MOS devices [6]. This model is based on a linear, physics-based relationship between the inversion charge density and the surface potential, which is physically justified in FD SOI MOSFETs. This allows us to obtain expressions of the drain current and total charges in terms of the inversion charge densities at the source and drain ends of the channel. The use of explicit expressions of the inversion charge densities in terms of the applied voltages leads to a compact model for the FD SOI MOSFET, which has an infinite order of continuity through all operating regimes. This last point is particularly important for it allows us to calculate the noise performance from small to strong inversion operation. In order to develop a noise modeling close to the device physics in a MOSFET, one has to take into account the distributed nature of the channel; for this issue, we have considered the device as a noisy active line [4,8]. It requires the determination of three electrical parameters Dc0 ðxÞ, Dgm ðxÞ, Dg0 ðxÞ of the local small signal equivalent circuit which can be deduced from the physical quantities varying along the channel (sheet carrier density, electrical field, etc. . .), but also the calculation of the local noise (current) source hi2n ðxÞi (Fig. 1). Once the local elements of the line and the
The local small-signal parameters of FD SOI MOSFETs are calculated as [6]: qleff W ðnðxÞ nðx þ DxÞÞ Dgm ðxÞ ¼ leff V ðxÞ Dx a 1 þ 2Dxvsat 2 qns hcof Id leff eSi qnðxÞ þ acof Vth l0 2 1 Dx l V ðxÞ ¼ Dr0 ðxÞ ¼ 1 þ eff Dg0 ðxÞ W 2Dxvsat 1 ! þ Drsat cof leff aV ðxÞ2 leff qnðxÞ 4Dxvsat
Dc0 ðxÞ ¼ cof W Dx
qnðxÞ acof Vth þ qnðxÞ
ð1Þ
ð2Þ
ð3Þ
where leff is the effective mobility, l0 the zero-bias mobility, nðxÞ the local inversion carrier density (per unit area), Vth the thermal voltage, q the electronic charge, W the channel width, Id the drain current, vsat the saturation velocity, h the mobility degradation parameter and cof the front oxide capacitance. Moreover, the other parameters are calculated as: V ðxÞ ¼ q
Drsat ¼
nðxÞ nðx þ DxÞ acof
Leff 2vsat l ðVds Vdsat Þ 1 þ eff Id leff 2ld vsat
a¼1þ
cb cob cof ðcob þ cb Þ
Fig. 1. MOS SOI channel in active line representation.
ð4Þ
ð5Þ
ð6Þ
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
where cob is the back oxide capacitance and cb the film capacitance. The above expressions for the local small-signal parameters include themselves the effect of velocity saturation. The definition of the microscopic noise sources hi2n i distributed along the channel is a key point of the modeling. The noise processes under investigation are related to carrier velocity fluctuations (e.g. diffusion noise). Consequently the spectral density Sin ðxÞ of hi2n i is given by: SðxÞ Sin ðxÞ ¼ 4 q2 nðxÞ De ðxÞ Dx SðxÞ ð7Þ ¼ 4 q Qnf ðxÞ De ðxÞ Dx where Dx is the length of the section. Qnf ðxÞ, De ðxÞ and SðxÞ are respectively the charge density in the channel (calculated by the physical model), the local lateral diffusion coefficient and the section of the effective channel at position x. In order to obtain Sin ðxÞ, we need an expression of the lateral diffusion coefficient. Considering the generalized Einstein relation, De ðxÞ is formulated as [9]:
De ðxÞ ¼
ðk Ta Þ leff ðxÞ q b !b1 b El ðxÞ 1þ Ec
ð8Þ
where k is the Boltzmann constant, Ec the lateral critical electrical field, Ta the room temperature, El ðxÞ the lateral electrical field at position x, and b is a coefficient set to 1.3 yielding realistic values for the electron diffusivity coefficient. Note that leff ðxÞ depends on the transversal gateto-electric field in self consistence with the physical model [6]. Eq. (8) includes basically hot carrier effects (which may have importance in the case of short channel). At this step, let us highlight the conditions for which the noise performances are calculated. Actually, the noisy channel under consideration is chosen from the source until the particular abscissa x ¼ xsat for which the carrier velocity saturates, e.g. the area for which the velocity is constant has been neglected. Nevertheless, xsat depends on the bias conditions, e.g. channel length modulation is taken into account, which corresponds to the work carried out in [3,5]. As a conclusion, the above considerations make our noise modeling to be fully consistent with the physical model [6] (once b is set, no additional parameter is required to perform the calculation).
817
in(x) ∆go(x) I1
V1
x
V(x)
x+dx
gm(x).V(x)
∆C0(x)
I2
V2
Fig. 2. Noisy intrinsic equivalent circuit in common gate configuration.
The general idea is taken from classical noise theory in circuits [10], applied to the local noisy equivalent circuits defined in Section 2.1. If we consider the noisy small signal equivalent circuit of one element of the active line in common gate configuration (Fig. 2), we can calculate its equivalent chain matrix CHg and its associated noise correlation matrix Cag [10]: 1 CHg ¼ Dgm ðxÞ þ Dg0 ðxÞ Dg0 ðxÞ 1 : j Dc0 ðxÞ x Dg0 ðxÞ Dgm ðxÞ þ Dg0 ðxÞ þ j Dc0 ðxÞ x
ð9Þ Cag ¼ ¼
he0 e0 i he0 i0 i hi0 e0 i hi0 i0 i
Sin ðxÞ ðDgm ðxÞ þ Dg0 ðxÞÞ2 1 j Dc0 ðxÞ x j Dc0 ðxÞ x ðDc0 xÞ2
ð10Þ
where corresponds to the conjugate. By cascading all the elements of the active line (see Appendix A as example the cascade of two successive local chain four poles), we obtain the equivalent chain CH0g and noise correlation matrixes Ca0g for the entire channel in common gate configuration. Note that the calculations are carried out using one hundred local equivalent circuits, e.g. the effective channel is divided into 100 elementary sections, to ensure the accuracy of the results [4]. By the end, we are using a path to recover the chain matrix CHs and its associated noise correlation matrix Cas in the usual common source configuration (Appendix B).
3. Results 2.2. An original noise modeling method The method which is described below allows basically to perform the AC and noise performances of any FET.
In the previous section, the noise modeling approach used to calculate the noise performance of SOI MOSFET has been presented, as well as the conditions for
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
which the calculation is carried out. In this section, we are going to comment the results obtained with the model. It goes from a description of the microscopic processes (distribution of the noise sources) using different representations, followed by a discussion on the bias dependency of the usual noise parameters such as P , R and C. Then the RF noise performances are performed and compared with measurements in the case of a FD SOI n-MOSFET (LETI technology) owing 0.25 lm physical gate length and 25 lm width (Fig. 3) [11]. A useful discussion related to the impact of down-scaling on the noise performances of MOSFETs concludes the section. All the results presented in this section assume that the back gate (due to the buried oxide) is biased to 0 V, i.e. the back channel is in depletion.
Cgd
Rgd
G
Cgs
D
V Cds
Gme-j. .τ. .V Ri
Gd
S
Fig. 4. Intrinsic equivalent circuit in common source configuration.
12
3.1. Small signal parameters Considering the admittance matrix Ys , calculated from CHs using Table 1, the intrinsic elements of the equivalent small signal circuit in common source configuration (Fig. 4) can then be obtained (Appendix C). Fig. 5 shows the simulated transconductance Gm versus frequency f compared with the experimental one. Good agreement is observed between the simulation and experimental data.
Gm (mS)
10 8 6
simulation experiment 4 2 0 0
Silicidation
Oxide
20
30
40
LDD( n
LOCOS OCOS Buried Oxide Substrate( p) Diffusion(n+ )
Fig. 3. Structure of the simulated and measured devices.
Figs. 6 and 7 show, respectively, the gate-to-source capacitance Cgs and drain to source capacitance Cgd versus frequency f . They are compared to experimental results. The results show a constant difference between simulations and experiments in the two cases, which is explained by the fact that the overlap capacitances have not been considered in this simulation. We have presented the results for the main elements of the small equivalent circuit, e.g. Gm and Cgs . Ri , the
Table 1 Transform of electrical equivalent matrix from one representation to another one To
From
Z
Z
Y CH
Z11 Z12 Z21 Z22 1 Z22 Z12 jZj Z21 Z11 1 Z11 detðZÞ Z22 Z21 1
50
Fig. 5. Transconductance Gm versus frequency (Vgs ¼ 1 V, Vds ¼ 1:5 V).
-)
LOCOSL LOCOS
10
Frequency (GHz)
Polysilicon
Y
1 Y22 Y12 jY j Y21 Y11 Y11 Y12 Y21 Y22 1 Y22 1 Y21 detðY Þ Y11
CH
1 CH11 detðCHÞ 1 CH22 CH21 1 CH22 detðCHÞ : 1 CH11 CH21 CH11 CH12 CH21 CH22
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
819
35
simulation experiment
30
Cgs (fF)
25 20 15 10 5 0 0
10
20
30
40
50
Frequency (GHz)
Fig. 6. Gate-to-source capacitance Cgs versus frequency (Vgs ¼ 1 V, Vds ¼ 1:5 V).
C
14 12
simulation experiment
Cgd (fF)
10
ig 8
[Y] Noiseless Intrinsic component
id
6
Fig. 8. Intrinsic equivalent circuit in current–current representation.
4 2 0 0
10
20
30
40
50
Frequency (GHz)
Fig. 7. Gate-to-drain capacitance Cgd versus frequency (Vgs ¼ 1 V, Vds ¼ 1:5 V).
intrinsic resistance or s, the delay time, are also calculated; these elements characterize nonquasi static effects which are usually not calculated using classical quasi static modeling. 3.2. Distribution of the current noise sources The noise correlation matrix Cys considering a ½Y representation provides the noise currents hi2g i and hi2d i
and their complex correlation hig id i in a current representation (Fig. 8). It is given by: C0 ¼ T C T t
ð11Þ
where T is a transform matrix given in Table 2 and superscript t stands for the transposed conjugate. At this point, we can have interest in the contribution of each local noise source distributed along the channel on the noise current hi2g i and hi2d i and their correlation hig id i (Fig. 9). The distribution of hi2d i is almost independent of the position x, while those of hi2g i is varying strongly along the channel (Fig. 9a). Furthermore, the distribution of the correlation hig id i is mainly imaginary (Fig. 9b), which confirms the capacitive coupling (presence of the oxide) existing between the gate and the channel [7].
Table 2 Transform of noise correlation matrix from one representation to another one From C To C
0
Admittance CY Impedance CZ Chain CA
Admittance CY 1 0 0 1 Z11 Z12 Z21 Z22 0 CH12 1 CH22
Impedance CZ Y11 Y12 Y21 Y22 1 0 0 1 1 CH11 0 CH21
Chain CA Y11 1 Y21 0 1 Z11 0 Z21 1 0 0 1
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825 R(
0.02
0.045 0.04
0.015
0.035
I(
0.01
0.03
0.005
0.025
0
0.02
-0.005
0.015 0.01
-0.01
0.005
-0.015
0
-0.02 0
(a)
0.05 0.1 0.15 channel position (µm)
0
(b)
0.05 0.1 0.15 channel position (µm)
Fig. 9. Normalized distribution of hi2g i and hi2d i (a) and of their correlation hig id i (b) along the active channel (Vgs ¼ 1 V, Vds ¼ 1:5 V, f ¼ 6 GHz).
3.3. Intrinsic noise parameters P , R and C (current– current representation)
1
In order to discuss the variations of the noise sources, it is useful to define the usual noise parameters P , R and C from the noise current sources hi2g i, hi2d i and their correlation hig id i:
0.75
hi2d i ¼ 4 k Ta P Gm Df hi2g i ¼ 4 k Ta R
2 Cgs
0.8
P R C
0.6
0.5
0.4
0.25
0.2
ð12Þ
2
x Df Gm
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi hig id i ¼ j C hi2g i hi2d i
ð13Þ 0
0 0
ð14Þ
where Gm and Cgs are the transconductance and the gate-to-source capacitance extracted from the Y -matrix of the active line. Though the physical model has been optimized for short channel SOI MOSFET, it is interesting to simulate first a long SOI MOSFET channel (Fig. 10), and for that purpose, we did simply change the physical gate length. We observe the parameters P , R and C to be almost independent of the biasing conditions. The value of P (referenced to Gm in (12)) is equal to 0.9 and is consistent with the value of c (referenced to the conductance Gd at Vds ¼ 0 V) equal to (2/3) originally calculated by Van Der Ziel [7]. Indeed, in our simulation case, the transconductance Gm in saturation is slightly different to the conductance Gd at Vds ¼ 0 V, which actually gives P to be a little bit different of c for the simulation. The value of R is found to be equal to 0.2 and the value of the correlation coefficient C is found to be around 0.4 (0.395 in [7]). All of these results are con-
10
20
30
40
50
60
70
Id (mA/mm) Fig. 10. P , R and C parameters versus DC bias current Id for a 1 lm gate length device (Vds ¼ 5 V, f ¼ 6 GHz).
sistent with those published in the literature in the case of long channel MOSFET’s. The values of P , R and C in the case of a 0.25 lm physical gate length SOI MOSFET versus the DC bias current Id are presented in Fig. 11 (f ¼ 6 GHz, Vds ¼ 1:5 V, Vgs varying from the threshold voltage to 1.5 V). We observe quite low values for C (lower than 0.4 over the entire biasing range), which are physically related to the very different distributions of hi2d i and hi2g i (Fig. 9a). The decrease of C along the increase of Id is related to short channel effect (unlike what occurs in the case of long channel, Fig. 10). P is found to be strongly bias dependent (as compared to long channel, Fig. 10), which means that hi2d i is sensitive to short channel effect [5] and to an increase of the noise temperature (hot carrier effect) in the channel
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825 2
0.8
0.4
1.8
0.36
1.6
0.32
821
0.7
0.28
P R C
1.2 1
0.24 0.2
0.8
0.16
0.6
0.12
0.4
0.08
0.2
0.04
0 0
50
100
150
200
250
300
350
Nfmin (dB)
0.6
1.4
0.5 0.4 0.3
simulation without overlap simulation with overlap experiment
0.2 0.1
0 400
0 0
50
100
Id (mA/mm)
150
200
250
300
350
Id (mA/mm)
Fig. 11. P , R and C parameters versus DC bias current Id for a 0.25 lm gate length device (Vds ¼ 1:5 V, f ¼ 6 GHz).
Fig. 12. Minimum Noise Figure NFmin versus DC bias current Id (Vds ¼ 1:5 V, f ¼ 6 GHz).
[12]. Finally, R is almost independent of Id , leading hi2g i to be mainly determined by the values of the small signal parameters Cgs and Gm .
Though the variations of the theoretical and experimental minimum noise figure NFmin versus the DC bias current Id are well reproduced, the theoretical values ( ) are lower than the experimental ones (––) (Fig. 12). If the parasitic overlap capacitances, in conjunction with the access resistances, are taking into account (– –), the comparison is much better (Fig. 12). There is still some discrepancy on Rn (Fig. 13) either on the magnitude of Copt (Fig. 14) that might be improved by a better description of the diffusion coefficient (8). Nevertheless, we preferred to let go the simulation because of the excellent agreement on the minimum noise figure NFmin and on the phase of Copt (Fig. 14).
3.4. Noise performances In order to perform the calculation of the noise parameters NFmin , the minimum noise figure, Rn , the equivalent noise resistance, and Copt , the optimum reflection coefficient, the noisy access resistances (with related thermal noise), have been added to the intrinsic part of the SOI MOSFET (e.g. the noiseless small signal equivalent circuit derived from the active line associated to the calculated noise sources hi2g i, hi2d i). The method is described in Appendix D. The usual noise parameters NFmin , Rn and Copt are calculated from the noise correlation matrix Ca0s associated to the equivalent chain matrix CH0s of the component with its extrinsic elements, using these formulations:
gcor ¼ Rðycor Þ; gopt ¼
ð15Þ
300
ycor ¼
Ca0s21 Ca0s11
bcor ¼ Iðycor Þ
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 b2 ; yopt opt
350
Rn (ohms)
yopt
The model has been used also for a FD SOI MOSFETs of 0.13 lm physical gate length and 25 lm gate
400
jCa0s11 j Rn ¼ 4 k T0 Df vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u 0 u Ca ¼ t s22 ; Ca0s11
3.5. Noise properties and performance of up-coming FD SOI MOSFET generation
250 200 150 simulation experiment
100 50
bopt ¼ bcor
0 0
Yopt ¼ gopt þ j bopt
ð16Þ
NFmin ¼ 10 log10 ð1 þ 2 Rn ðgopt þ gcor ÞÞ
ð17Þ
50
100
150
200
250
300
350
Id (mA/mm)
Fig. 13. Noise equivalent resistance Rn versus DC bias current Id (Vds ¼ 1:5 V, f ¼ 6 GHz).
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825 10 9
0.96
8
0.94
7
0.92
6
0.9
5
0.88
4
0.86
simulation experiment
0.84 0.82
|Gammaopt|
1 0.98
3 2 1
0.8 0
50
100
150
200
250
300
0 350
Ids (mA/mm)
Fig. 14. Optimum reflexion coefficient Copt versus DC bias current Id (Vds ¼ 1:5 V, f ¼ 6 GHz).
2
To summarize, the above comments let think that the noise performance of future FD SOI MOSFETs will be closely related to the intrinsic small-signal elements. In particular, with the increase of the intrinsic cut-off frequency ðfc Þ one may expect better noise performances. Nevertheless, this expected improvement will be counterbalanced by the influence of extrinsic elements such as the access resistances (mainly the gate resistance for which the noise will be more and more preponderant comparing to those of the induced gate noise, which will keep on decreasing) [3]. Note as well that the increase of overlap capacitances (Miller effect) will have more and more importance for the future technology nodes; indeed, these elements limit the maximum oscillation frequency fmax , and consequently, NFmin (which is highly dependent of fmax ) [13].
0.4
1.8
0.36
1.6 1.4
0.28 L = 0.25 µm L = 0.12 µm
1.2 C
1
0.24 0.2
0.8
0.16
0.6
0.12
0.4
0.08
R
0.2
0.04
0 0
100
4. Conclusion
0.32
P
200
300
0 400
Id (mA/mm) Fig. 15. Comparison of P , R and C parameters versus DC bias current Id for two different gate lengths: 0.13 lm ( ) and 0.25 lm (––) (Vds ¼ 1:5 V, f ¼ 6 GHz).
width. The P , R and C parameters are shown in Fig. 15, and compared with the previous results obtained with the 0.25 lm gate length FD SOI MOSFETs. These results clearly show that the next generation of FD SOI MOSFETs will present few variations of the P , R and C parameters. Eqs. (12) and (13) allow a useful discussion upon the variations of the noise sources along the down scaling in MOSFETs. Indeed, from one technology node to another one (corresponding to a lower channel size), the transconductance Gm increases while the capacitance Cgs keeps on relatively constant, leading to the following features (if the channel length is decreasing): • The drain noise current will increase (12), phenomena amplified by short channel effects ðP Þ. • The induced gate noise current will decrease (13), for R is kept constant. Note that these results are fully consistent with the variations observed experimentally [3,5].
An original noise modeling for fully depleted SOI MOSFETs has been developed. This noise modeling is based on the active line method, using the chain matrixes in common gate configuration, prior operating a path to obtain both the electrical and noise parameters in the more usual common source configuration. This noise modeling is fully consistent with the physical compact model developed in [6]. It has been used first to study the way the microscopic noise sources distributed along the channel propagate to the electrodes. Then, the usual noise parameters P , R and C have been calculated, showing the influence of short channel effects on the drain noise current and the correlation coefficient. Taking into account the extrinsic elements, the usual noise parameters NFmin , Copt and Rn have been calculated and compared to experimental results, showing a quite good agreement. Finally, it has been shown that the P , R and C parameters for up-to-date FD SOI MOSFETs generation were slightly modified, leading the noise performance ðNFmin Þ of future FD SOI MOSFETs node to be highly sensitive to fmax .
Acknowledgement Part of this work was funded by the Conseil Regional du Nord Pas de Calais, France.
Appendix A. Cascading two elements of the active line using chain matrixes in common gate configuration In order to obtain the chain matrix of the whole channel in common gate configuration, we must cascade each element of the active line one after the other. To be
G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
823
e’’
e’ I1
I2
V1
i’
[CHg2]
I3
V2
i’’
[CHg1]
V3
Fig. 16. Cascade of two elements in chain representation and common gate configuration.
consistent with the physical model [6], we perform those cascades from the drain side of the channel to the source side. With each element described with its equivalent chain matrix and its associated noise correlation matrix, we can calculate the equivalent chain matrix CH0g of two cascaded elements (Fig. 16), using this equation: CH0g ¼ ½CHg2 ½CHg1
ðA:1Þ
In the same time, the equivalent noise correlation matrix Ca0g is given by: he e i he i i 0 Cag ¼ hi e i hi i i ¼ ½CHg2 ½Cag1 ½CHg2 t þ ½Cag2
ðA:2Þ
Appendix B. Transformation of chain matrix and its associated noise correlation matrix from common gate configuration to common source configuration As the electrical and noise properties of two-port FETs are generally given in a common source configuration, we need to transform both electrical CH0g and noise Ca0g matrixes obtained in a common gate configuration to that usual configuration. Considering the common gate configuration, we have: e V Vsg ¼ ½CH0g : dg þ B ðB:1Þ Is Id iB In common source configuration, we should have: Vgs e Vds ¼ ½CHs þ A ðB:2Þ Ig Id iA
In the same time, considering Is ¼ Id þ Ig , Eq. (B.4) can be reformulated to: Ig ¼ CH0g21 ðVds Vgs Þ ð1 CH0g22 Þ Id iB
ðB:6Þ
Including Eq. (B.5) in Eq. (B.6), we obtain: Ig ¼
1 ðCH0g21 Vds ðCH0g11 þ CH0g22 CH0g11 1 1 detðCH0g ÞÞ Id Þ þ
CH0g21 eB i B CH0g11 1
ðB:7Þ
where detð Þ is the determinant of the matrix. By collecting Eqs. (B.5) and (B.7) into a matrix representation, we obtain: Vgs 1 ¼ 0 CH Ig g11 1 " # CH0g12 CH0g11 CH0g21 CH0g11 þ CH0g22 1 detðCH0g Þ 2 3 eB 0 6 CH 1 7 g11 Vds 6 7 þ6 ðB:8Þ 7 0 4 CHg21 eB 5 Id iB 0 CHg11 1 Comparing Eqs. (B.2) and (B.8), we can then define the its associated chain matrix CH s and noise correlation heA eA i heA iA i matrix Cas ¼ in common source hiA eA i hiA iA i configuration: CHs ¼
1 CH0g11 1 CH0g11 CH0g12 CH0g21 CH0g11 þ CH0g22 1 detðCH0g Þ
By expanding Eq. (B.1), we obtain: Vgs ¼
CH0g11
Vdg
CH0g12
Id þ eB
Is ¼ CH0g21 Vdg CH0g22 Id þ iB
ðB:9Þ ðB:3Þ ðB:4Þ
Considering Vgs ¼ Vsg and Vdg ¼ Vds þ Vsg Eq. (B.3) can be rewritten to: Vgs ¼
1 CH0g11 1
ðCH0g11 Vds CH0g12 Id þ eB Þ
ðB:5Þ
2
Ca0g11
g11
3 Ca0 CH0 g121 g11 0 7 7 jCH0g21 j2 Ca0g11 CHg21 Ca0g12 5 0 0 2 þ Cag22 2 R 0 CH 1 jCH 1j CH0 Ca0g11 g21
jCH0g11 1j2 6 Cas ¼ 6 4 CH0g21 Ca0g11 Ca0 CH0 g211 jCH0 1j2 g11
jCH0g11 1j2
g11
g11
ðB:10Þ
where jj is the modulus of the complex and R stands for real part.
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G. Pailloncy et al. / Solid-State Electronics 48 (2004) 813–825
Appendix C. Extracting the intrinsic elements of the equivalent small signal circuit from Admittance matrix Considering the admittance matrix Y of the entire channel in common source configuration, the different elements of the small signal equivalent circuit in such a configuration are calculated using these formulations: 2 ! IðY12 Þ RðY12 Þ Cgd ¼ 1þ ðC:1Þ 2x IðY12 Þ
Rgd ¼
RðY12 Þ IðY12 Þ Cgd x
ðC:2Þ
½CZ0 s ¼ ½CZs þ 4 k Ta Df Rg þ Rs Rs Rs Rd þ Rs
ðD:2Þ
where CZs is the noise correlation matrix associated to the impedance matrix Zs , and is calculated from Cys using Eq. (11). Next, we take into account the parasitic capacitances using: 0 j Cpg x 00 0 ½Ys ¼ ½Ys þ ðD:3Þ 0 j Cpd x
ðC:4Þ
where Ys0 is the admittance matrix, calculated from the impedance matrix Zs0 . Cpg and Cpd are respectively the gate and drain parasitic capacitances. As the electrical behavior of the device changes, we must calculate the associated noise correlation matrix CYs0 using Eq. (11). Next, we consider the two last extrinsic elements which are the gate and drain parasitic self Lg and Ld with:
IðY22 Þ þ IðY12 Þ Cds ¼ 2x
ðC:5Þ
½Zs000 ¼ ½Zs00 þ
Gd ¼ RðY22 Þ þ RðY12 Þ
ðC:6Þ
where Zs00 is the impedance matrix, calculated from the admittance matrix Ys00 using Eq. (11). One more time, we must calculate the associated noise correlation CZs00 using Eq. (11). Finally, we transform the impedance matrix Zs000 into the chain matrix CH0s using Table 1 and we calculate its associated noise correlation matrix Ca0s using Table 2.
IðY11 Þ þ IðY12 Þ 1þ Cgs ¼ 2x
RðY11 Þ þ RðY12 Þ IðY11 Þ þ IðY12 Þ
2 !
ðC:3Þ Ri ¼
1 RðY11 Þ þ RðY12 Þ 2 x IðY11 Þ þ IðY12 Þ
RðY11 Þ þ RðY12 Þ Gm ¼ ðY21 Y12 Þ 1 þ j IðY Þ þ IðY Þ 11
s¼
ðC:7Þ
12
1 RðY11 Þ þ RðY12 Þ angle ðY21 Y12 Þ 1 þ j 2x IðY11 Þ þ IðY12 Þ
j Lg x 0 0 j Ld x
ðD:4Þ
ðC:8Þ References Appendix D. Completion of the noisy equivalent smallsignal circuit with the extrinsic elements To calculate the noise performances of the component, we have to take into account its extrinsic elements such as its noisy access resistances. Considering the Impedance matrix Zs , calculated from the Admittance matrix Ys using Table 1, the access resistances and the source parasitic self are taken into account using: Rg þ Rs þ j Ls x Rs þ j Ls x ½Zs0 ¼ ½Zs þ Rs þ j Ls x Rd þ Rs þ j Ls x ðD:1Þ where Rg , Rs and Rd are respectively the gate, source and drain access resistance and Ls is the parasitic source self. As the access resistances are noisy elements, the excess noise is given by:
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