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Scaling behavior of sub-micron MOSFETs on fully depleted SOI
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Solid-State Electronics Vol. 39, No. 4, pp. 445~,54, 1996 Copyright © 1996 Elsevier Science Ltd 0038-1101(95)00168-9 Printed in Great Britain. All rights reserved 0038-1101/96 $15.00+0.00
Pergamon
S C A L I N G B E H A V I O R OF S U B - M I C R O N MOSFETs ON F U L L Y D E P L E T E D SO1 NEAL KISTLER and JASON WOO University of California at Los Angeles, Department of Electrical Engineering, 56-147K Engineering IV, Los Angeles, CA 90024-1594, U.S.A. (Received 27 February 1995; in revisedform 16 May 1995) Abstract--Fully depleted silicon-on-insulator (SOl) MOSFETs offer a number of advantages over conventional bulk silicon transistors, making them attractive candidates for deep sub-micron low power electronics. In this paper, we present detailed characterization and analysis of the scaling behavior of fully depleted SOl MOSFETs down to quarter-micrometer channel lengths. Based on the consideration of transconductance, short channel effects, sub-threshold conduction and breakdown voltage, a scaling guideline for thin SOl devices is developed for 0.5 and 0.25 #m channel lengths in terms of silicon film thickness, channel doping, and channel length.
I. INTRODUCTION
Fully depleted silicon-on-insulator (SOl) MOSFETs offer a number of advantages compared to conventional bulk silicon MOSFETs, including improved short channel behavior and lower sub-threshold slope. It is important, however, to understand the detailed scaling behavior of the devices in order to facilitate future SO1 device design. Some questions which need to be addressed include the following. (i) Is there any change in performance as the film thickness is scaled down? (ii) Does the short channel behavior continue to improve as the film thickness is scaled down, and by how much? (iii) Is ultra-thin, lightly doped SOl suitable for 0.5~.25/~m operation? This paper presents a wide range of data on the performance and short channel behavior of thin SO1 MOSFETs. The performance (saturation transconductance, gmsat) is evaluated as the film and gate oxide thicknesses are varied. The short channel behavior in both the linear (VTr~) and sub-threshold regions [drain-induced barrier lowering (DIBL), S] of operation has been characterized in detail. The dependence on film thickness, channel doping, and channel length is discussed. The issues of low source-drain breakdown voltages, and threshold voltage control using alternative gate materials, are also relevant to the discussion of scaling behavior. Using the data on threshold voltage, short channel effects and breakdown voltage, the scaling limitations for FDSOI, are identified and some guidelines for device design at 0.5 and 0.25 #m channel lengths are presented.
2. DEVICESTRUCTURE In order to study the scaling behavior of the breakdown voltage in fully depleted SO1 n-MOSFETs,
transistors were fabricated with a wide range of SOI film thicknesses and channel dopings. The starting substrates were multiple-implant SIMOX wafers, and a conventional LOCOS-isolated process was used. A schematic cross section of the fully depleted SOl device is shown in Fig. 1. Selective deposition of tungsten was used to reduce the parasitic source/drain resistance, which can be problematic in thin SO1. The tungsten deposition does not consume silicon, thereby avoiding the problems associated with the complete silicidation of a thin SOl layer[I,2]. The starting SO1 film thickness was varied using thermal oxidation and wet etching. A field implant was included immediately prior to the LOCOS oxidation, to suppress any leakage along the device edges. Implantation of boron was used to dope the p-type channel region, such that final doping concentrations of 1 x 10tS, 1 x 1016, and 1 × 1017cm-3 were achieved. Dry oxidation was used to grow the 7 and 10 nm gate oxides, and 250 nm of undoped polysilicon was deposited to form the gate electrode. The gate electrodes were degenerately doped using arsenic implantation. A 100 nm oxide layer was subsequently deposited on the polysilicon for the purpose of isolating the gate electrode from the tungsten deposition. After the polyphotolithography, a photoresist ashing process[3] was used to reduce the line widths down to the 0.25 # m range. The oxide and poly layers were then etched sequentially in the same dry etching chamber, followed by a self-aligned arsenic implant (5 x 10~Scm-2) to dope the source/drain regions. After the source/drain implant anneal, oxide was deposited and anisotropically etched to form the 100 nm oxide spacer. Tungsten was selectively deposited on the source and drain silicon regions using a silane reduction process, so that the silicon in the 445
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Fig. 1. Cross section of the SOI MOSFET with selective deposition of tungsten on the source/drain and gate. SOI film was not consumed. Finally, AI/Si was used for the metallization. The transistors used in this study have effective channel lengths (Lo~) ranging from 0.25 to 10/xm, and channel widths of 8 #m. The effective channel lengths were electrically measured using a conventional technique[4]. After processing, the target SOI film thicknesses were 50, 100 and 150 nm. The actual film thicknesses were measured electrically using the technique in [5]. The buried oxide thickness is 350 nm in all cases. 3.0
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Some typical output characteristics for a fully depleted N M O S device are shown in Figs 2 and 3. The silicon film thickness is 95 nm and the channel doping is 1 x 1015cm -3 (no additional doping in the starting substrate). The effective channel length was electrically measured to be 0.91 #m. The output characteristics are well behaved out to the maximum gate and drain voltages of 3 V. However, because the gate electrode is n+-polysilicon and the channel doping is very light, the threshold voltage is below 0 V ( - 0 . 1 4 6 V ) . If an alternative gate material is used, such as p +-polySiGe[6], the threshold voltage of this structure could be adjusted to 0.5 V. The IDs--V6s characteristics (Fig. 3) exhibit very good sub-threshold slope and low off-state leakage. The sub-threshold slopes at lids = 0.1 and 2.0 V are both 65-67mV/decade. This near-ideal sub-threshold slope is a result of the SO1 film being fully depleted for the full range of Vos values. Typical fully depleted SO1 P M O S output characteristics are shown in Figs 4 and 5. The silicon film thickness is also 95 nm, and the channel doping is 1 x 1015cm -3 p-type (no additional doping in the starting substrate). Because the channel doping is
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Scaling behavior of sub-micron MOSFETs p-type, this device operates in the accumulation mode. When the device is off, the SOI film is fully depleted. Then, when the gate voltage is increased (negative), the depletion region shrinks and conduction occurs below the surface. The effective channel length was electrically measured to be 0.72 #m. The threshold voltage of this PMOS device is - 1 . 0 5 V, due to the n ÷-polysilicon gate. The threshold voltage can be reduced by increasing the p-type dopant in the channel, or by using an alternative gate material such as p+-polySiGe mentioned above. As with the NMOS devices, the PMOS IDs--VGs characteristics (Fig. 5) exhibit very good sub-threshold slopes (66-67 mV/decade) and low off-state leakage. 3. SATURATIONTRANSCONDUCTANCE It is important to understand the performance of the SOI MOSFET as the silicon film thickness is scaled down, including channel length, in order to choose the optimal design thickness for deep submicron devices. The transconductance has been studied for SOI n-MOSFETs with varying film thickness, channel doping, and gate oxide thickness. Figure 6 shows the measured transconductance of a variety of lightly-doped, fully-depleted SOI MOSFETs. For 10nm gate oxide devices, the transconductance does not vary much with film thickness. This is expected, since the transconductancc is proportional to mobility, which varies only slightly with film thickness[7]. At very short channel lengths, the transconductance can be limited by velocity saturation, which should also be independent of film thickness. The transconductance values for SOI MOSFETs with 7.5 nm gate oxide are about 35% higher than the thicker oxide values. This is consistent with the fact that gm OCCo~, so that the improvement is expected to be ,~ 10/7.5 = 33%. Transconductance data for SOI MOSFETs with heavier channel doping are shown in Fig. 7. At this doping level, the 42 nm thick SOI is fully depleted, but the 99 nm film is not quite fully depleted. Accord-
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Fig. 7. Saturation transconductance of SOl n-MOSFETs with N, = 1 x 10'7 cm-3, Tsi = 42 and 99 nm and Tox= 10nm. ing to the figure, the thinner SO1 devices apparently exhibit lower transconductance values than the thicker SO1. However, this is not due to any intrinsic change in device behavior, but rather to the effect of parasitic series resistance. The series resistance has been extracted from the device I - V characteristics, using a conventional method[4]. The total extrinsic resistance of the devices in the 42 and 99 nm films is 4.56 and 1.26kD vm, respectively. The measured transconductance data can be corrected for the external series resistance using: g~t
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where g~t is the intrinsic transconductance, g~t is the extrinsic (measured) transconductance, and Rs is the source parasitic resistance, which is assumed to be half the total measured resistance. The data in Fig. 7 are re-plotted in Fig. 8, corrected for the source resistance. Again, there is apparently little variation in device performance as the film thickness is varied. The relatively high values of parasitic resistance in some of the SOI devices is in part due to the resistance of the non-silicided SOI layer (underneath the spacer
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Fig. 6. Saturation transconductance of fully depleted SOI n-MOSFETs with Na = 1 x 10'5 cm-3, Tsi = 46-150 nm and Tox= 7.5 and l0 rim.
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Fig. 8. Saturation transconductance of SOl n-MOSFETs, corrected for external parasitic resistance. N~= I x l0 '7 cm -3, Tsi = 42 and 99 nm and Tox= l0 nm.
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Fig. 9. Threshold voltage roll-off vs effective channel length for FDSOI NMOS devices with N~= 1 x 1015cm -3 and Tsl = 46, 95 and 142 nm.
Fig. 11. Threshold voltage roll-off vs effective channel length for SOl devices with N~= 1 x 1017cm -3 and Ts, = 4 2 and 99 nm.
oxide). However, the resistance is primarily attributed to the TiSi2/Si interface[I,2], or the selective W/Si interface, depending on the process used. These resistances can be reduced with appropriate modification and optimization of the process flow. In addition, other processes may be used with SO1 to achieve low parasiuc resistance values, including cobalt silicide[8].
gate electrode. In this case, the behavior is very similar to that of n +-polysilicon gate NMOSFETs. To illustrate the short channel behavior of the devices with different SOl thicknesses and channel doping, the short channel VxH roll-off relative to 10/~m long devices is shown in Figs 9-11. Figure 9 shows the data for FDSOI devices with 1 x 1015cm -3 channel doping. A clear improvement is observed as the film thickness is reduced. The reduction of short channel VTH roll-off with decreasing film thickness is a result of the reduced amount of charge sharing in a thinner film. Just as the charge sharing is reduced (and short channel behavior improves) in fully depleted SOl compared to bulk devices[9], the charge sharing is limited even more as the film thickness is scaled down. Similar behavior is observed for a channel doping of 1 x 10~6cm -3 (Fig. 10). The VTH roll-off for some SO1 devices with a thinner gate oxide is also plotted in Fig. 10. Some reduction is observed compared to the thicker oxide devices with similar film thickness, as expected. Finally, Fig. 11 shows the VXH roll-off for N a = 1 × 1017cm -3, for film thicknesses of 42 and 99 nm. The amount of VxH roll-off is higher than for lighter-doped devices, owing to increased charge sharing when N~ is increased. However, the dependence of VT. roll-off on film thickness is less clear, at
4. SHORT CHANNEL BEHAVIOR
4.1. Linear region threshold t,oltage The linear region threshold voltage, V+., is determined from the extrapolated IDS VS V~s characteristic at low drain bias (0.1 V). Again, for the case of low channel doping, alternative gate materials can be used (p+-polysilicon, p+-polySiGe) to adjust the threshold voltage to the desired value of ~0.5 V. In the case of n + polysilicon gate, the channel doping of the nMOSFET needs to be high ( ~ 1017 for an SOl thickness of 100 nm), while the p M O S F E T will be heavily doped in the accumulation mode (p-doped channel) to give correct threshold voltages. Alternatively, the p M O S F E T can use p +-polysilicon as the 200 1 I SOl NMOS Tox=10nm ~ ir U-
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Fig. 10. Threshold voltage roll-offvs effective channel length for FDSOI devices with Nd = 1 x 10J6cm -3 and Tsl = 43, 94 and 146 nm.
VG Fig. 12. Schematic illustration of DIBL measurement technique and definition of VD~B,.
Scaling behavior of sub-micron MOSFETs least for this range of Ts~. It is expected that thicker films will exhibit higher values of VTH roll-off, since the film will no longer be fully depleted. The 99 nm thick devices are actually on the edge of full/partial depletion at this doping level, and exhibit a saturation region kink.
4.2. Dram-induced barrier lowering The drain-induced barrier lowering (DIBL) has been characterized in SOl MOSFETs with various film thicknesses and channel doping. The DIBL in a given device is measured at a constant normalized sub-threshold current level, as shown in Fig. 12. The quantity VDmL is defined as the shift in gate voltage required to reach a specified current level when the drain voltage is increased from a low drain bias (0.1 V) to a higher drain bias (Von). The DIBL varies approximately linearly with drain bias up to the punch-through or breakdown point. In order to consistently compare the various SO1 devices, VDmL was measured at a maximum drain voltage of 2.0 V. This drain bias was chosen because it is in the fight range for a future low-voltage power supply, and because the breakdown voltages of most devices studied were above 2.0 V. The drain-induced barrier lowering for FDSOI nMOSFETs with near-intrinsic channel doping (1 x 1015cm-3) is shown in Fig. 13. A significant reduction in DIBL is observed as the film thickness is reduced from 142 to 95 to 46 nm. As Tsi is reduced, the source and drain electric fields fringe more strongly toward the substrate, so that they have less effect on the potential in the channel region. Hence, the gate maintains better control over the SO1 film potential, especially near the back Si/SiO2 interface, and less DIBL is observed. The drain-induced barrier lowering values for 100 nm thick FDSOI MOSFETs with 7.5nm gate oxide are also shown in Fig. 13. Comparing the ~ 100 nm SOl results, devices with the thinner gate oxide show reduced DIBL. This is due to the stronger capacitive coupling of the film potential to the applied gate voltage in the thinner oxide case. Similar behavior of VO]BL with channel
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length and Tsi is observed when the channel doping is increased to 1 x 1016cm-3. DIBL results for 42 and 99 nm SO1 devices with 1 x 1017cm -3 channel doping are plotted in Fig. 14. The ultra-thin (42 nm) SOl devices exhibit good short channel DIBL behavior, as with the previous sets of data, but the thicker SO1 devices exhibit very high DIBL values, and no clear trend with channel length. At this doping level, the 99 nm SO1 is partially depleted, so that the devices exhibit a saturation region kink as well as an anomalously steep subthreshold slope at higher drain bias. Both the output kink and steep sub-threshold slope are a result of the floating body effects and threshold voltage modulation in partially depleted devices[10-12]. As a consequence of these floating body effects, the measured DIBL at VDS= 2 V is very high. At a low enough drain bias ( ~ 1 V), impact ionizations, and hence the floating body effects, are minimized, and the DIBL reduces to acceptable values. Figure 15 compares fully depleted, ultra-thin SOI MOSFETs with channel doping ranging from 1 x 1015 to 1 x 10lTcm-3. For this range of channel doping, there is apparently little dependence of the drain-induced barrier lowering on the doping. ,
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Fig. 14. Measured DIBL, VDtBL, for SOl devices with N a = I × 1017cm -3. The 99 nm thick film is partially depleted at this doping level.
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Fig. 13. Measured DIBL, V D I B L , for fully depleted SO1 devices with N. = 1 x 101~cm-3.
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,
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Fig. 15. Measured DIBL, VD[BL, for ultra-thin FDSO1 devices with N, = 1 x 1015-1 x 1017cm-3.
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Fig. 16. Measured sub-threshold slope f o r F D S O I N M O S devices w i t h N . = I x 10 ~5cm -3.
However, the minimum channel length (before punch-through sets in) can be decreased slightly by increasing the doping from l0 is to 1017cm -3. Decreasing the power supply voltage will also reduce the D I B L and allow shorter channel lengths at lighter doping levels.
4.3. Sub-threshold slope The sub-threshold slope of each device was measured from the /Ds--Vos characteristics with low applied drain bias (0.1 V). The measured subthreshold slope for N M O S SOI devices, S, is presented in Figs 16-18. The long channel values o r s for fully depleted devices are all very close to the ideal value of 60 mV/decade as a result of the very small capacitance of the buried oxide. On the other hand, for 9 9 n m SOI with 1 x 1017cm -3 channel doping (partially depleted), the long channel S values are in the range 80-90 mV/decade, which is typical for bulk Si M O S F E T s . At short channel lengths, the sub-threshold slope of the SOI devices increase significantly, as with bulk Si devices, owing to the effects of D I B L on the sub-threshold current flow. It can be clearly observed in Fig. 16 that the short channel sub-threshold slope is significantly improved as the SOI film thickness is
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Fig. 18. Measured sub-threshold slope for SOl NMOS devices with N, = 1 x 1017cm-3. The 99 nm thick devices are partially depleted at this doping level. reduced. This is a direct result of the improved resistance to D I B L as Ts~ is scaled. In addition, the use of a thinner gate oxide (7.5 nm) results in better short channel sub-threshold slopes due to stronger front gate capacitive coupling. Comparing devices with different doping levels but similar film thicknesses (Fig. 19), only a slight improvement in the short channel sub-threshold slope can be observed as doping is increased to 1 x 1017cm -3. This is consistent with the slightly improved D I B L behavior in the heavier-doped film, as discussed earlier.
5. BREAKDOWN VOLTAGE
It is well known that a significant problem in thin SOI device design is the low N M O S source-to-drain breakdown voltages, compared to bulk transistors. In order to provide a guideline for SOI thickness scaling, a good understanding and model of the breakdown voltage is needed, taking into consideration a range of SOI film thicknesses, channel dopings and channel lengths. We have reported detailed characterization results of the breakdown behavior in various SOI n M O S F E T structures[13]. It has been found that, at ~" 120
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Fig. 17. Measured sub-threshold slope for FDSOI NMOS devices with N d = 1 x 10t6cm -3.
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Scaling behavior of sub-micron MOSFETs
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Fig. 20. Measured breakdown voltage vs effective channel length for SO1 devices with Tsi = 46, 95 and 142 nm, and Na = 1 x 10~5c m -3. A reduction in VBDwith decreasing film thickness is apparent at longer channel lengths. At channel lengths below 0.5 #m, the breakdown voltage increases as film thickness is reduced.
deep sub-micrometer channel lengths, thinner SO1 films can give higher breakdown voltages due to the improved punch-through resistance of these films. Figure 20 shows VBD VS Le~ for three SO1 film thicknesses with 1 x 1015cm 3 channel doping. Breakdown due to punch-through is indicated by a filled data point[13]. At longer channel lengths (>_2/~m), VBo decreases significantly as the film thickness is reduced from 150 to 95 nm. This is due to the increase in lateral electric field, and hence impact ionization as the SO1 film is thinned[14,15]. The increased impact ionization results in earlier triggering of the parasitic bipolar mechanism, and hence lower VBD.However, the measured breakdown voltage does not vary as significantly for film thicknesses less than 100nm. This may be a result of increased impact ionization compensated by lower parasitic bipolar gain as the SO1 film becomes very thin, as discussed in [16]. On the other hand, behavior of the breakdown voltage at channel lengths below 2 # m varies significantly as the film thickness is varied. Breakdown voltage in all SO1 film thicknesses reduces with decreasing channel length, due to higher electric fields and parasitic bipolar gain; however, the amount of V~Droll-off is reduced as the film thickness is reduced. This improvement in the short-channel VSD behavior is a result of improved resistance to DIBL effects as the SOl film thickness is reduced[13,17]. As a result of the reduced FaD roll-off, the ultra-thin (46 nm) SOI devices actually exhibit higher VBD values than the 95nm thick devices for L e ~ l # m and below (Fig. 20). The thicker film (142nm) devices suffer from punch-through at channel lengths below about 0.8 vm, making them unsuitable for 0.5 or 0.25/~m channel lengths. VaD values for 42 and 99 nm thick SO1 devices with N~ = 1 x 10tTcm -3 are shown in Fig. 21. Note that at a doping of 1 x 1017cm -3, the 99 nm SOl is actually near the transition of being fully/partially depleted
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3 j o ~ o Tsi = 99 nm O Tsi = 42 nm £3 2 < LU rr I rn 0.0 0.5 10 1.5 2.0 EFFECTIVE CHANNEL LENGTH (~tm)
Fig. 21. Measured breakdown voltage vs effective channel length for SO1 devices with Ts~=42 and 99nm, and N~= 1 x 1017cm 3. The 99 nm film is partially depleted at this doping level.
under normal operating conditions (these devices do exhibit a "kink" in the saturation region of the output characteristics, indicative of partial depletion). In these films, punch-through and DIBL effects are prevented by the heavier channel doping, so that there is little dependence of V B D o n film thickness. As a result, the SO1 film thickness is not critical for maintaining good breakdown voltage in devices which use n +-polysilicon gates and doping in the range 1-5 x 1027cm -3 (depending on the film thickness and desired VTn). However, ultra-thin films ( ~ 50 nm) will be needed if pure fully depleted operation (i.e. fully depleted at zero gate bias) is desired. A comparison of three different doping conditions in a fixed SO1 film thickness is given in Fig. 22. The breakdown voltage at a given channel length can be increased to the order of 1 V as the doping increases from 10~5 to 10]7cm -3. In addition, the minimum channel length without punch-through can be reduced from 0.5/tm to below 0.25 #m. Both of these effects are a result of the higher channel doping counteracting the sub-surface DIBL and punchthrough at shorter channel lengths.
>6
,
r
ILl
TSi = 100 nm
~--.
> z 3 0 a
2
/-~
O~O N-a--- 1X10! 6 cm "3
,/ ~-~N~ -- l~l°~scm-~ < 1 LU rr 0 ~ ~ ,__J CO 0.0 0.5 1.0 1.5 2.0 EFFECTIVE CHANNEL LENGTH (l~m)
Fig. 22. Measured breakdown voltage vs effective channel length for 100 nm SOl films with I x 10~5, 1 x 10r~ and 1 x 1017 c m -3 channel dopings. The devices with 1017cm -3 doping are partially depleted at this doping level.
452
N. Kistler and J. Woo
It is apparent from Figs 20--22 that heavier doping will always provide better breakdown voltages and shorter minimum channel lengths in SOl devices. However, as the doping level increases, the film thickness range for fully depleted operation will become very limited, and heavily doped fully depleted devices can have threshold voltage variations[5]. On the other hand, lightly doped films can provide reasonable breakdown voltages as long as the film thickness is scaled to prevent punch-through. The use of LDD has also been suggested to increase the breakdown voltage. However, LDD should only increase VBD by about 0.5-1 V. Therefore, power supply voltages will still be well below 5 and even 3.3 V. In addition, an LDD region will introduce additional series resistance, which may be especially high in thin SO1, so that a trade-off in lower performance will exist. 6. SCALING GUIDELINES One of the goals of studying the short channel scaling behavior of FDSOI MOSFETs is to provide some guidelines for device design, and to indicate the probable limitations as we scale the devices to 0.25 #m. The threshold voltage requirement places boundaries on the usable film thickness and channel doping, and these boundaries depend on the gate material used and whether fully or partially depleted operation is desired. The target threshold voltage for 0.25~).5 itm MOSFETs is expected to be in the range 0.4-0.6V. This threshold voltage range can be mapped to an SO1 film doping film thickness design space. Figure 23 illustrates the resulting design space, assuming either an n ÷-polysilicon or p ÷-polySiGe gate electrode. The results shown are for NMOS. Similar curves exist for p+-polysilicon and p+polySiGe gate PMOS. For the case of an n +polysilicon gate, there is a narrow design region between the VxH=0.4 and 0.6V curves, with relatively thin SOl ( < 70 nm for fully depleted) and heavy doping ( > 1017cm 3) being necessary. For the p+-polySiGe gate NMOS, a VrH of 0.5-0.6 V can be achieved with light doping and a wide range of film thicknesses (owing to the work function of the SiGe gate, the long channel Vva is always above 0.4 V). Also plotted in Fig. 23 is the maximum depletion width, Xd. . . . vs doping, to indicate where the fully
200
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i
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=E" 150
~?
Xdrnax
¢/) t.l.I
100 "lk"-
~,
50
O0~s
1016 10 ~7 CHANNEL DOPING (cm "3)
10TM
Fig. 23. Simulated SOl film thickness channel doping design space, assuming long channel NMOS threshold voltages of 0.4 and 0.6V and either n+-polysilicon or p+-polySiGe gates. Tox= 7 nm in all simulations.
depleted condition is satisfied. At film thicknesses and channel dopings below this curve, the devices will be fully depleted when the gate voltage is above the threshold voltage. However, the devices may not be fully depleted in weak inversion, which is necessary to achieve the near-ideal sub-threshold slopes. This condition will be satisfied if Tsi < 0.7 x X d . . . . which is the depletion width when the potential drop in the film is only half of the potential drop in strong inversion. The curve of 0.7 x ~'dmaxVS doping is also shown in Fig. 23. This more restrictive condition for fully depleted operation significantly reduces the design space when n +-polysilicon gates are used. The maximum allowable power supply voltage for a given structure will be limited by the punchthrough- or bipolar-induced breakdown of the SO! device. The breakdown voltage characterization data are summarized in Table 1. These data are presented in two groups: (i) devices with channel doping of 1 × 1015-1 × 1016cm 3, and (ii) devices with 1 × 1017 channel doping. The data for the first group are representative of devices with light channel doping which employ the p÷-polySiGe gate, or similar mid-gap gate material, to achieve the proper threshold voltage. The second set of data represent the case of the conventional, n+-polysilicon gate NMOS with heavier doping needed for threshold voltage adjustment. Whether the breakdown is caused by punch-through or DIBL, or a combination
Table 1. Breakdown voltage ranges for lightly doped (1 × 10 t~ I × 1016cm 3) and heavily doped (1 x 1017cm 5) SOl N M O S at 0.25 and 0.5 # m channel lengths. The dominant cause o f the breakdown is indicated in each case Heavily doped SOl with n ÷-polysilicon gate
Lightly doped SOl with p +-polySiGegate L = 0.25 #m
L =0.5#m
Ts~ = 50 n m
1.9-2.2 Latch
2.8-2.95 Latch
Tsi = 100 nm
1.4-1.88 Punch-through
2.28-2.87 Latch/punch-through
Tsi = 150 n m
0.5 Punch-through
2.07-4.4 Latch/punch-through
L =0.25,um
L = 0.5#m
Ts~ = 50 n m
2.81 Latch
3.2 Latch
Tsi = I00 n m
2.83 Latch
3.3 I Latch
453
Scaling behavior of sub-micron MOSFETs Table 2. Summaryof scalinglimitationsfor 0.5 and 0.25#m SOl MOSFETs,assumingp +-polySiGeor n +-polysilicongate designregions Heavy doping Light dopingp +-polySiGegate n +-polysilieongate Lcfr= 0.5 #m 50 nm SO1 neededto preventpunch-through No punch-through Fully depleted ~ 50 nm SO1 for FD r ' ~x v~,~;~ 2 v
Left= 0.25#m
< 100 mV DIBL S < 70 mV/decade
< 100 mV DIBL if FD S < 70 mV/decade if FD
50 nm SOI needed to prevent punch-through Fully depleted C ~ 1V < 100 mV DIBL S < 100 mV/decade
No punch-through ~ 50 nm SOI for FD V~ ~ 2 V ~ 100 mV DIBL if FD S ~ 70 mV/decade if FD
of both, is also indicated for each channel length/thickness combination. When using this data to predict the allowable power supply voltage, a reasonable criteria of approx. 1 V margin between VDD and VBD is used. The drain-induced barrier lowering is another factor which needs consideration in the scaling guideline. A criterion of _<100 mV of DIBL at the given power supply voltage is used. Table 2 summarizes the characteristics of SO1 devices in the four possible design regions. First, a target Left of 0.5 p m is considered. For the lightly doped case (see Table 1), the film thickness must be in the range of 50 nm to prevent punch-through at this channel length. At the heavier doping level, punch-through is suppressed. On the other hand, the heavily doped SO1 must be very thin to maintain full depletion ( ~ 5 0 n m for N~ = 3 x 1017cm-3). Because the latching voltages of 50 nm thick devices are about 3 V, the power supply voltage should be in the range of 2 V in both cases. In these thin films the DIBL values are within the 100mV requirement, and the sub-threshold slopes are excellent ( < 70 mV/decade). Partially depleted operation may also be considered if the higher DIBL and sub-threshold slope can be tolerated, or if the power supply is reduced below the "kink" voltage. The second set of results in Table 2 is for the target Leer of 0.25 #m. As with the Leer = 0.5/am case, the lightly doped SO1 must be in the range of 50 nm to prevent punch-through, while the heavily doped SOl still exhibits no punch-through at either film thickness tested. At this short channel length, the latching voltage of the 50 nm SOl with light doping is near 2 V, while for the heavier-doped SO1 it is still close to 3 V. As a result, the power supply voltage of lightly doped SO1 must be scaled down to the 1 V range. At this lower voltage, the measured DIBL can still meet the 100 mV criteria, and the sub-threshold slope is below 100mV/decade. The heavily doped SOl exhibits about 100 mV of DIBL and excellent subthreshold slope at this channel length. It should be noted that the data used for this analysis is taken from the SOICMOS with 10nm gate oxide. Additional improvements can be obtained at 0.25 # m channel lengths if the gate oxide is further scaled, as seen in the data from 100 nm SOI devices with 7.5 nm
gate oxide (presented earlier in this section). It is expected that a combination of ~ 50 nm SO1 and ~ T n m gate oxide will provide excellent device characteristics in the 0.25#m range. In addition, proper source/drain engineering can be used to further improve the short channel effects as well as punch-through. With thinner oxide and source/drain engineering, we expect that ~ 0.1 pm CMOS on very thin SOI ( < 500/~) can be very attractive for low power applications.
7. CONCLUSION
In this paper, detailed characterization of MOSFETs on SIMOX with different channel dopings and SOI thicknesses was presented. It was found that while the transconductance (and therefore current drive) does not depend significantly on the thickness, short channel effects, sub-threshold current slopes and breakdown voltage show strong dependence on both SOI thickness and the channel doping. Scaling guidelines for 0.5 and 0.25 #m devices were developed using these data. It was found that, using lightly doped SOI with a p +-polySiGe gate, channel lengths in the 0.25pm range are achievable with aggressive scaling of the film thickness and gate oxide thickness for low voltage ( ~ 1 V) applications. However, Tsi scaling below 50 nm will become exceedingly difficult. Therefore, to reach channel lengths approaching 0.1 pm, it will require very thin gate oxide ( ~ 5 nm) and proper source/drain engineering. Such devices will also allow higher power supply voltages, in the range of 2 V, which will be desirable for some analog applications, and for higher current drive and speed for some digital applications. Based on these considerations, sub-quarter micron CMOS on SOl show great promise for low power applications.
REFERENCES
I. Y. Yamaguchi, T. Nishimura, Y. Akasaka and K. Fujibayashi, IEEE Trans. Electron Devices 39, 1179 0992). 2. J. Foerstner, J. Jones, M. Huang, B.-Y. Hwang, M. Racanelli, J. Tsao and N. D. Theodore, IEEE Int. SOl Conf. Proc., p. 86 (1993).
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3. J. Chung, M.-C. Jeng, J. E. Moon, A. T. Wu, T. Y. Chan, P. K. Ko and C. Hu, IEEE Electron Device Left. 9, 186 (1988). 4. J. G. J. Chern, P. Chang, R. F. Motta and N. Godinho, IEEE Electron Device Lett. 1, 170 (1980). 5. J. Chen, R. Solomon, T.-Y. Chan, P.-K. Ko and C. Hu, IEEE Electron Device Lett. 12, 453 (1991). 6. N. Kistler and J. Woo, I E D M Tech. Dig., p. 727 (1993). 7. J. Wang, N. Kistler, J. Woo and C. R. Viswanathan, IEEE Electron Device Lett. Submitted. 8. L. T. Su, M. J. Sherony, H. Hu, J. E. Chung and D. A. Antoniadis, I E D M Tech. Dig., p. 723 (1993). 9. J. P. Colinge and T. I. Kamins, Electron. Lett. 23, 1162 (1987). 10. J. P. Colinge, IEEE Electron Device Lett. EDL-9, 97 (1988).
11. S. P. Edwards, K. J. Yallup and K. M. De Meyer, IEEE Trans. Electron Devices 35, 1012 (1988). 12. J. R. Davis, A. E. Glaccum, K. Reeson and P. L. F. Hemment, IEEE Electron Device Lett. EDL-7, 570 (1986). 13. N. Kistler and J. Woo, IEEE Trans. Electron Devices 41, 1217 (1994). 14. J. G. Fossum, J.-Y. Choi and R. Sundaresan, IEEE Trans. Electron Devices 37, 724 (1990). 15. M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi and K. Natori, 1EEE Trans. Electron Devices 37, 2015 (1990). 16. J.-Y. Choi and J. G. Fossum, IEEE Trans. Electron Devices 38, 1384 (1991). 17. N. Kistler, E. Ver Ploeg, J. Woo and J. Plummer, IEEE Int. SO1 Conf. Proc., p. 128 (1992).
Solid-State Electronics Vol. 39, No. 4, pp. 445~,54, 1996 Copyright © 1996 Elsevier Science Ltd 0038-1101(95)00168-9 Printed in Great Britain. All rights reserved 0038-1101/96 $15.00+0.00
Pergamon
S C A L I N G B E H A V I O R OF S U B - M I C R O N MOSFETs ON F U L L Y D E P L E T E D SO1 NEAL KISTLER and JASON WOO University of California at Los Angeles, Department of Electrical Engineering, 56-147K Engineering IV, Los Angeles, CA 90024-1594, U.S.A. (Received 27 February 1995; in revisedform 16 May 1995) Abstract--Fully depleted silicon-on-insulator (SOl) MOSFETs offer a number of advantages over conventional bulk silicon transistors, making them attractive candidates for deep sub-micron low power electronics. In this paper, we present detailed characterization and analysis of the scaling behavior of fully depleted SOl MOSFETs down to quarter-micrometer channel lengths. Based on the consideration of transconductance, short channel effects, sub-threshold conduction and breakdown voltage, a scaling guideline for thin SOl devices is developed for 0.5 and 0.25 #m channel lengths in terms of silicon film thickness, channel doping, and channel length.
I. INTRODUCTION
Fully depleted silicon-on-insulator (SOl) MOSFETs offer a number of advantages compared to conventional bulk silicon MOSFETs, including improved short channel behavior and lower sub-threshold slope. It is important, however, to understand the detailed scaling behavior of the devices in order to facilitate future SO1 device design. Some questions which need to be addressed include the following. (i) Is there any change in performance as the film thickness is scaled down? (ii) Does the short channel behavior continue to improve as the film thickness is scaled down, and by how much? (iii) Is ultra-thin, lightly doped SOl suitable for 0.5~.25/~m operation? This paper presents a wide range of data on the performance and short channel behavior of thin SO1 MOSFETs. The performance (saturation transconductance, gmsat) is evaluated as the film and gate oxide thicknesses are varied. The short channel behavior in both the linear (VTr~) and sub-threshold regions [drain-induced barrier lowering (DIBL), S] of operation has been characterized in detail. The dependence on film thickness, channel doping, and channel length is discussed. The issues of low source-drain breakdown voltages, and threshold voltage control using alternative gate materials, are also relevant to the discussion of scaling behavior. Using the data on threshold voltage, short channel effects and breakdown voltage, the scaling limitations for FDSOI, are identified and some guidelines for device design at 0.5 and 0.25 #m channel lengths are presented.
2. DEVICESTRUCTURE In order to study the scaling behavior of the breakdown voltage in fully depleted SO1 n-MOSFETs,
transistors were fabricated with a wide range of SOI film thicknesses and channel dopings. The starting substrates were multiple-implant SIMOX wafers, and a conventional LOCOS-isolated process was used. A schematic cross section of the fully depleted SOl device is shown in Fig. 1. Selective deposition of tungsten was used to reduce the parasitic source/drain resistance, which can be problematic in thin SO1. The tungsten deposition does not consume silicon, thereby avoiding the problems associated with the complete silicidation of a thin SOl layer[I,2]. The starting SO1 film thickness was varied using thermal oxidation and wet etching. A field implant was included immediately prior to the LOCOS oxidation, to suppress any leakage along the device edges. Implantation of boron was used to dope the p-type channel region, such that final doping concentrations of 1 x 10tS, 1 x 1016, and 1 × 1017cm-3 were achieved. Dry oxidation was used to grow the 7 and 10 nm gate oxides, and 250 nm of undoped polysilicon was deposited to form the gate electrode. The gate electrodes were degenerately doped using arsenic implantation. A 100 nm oxide layer was subsequently deposited on the polysilicon for the purpose of isolating the gate electrode from the tungsten deposition. After the polyphotolithography, a photoresist ashing process[3] was used to reduce the line widths down to the 0.25 # m range. The oxide and poly layers were then etched sequentially in the same dry etching chamber, followed by a self-aligned arsenic implant (5 x 10~Scm-2) to dope the source/drain regions. After the source/drain implant anneal, oxide was deposited and anisotropically etched to form the 100 nm oxide spacer. Tungsten was selectively deposited on the source and drain silicon regions using a silane reduction process, so that the silicon in the 445
446
N. Kistler and J. Woo
Oxide ~
W
-1.0
~:acer
PMOS Tsi=95nm Tox=10nm Na=l E15/cm3 Leff=O.72um
__ ~"
g
-0.8
I-.•
.
."
"+ i
i
Buried Oxide
z iii rr n,"
-0.6
o z < rr c~
-0.4
Vgs=-3~)V
-2.5V
-2.0V -0.2
-1.5V
Fig. 1. Cross section of the SOI MOSFET with selective deposition of tungsten on the source/drain and gate. SOI film was not consumed. Finally, AI/Si was used for the metallization. The transistors used in this study have effective channel lengths (Lo~) ranging from 0.25 to 10/xm, and channel widths of 8 #m. The effective channel lengths were electrically measured using a conventional technique[4]. After processing, the target SOI film thicknesses were 50, 100 and 150 nm. The actual film thicknesses were measured electrically using the technique in [5]. The buried oxide thickness is 350 nm in all cases. 3.0
NMOS
V g s = 3 . 0 y ~ ~
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t - 2.0 z iii
~ ~
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~
~ J
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0.0
1
2
DRAIN V O L T A G E (V)
Fig. 2. Drain current vs drain voltage characteristics of a fully depleted SO1 NMOS device. Ts~= 95 nm, N, = 1 x 10~Scm-3 and L,~ = 0.91/am.
0.0
i
Some typical output characteristics for a fully depleted N M O S device are shown in Figs 2 and 3. The silicon film thickness is 95 nm and the channel doping is 1 x 1015cm -3 (no additional doping in the starting substrate). The effective channel length was electrically measured to be 0.91 #m. The output characteristics are well behaved out to the maximum gate and drain voltages of 3 V. However, because the gate electrode is n+-polysilicon and the channel doping is very light, the threshold voltage is below 0 V ( - 0 . 1 4 6 V ) . If an alternative gate material is used, such as p +-polySiGe[6], the threshold voltage of this structure could be adjusted to 0.5 V. The IDs--V6s characteristics (Fig. 3) exhibit very good sub-threshold slope and low off-state leakage. The sub-threshold slopes at lids = 0.1 and 2.0 V are both 65-67mV/decade. This near-ideal sub-threshold slope is a result of the SO1 film being fully depleted for the full range of Vos values. Typical fully depleted SO1 P M O S output characteristics are shown in Figs 4 and 5. The silicon film thickness is also 95 nm, and the channel doping is 1 x 1015cm -3 p-type (no additional doping in the starting substrate). Because the channel doping is
.10 -2
1
10.4
Vds=2.0~
.10 4
!/fv°.,v
10 -°
m
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- 1 0 .6
~
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Vds=-2.0V
,
r~
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0 10.8 Z < a
-3
Fig. 4. Drain current vs drain voltage characteristics of a fully depleted SOl PMOS device. Tsi = 95 nm, N, = 1 x l0 ts cm -3 and Left= 0.72/am.
10 .2
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1040
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k -2
i
-1
0
ZO < --
a
2
[_
t
.104o L i
i
~
.10.8
3
GATE V O L T A G E (V)
Fig. 3. Drain current vs gate voltage characteristics of a fully depleted SOl NMOS device. Tsi = 95 nm, N, = 1 x 10~5cm -~ and L=fr= 0.91/am.
.1042 i 1
i
0
, i:
i
,
i
-1 -2 GATE V O L T A G E (V)
-3
Fig. 5. Drain current vs gate voltage characteristics of a fully depleted SO1 PMOS device. Tsi = 95 nm, Na = 1 x 10I~cm -~ and Lc~ = 0.72/am.
Scaling behavior of sub-micron MOSFETs p-type, this device operates in the accumulation mode. When the device is off, the SOI film is fully depleted. Then, when the gate voltage is increased (negative), the depletion region shrinks and conduction occurs below the surface. The effective channel length was electrically measured to be 0.72 #m. The threshold voltage of this PMOS device is - 1 . 0 5 V, due to the n ÷-polysilicon gate. The threshold voltage can be reduced by increasing the p-type dopant in the channel, or by using an alternative gate material such as p+-polySiGe mentioned above. As with the NMOS devices, the PMOS IDs--VGs characteristics (Fig. 5) exhibit very good sub-threshold slopes (66-67 mV/decade) and low off-state leakage. 3. SATURATIONTRANSCONDUCTANCE It is important to understand the performance of the SOI MOSFET as the silicon film thickness is scaled down, including channel length, in order to choose the optimal design thickness for deep submicron devices. The transconductance has been studied for SOI n-MOSFETs with varying film thickness, channel doping, and gate oxide thickness. Figure 6 shows the measured transconductance of a variety of lightly-doped, fully-depleted SOI MOSFETs. For 10nm gate oxide devices, the transconductance does not vary much with film thickness. This is expected, since the transconductancc is proportional to mobility, which varies only slightly with film thickness[7]. At very short channel lengths, the transconductance can be limited by velocity saturation, which should also be independent of film thickness. The transconductance values for SOI MOSFETs with 7.5 nm gate oxide are about 35% higher than the thicker oxide values. This is consistent with the fact that gm OCCo~, so that the improvement is expected to be ,~ 10/7.5 = 33%. Transconductance data for SOI MOSFETs with heavier channel doping are shown in Fig. 7. At this doping level, the 42 nm thick SOI is fully depleted, but the 99 nm film is not quite fully depleted. Accord-
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~
i
~ ~ ~
~
Z 150 O < FO
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~
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,
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150 100
Z O O
50
rr F-
{
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i
i
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Fig. 7. Saturation transconductance of SOl n-MOSFETs with N, = 1 x 10'7 cm-3, Tsi = 42 and 99 nm and Tox= 10nm. ing to the figure, the thinner SO1 devices apparently exhibit lower transconductance values than the thicker SO1. However, this is not due to any intrinsic change in device behavior, but rather to the effect of parasitic series resistance. The series resistance has been extracted from the device I - V characteristics, using a conventional method[4]. The total extrinsic resistance of the devices in the 42 and 99 nm films is 4.56 and 1.26kD vm, respectively. The measured transconductance data can be corrected for the external series resistance using: g~t
=
1
ext gm
1
- g i ne x t R~'
where g~t is the intrinsic transconductance, g~t is the extrinsic (measured) transconductance, and Rs is the source parasitic resistance, which is assumed to be half the total measured resistance. The data in Fig. 7 are re-plotted in Fig. 8, corrected for the source resistance. Again, there is apparently little variation in device performance as the film thickness is varied. The relatively high values of parasitic resistance in some of the SOI devices is in part due to the resistance of the non-silicided SOI layer (underneath the spacer
~ ~,
i
i
Na=1x1017cm "3
200 ~
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9
~
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,
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,
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I
{
{
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10
Fig. 6. Saturation transconductance of fully depleted SOI n-MOSFETs with Na = 1 x 10'5 cm-3, Tsi = 46-150 nm and Tox= 7.5 and l0 rim.
5O 0
--
,
i
I
i
i
2 4 6 8 EFFECTIVE CHANNEL LENGTH (urn)
10
Fig. 8. Saturation transconductance of SOl n-MOSFETs, corrected for external parasitic resistance. N~= I x l0 '7 cm -3, Tsi = 42 and 99 nm and Tox= l0 nm.
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200
i [ '
,
150 !
LL
LL
o
,© , ~) 100
u_
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,
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-t /
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\ \
~-] 50 >
1 2 3 4 EFFECTIVE CHANNEL LENGTH (um)
5
0
1 2 3 4 EFFECTIVE CHANNEL LENGTH (um)
Fig. 9. Threshold voltage roll-off vs effective channel length for FDSOI NMOS devices with N~= 1 x 1015cm -3 and Tsl = 46, 95 and 142 nm.
Fig. 11. Threshold voltage roll-off vs effective channel length for SOl devices with N~= 1 x 1017cm -3 and Ts, = 4 2 and 99 nm.
oxide). However, the resistance is primarily attributed to the TiSi2/Si interface[I,2], or the selective W/Si interface, depending on the process used. These resistances can be reduced with appropriate modification and optimization of the process flow. In addition, other processes may be used with SO1 to achieve low parasiuc resistance values, including cobalt silicide[8].
gate electrode. In this case, the behavior is very similar to that of n +-polysilicon gate NMOSFETs. To illustrate the short channel behavior of the devices with different SOl thicknesses and channel doping, the short channel VxH roll-off relative to 10/~m long devices is shown in Figs 9-11. Figure 9 shows the data for FDSOI devices with 1 x 1015cm -3 channel doping. A clear improvement is observed as the film thickness is reduced. The reduction of short channel VTH roll-off with decreasing film thickness is a result of the reduced amount of charge sharing in a thinner film. Just as the charge sharing is reduced (and short channel behavior improves) in fully depleted SOl compared to bulk devices[9], the charge sharing is limited even more as the film thickness is scaled down. Similar behavior is observed for a channel doping of 1 x 10~6cm -3 (Fig. 10). The VTH roll-off for some SO1 devices with a thinner gate oxide is also plotted in Fig. 10. Some reduction is observed compared to the thicker oxide devices with similar film thickness, as expected. Finally, Fig. 11 shows the VXH roll-off for N a = 1 × 1017cm -3, for film thicknesses of 42 and 99 nm. The amount of VxH roll-off is higher than for lighter-doped devices, owing to increased charge sharing when N~ is increased. However, the dependence of VT. roll-off on film thickness is less clear, at
4. SHORT CHANNEL BEHAVIOR
4.1. Linear region threshold t,oltage The linear region threshold voltage, V+., is determined from the extrapolated IDS VS V~s characteristic at low drain bias (0.1 V). Again, for the case of low channel doping, alternative gate materials can be used (p+-polysilicon, p+-polySiGe) to adjust the threshold voltage to the desired value of ~0.5 V. In the case of n + polysilicon gate, the channel doping of the nMOSFET needs to be high ( ~ 1017 for an SOl thickness of 100 nm), while the p M O S F E T will be heavily doped in the accumulation mode (p-doped channel) to give correct threshold voltages. Alternatively, the p M O S F E T can use p +-polysilicon as the 200 1 I SOl NMOS Tox=10nm ~ ir U-
.~, !. i ~ ", 1
100
~,,,
o
=v0
c - - - - o Tsi=43nm
:}---u Tsi=94nm c-----o Tsi=146nm
~;
"1-
Iog'°s v
Na=l E16/cm3
:
i 5o
/ //f/ o~
o
i
2
3
%,BL
5
EFFECTIVE CHANNEL LENGTH (urn)
Fig. 10. Threshold voltage roll-offvs effective channel length for FDSOI devices with Nd = 1 x 10J6cm -3 and Tsl = 43, 94 and 146 nm.
VG Fig. 12. Schematic illustration of DIBL measurement technique and definition of VD~B,.
Scaling behavior of sub-micron MOSFETs least for this range of Ts~. It is expected that thicker films will exhibit higher values of VTH roll-off, since the film will no longer be fully depleted. The 99 nm thick devices are actually on the edge of full/partial depletion at this doping level, and exhibit a saturation region kink.
4.2. Dram-induced barrier lowering The drain-induced barrier lowering (DIBL) has been characterized in SOl MOSFETs with various film thicknesses and channel doping. The DIBL in a given device is measured at a constant normalized sub-threshold current level, as shown in Fig. 12. The quantity VDmL is defined as the shift in gate voltage required to reach a specified current level when the drain voltage is increased from a low drain bias (0.1 V) to a higher drain bias (Von). The DIBL varies approximately linearly with drain bias up to the punch-through or breakdown point. In order to consistently compare the various SO1 devices, VDmL was measured at a maximum drain voltage of 2.0 V. This drain bias was chosen because it is in the fight range for a future low-voltage power supply, and because the breakdown voltages of most devices studied were above 2.0 V. The drain-induced barrier lowering for FDSOI nMOSFETs with near-intrinsic channel doping (1 x 1015cm-3) is shown in Fig. 13. A significant reduction in DIBL is observed as the film thickness is reduced from 142 to 95 to 46 nm. As Tsi is reduced, the source and drain electric fields fringe more strongly toward the substrate, so that they have less effect on the potential in the channel region. Hence, the gate maintains better control over the SO1 film potential, especially near the back Si/SiO2 interface, and less DIBL is observed. The drain-induced barrier lowering values for 100 nm thick FDSOI MOSFETs with 7.5nm gate oxide are also shown in Fig. 13. Comparing the ~ 100 nm SOl results, devices with the thinner gate oxide show reduced DIBL. This is due to the stronger capacitive coupling of the film potential to the applied gate voltage in the thinner oxide case. Similar behavior of VO]BL with channel
c - - ~ Tsi=46nm,Tox=10nm ~ Tsi=95nm,Tox=10nm Tsi=142nm,Tox=l0nm ,~ J,Tsi=100nm,Tox=7.5nm
250 '-
g 200 F _ 5o!
300 250 ~" 200 g t -J 150 £13 Nh > 100
~ Tsi=99nm o-----o Tsi=42nm
Tox=lOnm Na=1E17/cm3
5o I 00.0
, 0.5 110 1.5 2.0 2.5 EFFECTIVE CHANNEL LENGTH (urn)
~
\\
3.0
length and Tsi is observed when the channel doping is increased to 1 x 1016cm-3. DIBL results for 42 and 99 nm SO1 devices with 1 x 1017cm -3 channel doping are plotted in Fig. 14. The ultra-thin (42 nm) SOl devices exhibit good short channel DIBL behavior, as with the previous sets of data, but the thicker SO1 devices exhibit very high DIBL values, and no clear trend with channel length. At this doping level, the 99 nm SO1 is partially depleted, so that the devices exhibit a saturation region kink as well as an anomalously steep subthreshold slope at higher drain bias. Both the output kink and steep sub-threshold slope are a result of the floating body effects and threshold voltage modulation in partially depleted devices[10-12]. As a consequence of these floating body effects, the measured DIBL at VDS= 2 V is very high. At a low enough drain bias ( ~ 1 V), impact ionizations, and hence the floating body effects, are minimized, and the DIBL reduces to acceptable values. Figure 15 compares fully depleted, ultra-thin SOI MOSFETs with channel doping ranging from 1 x 1015 to 1 x 10lTcm-3. For this range of channel doping, there is apparently little dependence of the drain-induced barrier lowering on the doping. ,
125 t
100 75 I
Na=1E15/cm3
4
Fig. 14. Measured DIBL, VDtBL, for SOl devices with N a = I × 1017cm -3. The 99 nm thick film is partially depleted at this doping level.
150 E
300 I
449
, o - - o N~=lE15/~m3
t
\~
> lOO 5o
~l
0 ~ 0.0
0.5 1.0 1.5 2.0 2.5 EFFECTIVE CHANNEL LENGTH (urn)
3.0
Fig. 13. Measured DIBL, V D I B L , for fully depleted SO1 devices with N. = 1 x 101~cm-3.
0
0.0
,
L
0.5 1.0 1.5 2.0 2.5 EFFECTIVE CHANNEL LENGTH (um)
3.0
Fig. 15. Measured DIBL, VD[BL, for ultra-thin FDSO1 devices with N, = 1 x 1015-1 x 1017cm-3.
450
N. Kistler and J. Woo
~" 120 ~ - , 110 ~ :~ v uJ 100 " O m
90
"1-0 80
m "l- 70 F-:D
60
~
~
,
,
~ -oTsi=46nm, Tox=10nm 2 - - ~ Tsi=g5nm, Tox=10nm ~ ~ Tsi= 142nm, Tox=10nm A---~Tsi=100nm, Tox=7.5nm
i~
~~ '1 ~,
120 !
>
110
aa=l E15/cm3
Tsi=42nm Tsi=99nm
i
Tox=10nm Na=l E17/cm3
tu 100~ Q.
i !,',, !, I ' I,. '1 '~,,\ ~
l
i
q
r
m
90 I-
q
~
ao I
,
1 2 3 4 EFFECTIVE CHANNEL LENGTH (urn)
Fig. 16. Measured sub-threshold slope f o r F D S O I N M O S devices w i t h N . = I x 10 ~5cm -3.
However, the minimum channel length (before punch-through sets in) can be decreased slightly by increasing the doping from l0 is to 1017cm -3. Decreasing the power supply voltage will also reduce the D I B L and allow shorter channel lengths at lighter doping levels.
4.3. Sub-threshold slope The sub-threshold slope of each device was measured from the /Ds--Vos characteristics with low applied drain bias (0.1 V). The measured subthreshold slope for N M O S SOI devices, S, is presented in Figs 16-18. The long channel values o r s for fully depleted devices are all very close to the ideal value of 60 mV/decade as a result of the very small capacitance of the buried oxide. On the other hand, for 9 9 n m SOI with 1 x 1017cm -3 channel doping (partially depleted), the long channel S values are in the range 80-90 mV/decade, which is typical for bulk Si M O S F E T s . At short channel lengths, the sub-threshold slope of the SOI devices increase significantly, as with bulk Si devices, owing to the effects of D I B L on the sub-threshold current flow. It can be clearly observed in Fig. 16 that the short channel sub-threshold slope is significantly improved as the SOI film thickness is
w "1I-CO CO
70 '-
60 i
0.0
0.5 1.0 1.5 2.0 215 EFFECTIVE CHANNEL LENGTH (urn)
3.0
Fig. 18. Measured sub-threshold slope for SOl NMOS devices with N, = 1 x 1017cm-3. The 99 nm thick devices are partially depleted at this doping level. reduced. This is a direct result of the improved resistance to D I B L as Ts~ is scaled. In addition, the use of a thinner gate oxide (7.5 nm) results in better short channel sub-threshold slopes due to stronger front gate capacitive coupling. Comparing devices with different doping levels but similar film thicknesses (Fig. 19), only a slight improvement in the short channel sub-threshold slope can be observed as doping is increased to 1 x 1017cm -3. This is consistent with the slightly improved D I B L behavior in the heavier-doped film, as discussed earlier.
5. BREAKDOWN VOLTAGE
It is well known that a significant problem in thin SOI device design is the low N M O S source-to-drain breakdown voltages, compared to bulk transistors. In order to provide a guideline for SOI thickness scaling, a good understanding and model of the breakdown voltage is needed, taking into consideration a range of SOI film thicknesses, channel dopings and channel lengths. We have reported detailed characterization results of the breakdown behavior in various SOI n M O S F E T structures[13]. It has been found that, at ~" 120
~" 120
g >
LU
c - - ~ Tsi=43nm. Tox=10nm Tsi=94nm, Tox=l 0nm Tsi=146nm, Tox=10nm v~ Tsi=100nm, Tox=7.5nm
110 100
13.
9 W
80
ni
70
D
60
2
3
4
EFFECTIVE CHANNEL LENGTH (urn)
Fig. 17. Measured sub-threshold slope for FDSOI NMOS devices with N d = 1 x 10t6cm -3.
q
I
O.
o---~o Na=l E15/cm3 Na=l E16/cm3 Na=l E17/cm3
90
-d
Na=l E16/em3
1
Tsi=45nm
t.u 100 m
'i,
11o
g
£
$
co 90 0-l-
>
0-i- 80 u.i n.- 70 I Frn ~ 60
0
,o~z- ,"~ 3 4 5 1 2 EFFECTIVE CHANNEL LENGTH (um)
Fig. 19. Sub-threshold slope for FDSOI NMOS devices with Tsi ~ 45 nm and Na = l x 1015-1 x 1017cm-3.
Scaling behavior of sub-micron MOSFETs
>6 LU (5 < 5
- -
'
Na= 1
I
~
L
~
b
0 4 > z
~3
.~0 ~ ~Tsi = 142 nm 0 EE /~ ~Tsi=95nm ',.-" 2 i~' Ek~E]TSi: 46 nm < LU n" I m 0.0 0.5 1.0 1.5 2.0 EFFECTIVE CHANNEL LENGTH (~tm)
Fig. 20. Measured breakdown voltage vs effective channel length for SO1 devices with Tsi = 46, 95 and 142 nm, and Na = 1 x 10~5c m -3. A reduction in VBDwith decreasing film thickness is apparent at longer channel lengths. At channel lengths below 0.5 #m, the breakdown voltage increases as film thickness is reduced.
deep sub-micrometer channel lengths, thinner SO1 films can give higher breakdown voltages due to the improved punch-through resistance of these films. Figure 20 shows VBD VS Le~ for three SO1 film thicknesses with 1 x 1015cm 3 channel doping. Breakdown due to punch-through is indicated by a filled data point[13]. At longer channel lengths (>_2/~m), VBo decreases significantly as the film thickness is reduced from 150 to 95 nm. This is due to the increase in lateral electric field, and hence impact ionization as the SO1 film is thinned[14,15]. The increased impact ionization results in earlier triggering of the parasitic bipolar mechanism, and hence lower VBD.However, the measured breakdown voltage does not vary as significantly for film thicknesses less than 100nm. This may be a result of increased impact ionization compensated by lower parasitic bipolar gain as the SO1 film becomes very thin, as discussed in [16]. On the other hand, behavior of the breakdown voltage at channel lengths below 2 # m varies significantly as the film thickness is varied. Breakdown voltage in all SO1 film thicknesses reduces with decreasing channel length, due to higher electric fields and parasitic bipolar gain; however, the amount of V~Droll-off is reduced as the film thickness is reduced. This improvement in the short-channel VSD behavior is a result of improved resistance to DIBL effects as the SOl film thickness is reduced[13,17]. As a result of the reduced FaD roll-off, the ultra-thin (46 nm) SOI devices actually exhibit higher VBD values than the 95nm thick devices for L e ~ l # m and below (Fig. 20). The thicker film (142nm) devices suffer from punch-through at channel lengths below about 0.8 vm, making them unsuitable for 0.5 or 0.25/~m channel lengths. VaD values for 42 and 99 nm thick SO1 devices with N~ = 1 x 10tTcm -3 are shown in Fig. 21. Note that at a doping of 1 x 1017cm -3, the 99 nm SOl is actually near the transition of being fully/partially depleted
451
> LU (5 < I-._I 0>
Na= lx1017 cm -3
z
3 j o ~ o Tsi = 99 nm O Tsi = 42 nm £3 2 < LU rr I rn 0.0 0.5 10 1.5 2.0 EFFECTIVE CHANNEL LENGTH (~tm)
Fig. 21. Measured breakdown voltage vs effective channel length for SO1 devices with Ts~=42 and 99nm, and N~= 1 x 1017cm 3. The 99 nm film is partially depleted at this doping level.
under normal operating conditions (these devices do exhibit a "kink" in the saturation region of the output characteristics, indicative of partial depletion). In these films, punch-through and DIBL effects are prevented by the heavier channel doping, so that there is little dependence of V B D o n film thickness. As a result, the SO1 film thickness is not critical for maintaining good breakdown voltage in devices which use n +-polysilicon gates and doping in the range 1-5 x 1027cm -3 (depending on the film thickness and desired VTn). However, ultra-thin films ( ~ 50 nm) will be needed if pure fully depleted operation (i.e. fully depleted at zero gate bias) is desired. A comparison of three different doping conditions in a fixed SO1 film thickness is given in Fig. 22. The breakdown voltage at a given channel length can be increased to the order of 1 V as the doping increases from 10~5 to 10]7cm -3. In addition, the minimum channel length without punch-through can be reduced from 0.5/tm to below 0.25 #m. Both of these effects are a result of the higher channel doping counteracting the sub-surface DIBL and punchthrough at shorter channel lengths.
>6
,
r
ILl
TSi = 100 nm
~--.
> z 3 0 a
2
/-~
O~O N-a--- 1X10! 6 cm "3
,/ ~-~N~ -- l~l°~scm-~ < 1 LU rr 0 ~ ~ ,__J CO 0.0 0.5 1.0 1.5 2.0 EFFECTIVE CHANNEL LENGTH (l~m)
Fig. 22. Measured breakdown voltage vs effective channel length for 100 nm SOl films with I x 10~5, 1 x 10r~ and 1 x 1017 c m -3 channel dopings. The devices with 1017cm -3 doping are partially depleted at this doping level.
452
N. Kistler and J. Woo
It is apparent from Figs 20--22 that heavier doping will always provide better breakdown voltages and shorter minimum channel lengths in SOl devices. However, as the doping level increases, the film thickness range for fully depleted operation will become very limited, and heavily doped fully depleted devices can have threshold voltage variations[5]. On the other hand, lightly doped films can provide reasonable breakdown voltages as long as the film thickness is scaled to prevent punch-through. The use of LDD has also been suggested to increase the breakdown voltage. However, LDD should only increase VBD by about 0.5-1 V. Therefore, power supply voltages will still be well below 5 and even 3.3 V. In addition, an LDD region will introduce additional series resistance, which may be especially high in thin SO1, so that a trade-off in lower performance will exist. 6. SCALING GUIDELINES One of the goals of studying the short channel scaling behavior of FDSOI MOSFETs is to provide some guidelines for device design, and to indicate the probable limitations as we scale the devices to 0.25 #m. The threshold voltage requirement places boundaries on the usable film thickness and channel doping, and these boundaries depend on the gate material used and whether fully or partially depleted operation is desired. The target threshold voltage for 0.25~).5 itm MOSFETs is expected to be in the range 0.4-0.6V. This threshold voltage range can be mapped to an SO1 film doping film thickness design space. Figure 23 illustrates the resulting design space, assuming either an n ÷-polysilicon or p ÷-polySiGe gate electrode. The results shown are for NMOS. Similar curves exist for p+-polysilicon and p+polySiGe gate PMOS. For the case of an n +polysilicon gate, there is a narrow design region between the VxH=0.4 and 0.6V curves, with relatively thin SOl ( < 70 nm for fully depleted) and heavy doping ( > 1017cm 3) being necessary. For the p+-polySiGe gate NMOS, a VrH of 0.5-0.6 V can be achieved with light doping and a wide range of film thicknesses (owing to the work function of the SiGe gate, the long channel Vva is always above 0.4 V). Also plotted in Fig. 23 is the maximum depletion width, Xd. . . . vs doping, to indicate where the fully
200
.......
i
0.7*Xdmax
=E" 150
~?
Xdrnax
¢/) t.l.I
100 "lk"-
~,
50
O0~s
1016 10 ~7 CHANNEL DOPING (cm "3)
10TM
Fig. 23. Simulated SOl film thickness channel doping design space, assuming long channel NMOS threshold voltages of 0.4 and 0.6V and either n+-polysilicon or p+-polySiGe gates. Tox= 7 nm in all simulations.
depleted condition is satisfied. At film thicknesses and channel dopings below this curve, the devices will be fully depleted when the gate voltage is above the threshold voltage. However, the devices may not be fully depleted in weak inversion, which is necessary to achieve the near-ideal sub-threshold slopes. This condition will be satisfied if Tsi < 0.7 x X d . . . . which is the depletion width when the potential drop in the film is only half of the potential drop in strong inversion. The curve of 0.7 x ~'dmaxVS doping is also shown in Fig. 23. This more restrictive condition for fully depleted operation significantly reduces the design space when n +-polysilicon gates are used. The maximum allowable power supply voltage for a given structure will be limited by the punchthrough- or bipolar-induced breakdown of the SO! device. The breakdown voltage characterization data are summarized in Table 1. These data are presented in two groups: (i) devices with channel doping of 1 × 1015-1 × 1016cm 3, and (ii) devices with 1 × 1017 channel doping. The data for the first group are representative of devices with light channel doping which employ the p÷-polySiGe gate, or similar mid-gap gate material, to achieve the proper threshold voltage. The second set of data represent the case of the conventional, n+-polysilicon gate NMOS with heavier doping needed for threshold voltage adjustment. Whether the breakdown is caused by punch-through or DIBL, or a combination
Table 1. Breakdown voltage ranges for lightly doped (1 × 10 t~ I × 1016cm 3) and heavily doped (1 x 1017cm 5) SOl N M O S at 0.25 and 0.5 # m channel lengths. The dominant cause o f the breakdown is indicated in each case Heavily doped SOl with n ÷-polysilicon gate
Lightly doped SOl with p +-polySiGegate L = 0.25 #m
L =0.5#m
Ts~ = 50 n m
1.9-2.2 Latch
2.8-2.95 Latch
Tsi = 100 nm
1.4-1.88 Punch-through
2.28-2.87 Latch/punch-through
Tsi = 150 n m
0.5 Punch-through
2.07-4.4 Latch/punch-through
L =0.25,um
L = 0.5#m
Ts~ = 50 n m
2.81 Latch
3.2 Latch
Tsi = I00 n m
2.83 Latch
3.3 I Latch
453
Scaling behavior of sub-micron MOSFETs Table 2. Summaryof scalinglimitationsfor 0.5 and 0.25#m SOl MOSFETs,assumingp +-polySiGeor n +-polysilicongate designregions Heavy doping Light dopingp +-polySiGegate n +-polysilieongate Lcfr= 0.5 #m 50 nm SO1 neededto preventpunch-through No punch-through Fully depleted ~ 50 nm SO1 for FD r ' ~x v~,~;~ 2 v
Left= 0.25#m
< 100 mV DIBL S < 70 mV/decade
< 100 mV DIBL if FD S < 70 mV/decade if FD
50 nm SOI needed to prevent punch-through Fully depleted C ~ 1V < 100 mV DIBL S < 100 mV/decade
No punch-through ~ 50 nm SOI for FD V~ ~ 2 V ~ 100 mV DIBL if FD S ~ 70 mV/decade if FD
of both, is also indicated for each channel length/thickness combination. When using this data to predict the allowable power supply voltage, a reasonable criteria of approx. 1 V margin between VDD and VBD is used. The drain-induced barrier lowering is another factor which needs consideration in the scaling guideline. A criterion of _<100 mV of DIBL at the given power supply voltage is used. Table 2 summarizes the characteristics of SO1 devices in the four possible design regions. First, a target Left of 0.5 p m is considered. For the lightly doped case (see Table 1), the film thickness must be in the range of 50 nm to prevent punch-through at this channel length. At the heavier doping level, punch-through is suppressed. On the other hand, the heavily doped SO1 must be very thin to maintain full depletion ( ~ 5 0 n m for N~ = 3 x 1017cm-3). Because the latching voltages of 50 nm thick devices are about 3 V, the power supply voltage should be in the range of 2 V in both cases. In these thin films the DIBL values are within the 100mV requirement, and the sub-threshold slopes are excellent ( < 70 mV/decade). Partially depleted operation may also be considered if the higher DIBL and sub-threshold slope can be tolerated, or if the power supply is reduced below the "kink" voltage. The second set of results in Table 2 is for the target Leer of 0.25 #m. As with the Leer = 0.5/am case, the lightly doped SO1 must be in the range of 50 nm to prevent punch-through, while the heavily doped SOl still exhibits no punch-through at either film thickness tested. At this short channel length, the latching voltage of the 50 nm SOl with light doping is near 2 V, while for the heavier-doped SO1 it is still close to 3 V. As a result, the power supply voltage of lightly doped SO1 must be scaled down to the 1 V range. At this lower voltage, the measured DIBL can still meet the 100 mV criteria, and the sub-threshold slope is below 100mV/decade. The heavily doped SOl exhibits about 100 mV of DIBL and excellent subthreshold slope at this channel length. It should be noted that the data used for this analysis is taken from the SOICMOS with 10nm gate oxide. Additional improvements can be obtained at 0.25 # m channel lengths if the gate oxide is further scaled, as seen in the data from 100 nm SOI devices with 7.5 nm
gate oxide (presented earlier in this section). It is expected that a combination of ~ 50 nm SO1 and ~ T n m gate oxide will provide excellent device characteristics in the 0.25#m range. In addition, proper source/drain engineering can be used to further improve the short channel effects as well as punch-through. With thinner oxide and source/drain engineering, we expect that ~ 0.1 pm CMOS on very thin SOI ( < 500/~) can be very attractive for low power applications.
7. CONCLUSION
In this paper, detailed characterization of MOSFETs on SIMOX with different channel dopings and SOI thicknesses was presented. It was found that while the transconductance (and therefore current drive) does not depend significantly on the thickness, short channel effects, sub-threshold current slopes and breakdown voltage show strong dependence on both SOI thickness and the channel doping. Scaling guidelines for 0.5 and 0.25 #m devices were developed using these data. It was found that, using lightly doped SOI with a p +-polySiGe gate, channel lengths in the 0.25pm range are achievable with aggressive scaling of the film thickness and gate oxide thickness for low voltage ( ~ 1 V) applications. However, Tsi scaling below 50 nm will become exceedingly difficult. Therefore, to reach channel lengths approaching 0.1 pm, it will require very thin gate oxide ( ~ 5 nm) and proper source/drain engineering. Such devices will also allow higher power supply voltages, in the range of 2 V, which will be desirable for some analog applications, and for higher current drive and speed for some digital applications. Based on these considerations, sub-quarter micron CMOS on SOl show great promise for low power applications.
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3. J. Chung, M.-C. Jeng, J. E. Moon, A. T. Wu, T. Y. Chan, P. K. Ko and C. Hu, IEEE Electron Device Left. 9, 186 (1988). 4. J. G. J. Chern, P. Chang, R. F. Motta and N. Godinho, IEEE Electron Device Lett. 1, 170 (1980). 5. J. Chen, R. Solomon, T.-Y. Chan, P.-K. Ko and C. Hu, IEEE Electron Device Lett. 12, 453 (1991). 6. N. Kistler and J. Woo, I E D M Tech. Dig., p. 727 (1993). 7. J. Wang, N. Kistler, J. Woo and C. R. Viswanathan, IEEE Electron Device Lett. Submitted. 8. L. T. Su, M. J. Sherony, H. Hu, J. E. Chung and D. A. Antoniadis, I E D M Tech. Dig., p. 723 (1993). 9. J. P. Colinge and T. I. Kamins, Electron. Lett. 23, 1162 (1987). 10. J. P. Colinge, IEEE Electron Device Lett. EDL-9, 97 (1988).
11. S. P. Edwards, K. J. Yallup and K. M. De Meyer, IEEE Trans. Electron Devices 35, 1012 (1988). 12. J. R. Davis, A. E. Glaccum, K. Reeson and P. L. F. Hemment, IEEE Electron Device Lett. EDL-7, 570 (1986). 13. N. Kistler and J. Woo, IEEE Trans. Electron Devices 41, 1217 (1994). 14. J. G. Fossum, J.-Y. Choi and R. Sundaresan, IEEE Trans. Electron Devices 37, 724 (1990). 15. M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi and K. Natori, 1EEE Trans. Electron Devices 37, 2015 (1990). 16. J.-Y. Choi and J. G. Fossum, IEEE Trans. Electron Devices 38, 1384 (1991). 17. N. Kistler, E. Ver Ploeg, J. Woo and J. Plummer, IEEE Int. SO1 Conf. Proc., p. 128 (1992).