- Email: [email protected]
A new process for printing fine conductor lines and spaces on large area substrates
Stress distributions around an interference-fit pin connection in a plated through hole R. P. G O E L and E. G U A N C I A L IEEE Trans. Components, ttybrids Mfng TechnoL Chmt-3(3), 392 (1980). In our applications with interference fit pins in plated through holes, we find it necessary to determine regions of high stress. The regions of high stress may be a source of cracks in the plated copper or land regions. In order to understand the source of these high stress regions, two analyses were performed. First, a thermal stress analysis of an interference fit pin connection is carried out with an assumed temperature rise of 70~C. Secondly, an analysis of the process of the insertion of a pin into a PTH is considered. The process is modeled by considering a series of shear and normal loads applied to the inside of the PTH. Inertia effects are not considered in this analysis. The finite element method is used to determine the solutions to both analyses. The results of the thermal stress stu~ly show high stresses in the barrel of the PTH only, thereby implying that cracks in the copper of the land area are unlikely to occur due to a temperature rise of 70~C. Shear stress set up at this interface is not large enough to cause cracking either. The results of the pin insertion process show that the interface goes through a rather severe change in stress history during insertion. It is estimated that the interface stress changes from 18,000 Ibf/in2 (compression) to 7,860 lbf/in2 (tension) during insertion.
Advances in thin-film implementation of RC-active filters E. L U D E R Frequenz 34(9), 248 (1980). Building blocks are a very powerful concept for the hybrid implementation of RC-active filters in Ta-thin-film-technology. The substrate area can be decreased by transformations of the RC-network, by high sheet-resistances of up to 300f1/7"-I as well as high capacitancedensities of 69nF/cm 2 and by the introduction of uniform RC-lines. A single Ta-oxinitride layer provides both Rs and Cs with excellent temperature compensation. Double layer dielectrics ensure'a high yield. RC-lines and temperature stabilised amplifiers provide pole-Qs of up to 250 in the frequency range up to 10MHz.
Ilybrids with TAB - at the threshold of production W. R. R O D R I G U E S De M I R A N D A Solid-St. Technol. p.I15 (1980). Tape automated bonding (TAB) applications for military hybrid microcircuits have seen more than three years of development. During this time, several material combinations, bump and tape configurations, and bonding techniques have been explored. Small-tomoderate quantities of different configurations have been built and tested. The time has arrived for some fundamental decisions to be made, and several basic issues must be dealt with as the TAB technology is at the threshold of production. Honeywell's experience with TAB for military hybrids, today's status of TAB technology, including both progress and problems, trade-offs between different approaches to technology details, and areas requiring further development are reviewed and unknown cost factors are discussed. Finally, the prerequisites for placing TAB into production are presented. Computer controlled imaging system for automatic hybrid inspection L. A R L A N and R. W I L D E N B E R G E R Solid-St. Technol. p.123 (1980). It is shown that an electro-optical system can be used for automatic quality control inspection of thick-film hybrid circuits. A high resolution (10,000 Television Lines/Raster Height; TVL/RH) Return Beam Vidicon (RBV) is used to image an entire 2-inch by 2-inch substrate. The RBV is operated with computer controlled electronic steering and zoom to provide an appropriate level of detail for rapid sequential frame inspection. Video from each frame is compared with that from a referenced image stored on a video disc. Differences are displayed on a colour TV monitor and processed by the computer to identify and characterise faults. Various manual and automatic inspection sequences can be programmed readily. This technique can inspect hybrid substrates at rates of 750 per hour, and its efficiency makes 100% inspection an economical method for quality control at high throughput rates. Hardware instrumentation is described and functional inspection results achieved using sample hybrid circuits with built-in flaws are reported.
5.
Discretes
Low pinch-off voltage FET logic (LPFL): LSI oriented logic approach using quasinormally off GaAs MESFETs G. NUZILLAT, F. DAMAY-KAVALA, G. BERT and C. ARNODO lEE Proc. 127, I(5), 287 (1980). A new LSI oriented logic approach, low pinch-off voltage FET logic (LPFL), leading to highly versatile logic gates capable of combining high speed and low power consumption and requiring a standard fabrication process, is introduced and structures of complex logic gates realisable with this approach are described. Furthermore, a tentative comparison of the LPFL approach with other MESFET logic approaches to date is presented to show their respective design tradeoffs which dictate the range of applications open to each of these approaches. The comparison is based on both computer simulations and experimental measurements on test circuits such as ring oscillators, flip-flops and binary frequency dividers. V.groove isolated BIFET technology for mlcropower ICs S. D. S. MALHI and C. A. T. SALAMA lEE Proc. 127, I(4), 169 (1980). This paper descibes a V-groove isolated B1FET technology suitable for micropower integrated-circuit fabrication. The V-groove isolation technique offers considerable advantages in area and performance over standard junction islated technology. The technology provides an ideal combination of active elements which include low pinch-off JFETs and bipolar transistors. The characteristics of the devices as well as typical applications of the technology are described. Mechanism of ceramic capacitor leakage failures due to low DC stress K. SATO, Y. OGATA, K. OHNO and H. 1KEO IEEE 18th Annual Proceedings, Reliability Physics 1980, Las Vegas, Nevada, p.205 (1980). Ceramic capacitors failed insulation resistance testing at DC voltages far below their rated voltages. Using improved techniques of microanalysis and electrochemical methods, we found that failures resulted from electromigration of electrode materials through a small space in dielectrics filled with a solution containing CI ions. This mechanism could explain electrical behaviours of failed capacitors. Chip capacitors tackle mounting and reliability problems F. KANEKO, F. OHNISHI and N. YAMANA J. Electron, Engng. p.45 (1980). In recent years, electronics equipment has become smaller in size, higher in quality, higher in degree of integration, and lower in manufacturing cost. Hybrid electronic circuits are replacing discrete components in industrial products, automobile control devices, cameras, watches and clocks, and other consumer goods, with chips mounted directly on aluminium substrates or PC boards. In the meantime, hybrid packaging techniques and automation are progressing, enabling cost reduction of chip capacitors. A new process for printing fine conductor lines and spaces on large area substrates H. M. NAGUIB, K. L. KAVANAGH and L. H. HOBBS Solid-St. Technol. p. 109 (1980). A new process ('Mid-Film') that combines the high resolution capability of thin-film technology and the non-vacuum, low-cost and large area capability of thick-film technology is described. The circuit pattern is defined using photolithography as in thin films. The substrate is then fired at high temperature for sintering and bonding the material to the substrate as in thick fiIms. The average thickness of mid-films is 0.2rail 5#m) and their line resolution is less than 2mils (50/.tin) for Au and Ag conductors on large area alumina, glass, and porcelain steel substrates. The physical and electrical characteristics and the advantages and limitations of the new process are discussed.
Design of ion implanted resistors with low l/f noise C. J. M. DAS and W. M. C. SANSEN Aficroelectron. J. 11(3) 24 (1980). This paper provides general design rules for ion implanted resistors. Their fabrication and temperature dependence are presented. In particular, the dependence of the 1/f noise on the sheet resistance and the area of the resistors is discussed. 41
Advances in thin-film implementation of RC-active filters E. L U D E R Frequenz 34(9), 248 (1980). Building blocks are a very powerful concept for the hybrid implementation of RC-active filters in Ta-thin-film-technology. The substrate area can be decreased by transformations of the RC-network, by high sheet-resistances of up to 300f1/7"-I as well as high capacitancedensities of 69nF/cm 2 and by the introduction of uniform RC-lines. A single Ta-oxinitride layer provides both Rs and Cs with excellent temperature compensation. Double layer dielectrics ensure'a high yield. RC-lines and temperature stabilised amplifiers provide pole-Qs of up to 250 in the frequency range up to 10MHz.
Ilybrids with TAB - at the threshold of production W. R. R O D R I G U E S De M I R A N D A Solid-St. Technol. p.I15 (1980). Tape automated bonding (TAB) applications for military hybrid microcircuits have seen more than three years of development. During this time, several material combinations, bump and tape configurations, and bonding techniques have been explored. Small-tomoderate quantities of different configurations have been built and tested. The time has arrived for some fundamental decisions to be made, and several basic issues must be dealt with as the TAB technology is at the threshold of production. Honeywell's experience with TAB for military hybrids, today's status of TAB technology, including both progress and problems, trade-offs between different approaches to technology details, and areas requiring further development are reviewed and unknown cost factors are discussed. Finally, the prerequisites for placing TAB into production are presented. Computer controlled imaging system for automatic hybrid inspection L. A R L A N and R. W I L D E N B E R G E R Solid-St. Technol. p.123 (1980). It is shown that an electro-optical system can be used for automatic quality control inspection of thick-film hybrid circuits. A high resolution (10,000 Television Lines/Raster Height; TVL/RH) Return Beam Vidicon (RBV) is used to image an entire 2-inch by 2-inch substrate. The RBV is operated with computer controlled electronic steering and zoom to provide an appropriate level of detail for rapid sequential frame inspection. Video from each frame is compared with that from a referenced image stored on a video disc. Differences are displayed on a colour TV monitor and processed by the computer to identify and characterise faults. Various manual and automatic inspection sequences can be programmed readily. This technique can inspect hybrid substrates at rates of 750 per hour, and its efficiency makes 100% inspection an economical method for quality control at high throughput rates. Hardware instrumentation is described and functional inspection results achieved using sample hybrid circuits with built-in flaws are reported.
5.
Discretes
Low pinch-off voltage FET logic (LPFL): LSI oriented logic approach using quasinormally off GaAs MESFETs G. NUZILLAT, F. DAMAY-KAVALA, G. BERT and C. ARNODO lEE Proc. 127, I(5), 287 (1980). A new LSI oriented logic approach, low pinch-off voltage FET logic (LPFL), leading to highly versatile logic gates capable of combining high speed and low power consumption and requiring a standard fabrication process, is introduced and structures of complex logic gates realisable with this approach are described. Furthermore, a tentative comparison of the LPFL approach with other MESFET logic approaches to date is presented to show their respective design tradeoffs which dictate the range of applications open to each of these approaches. The comparison is based on both computer simulations and experimental measurements on test circuits such as ring oscillators, flip-flops and binary frequency dividers. V.groove isolated BIFET technology for mlcropower ICs S. D. S. MALHI and C. A. T. SALAMA lEE Proc. 127, I(4), 169 (1980). This paper descibes a V-groove isolated B1FET technology suitable for micropower integrated-circuit fabrication. The V-groove isolation technique offers considerable advantages in area and performance over standard junction islated technology. The technology provides an ideal combination of active elements which include low pinch-off JFETs and bipolar transistors. The characteristics of the devices as well as typical applications of the technology are described. Mechanism of ceramic capacitor leakage failures due to low DC stress K. SATO, Y. OGATA, K. OHNO and H. 1KEO IEEE 18th Annual Proceedings, Reliability Physics 1980, Las Vegas, Nevada, p.205 (1980). Ceramic capacitors failed insulation resistance testing at DC voltages far below their rated voltages. Using improved techniques of microanalysis and electrochemical methods, we found that failures resulted from electromigration of electrode materials through a small space in dielectrics filled with a solution containing CI ions. This mechanism could explain electrical behaviours of failed capacitors. Chip capacitors tackle mounting and reliability problems F. KANEKO, F. OHNISHI and N. YAMANA J. Electron, Engng. p.45 (1980). In recent years, electronics equipment has become smaller in size, higher in quality, higher in degree of integration, and lower in manufacturing cost. Hybrid electronic circuits are replacing discrete components in industrial products, automobile control devices, cameras, watches and clocks, and other consumer goods, with chips mounted directly on aluminium substrates or PC boards. In the meantime, hybrid packaging techniques and automation are progressing, enabling cost reduction of chip capacitors. A new process for printing fine conductor lines and spaces on large area substrates H. M. NAGUIB, K. L. KAVANAGH and L. H. HOBBS Solid-St. Technol. p. 109 (1980). A new process ('Mid-Film') that combines the high resolution capability of thin-film technology and the non-vacuum, low-cost and large area capability of thick-film technology is described. The circuit pattern is defined using photolithography as in thin films. The substrate is then fired at high temperature for sintering and bonding the material to the substrate as in thick fiIms. The average thickness of mid-films is 0.2rail 5#m) and their line resolution is less than 2mils (50/.tin) for Au and Ag conductors on large area alumina, glass, and porcelain steel substrates. The physical and electrical characteristics and the advantages and limitations of the new process are discussed.
Design of ion implanted resistors with low l/f noise C. J. M. DAS and W. M. C. SANSEN Aficroelectron. J. 11(3) 24 (1980). This paper provides general design rules for ion implanted resistors. Their fabrication and temperature dependence are presented. In particular, the dependence of the 1/f noise on the sheet resistance and the area of the resistors is discussed. 41