- Email: [email protected]
A power-constrained design strategy for CMOS tuned low noise amplifiers
Microelectronics Reliability 44 (2004) 877–883 www.elsevier.com/locate/microrel
A power-constrained design strategy for CMOS tuned low noise amplifiers O. Mitrea *, M. Glesner Institute of Microelectronic Systems, Darmstadt University of Technology, 64283 Darmstadt, Germany Received 2 October 2003; received in revised form 10 November 2003
Abstract This paper presents a design methodology for tuned low noise amplifiers (LNAs), based on the minimization of the noise figure for a given power consumption. Our proposed design strategy is demonstrated through the design of a 2.4 GHz LNA. Simulation results show that the amplifier draws 5 mA from a 3.3 V supply voltage and features a 1.7 dB noise figure, while keeping the input/output impedance matched to 50 X. The circuit achieves a gain of 11dB and a 1dB compression point of about )5 dB m. Custom ESD structures that do not degrade excessively the LNA performance are used for protection. The chip area (excluding the bonding pads) is approximately 0.3 · 0.3 mm2 . 2004 Elsevier Ltd. All rights reserved.
1. Introduction Today’s wireless receivers are typically manufactured using several integrated circuits and discrete components provided by different suppliers. For example, in a superheterodyne architecture, the RF front-ends––low noise amplifier (LNA), mixer, voltage controlled oscillator––are implemented in GaAs technology, the intermediate frequency blocks––amplifier, mixer––in silicon bipolar and the baseband components––A/D converter, digital baseband circuitry––in silicon CMOS, while the different filters that define the receiver’s selectivity––RF band-select, image-reject and channel-select filters––are discrete ceramic or SAW devices. Thus, the receiver performance is limited by the specifications of these components, which are often individually optimized without taking into account the whole system. Over the last decade, the RFIC designers have focused on implementing wireless receivers in a standard CMOS technology, being motivated by its low cost and highly integration potential. However, in order to take advantage of the CMOS benefits, new design approaches are
*
Corresponding author. Tel.: +49-6151-164939; fax: +496151-164936. E-mail address: [email protected] (O. Mitrea).
needed, especially in the front-end blocks, where the performance requirements are the most demanding. Typically, the LNA is the first block in a receiver chain. Because its noise contribution adds directly to the receiver noise figure, the LNA has to introduce as little noise as possible. Moreover, it should provide enough gain to reduce the mixer noise, but not so much as to cause a premature mixer overload. Other important design issue is to minimize the power consumption, a stringent requirement in any mobile device. The amplifier should also be linear and able to accommodate large input signals with little distortion. Because the previous RF band-select filter is very sensitive to the quality of its terminating impedance, the input impedance of the LNA has to be matched (usually to 50 X) ensuring besides an optimal signal power transfer. The electrostatic discharge (ESD) protection structures needed for increasing the reliability introduce additional constrains and should be carefully designed, because they strongly influence the amplifier performance. It is a challenging task to trade all these issues, at high frequencies, in a monolithic CMOS implementation. In general, it is difficult to meet the LNA design requirements in a single stage amplifier. The most used topology for implementing a LNA is the tuned cascode amplifier that employs inductive degeneration at the source––see Fig. 1. Even if this narrowband approach
0026-2714/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.01.002
878
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
Fig. 1. Tuned-cascode LNA topology.
requires on-chip inductors (which have poor performance in CMOS) for the input matching, it offers a good noise figure and gain with low power consumption. Taking into account the number and the complexity of the required trade-offs between the design parameters, a design methodology is needed for a successful LNA implementation. In this work we present a design strategy that minimizes the noise figure of the amplifier for a given power consumption, while the other requirements––input/output matching, gain, linearity, ESD protection––are fulfilled. The second section of the paper describes the proposed design approach. In Section 3 an example design for a 2.4 GHz LNA and simulation results are reported.
2.1. Noise performance of MOSFETs It is obvious that the noise behavior of the employed active devices plays a crucial role in LNAs design. The noise of a MOS transistor––see Fig. 2––is modeled by the drain and gate current noise generators, that have the power spectral densities [1]: i2g ¼ 4KT dgg Df
The distributed gate resistance and the substrate resistance are additional noise generators, but they can be reduced to negligible levels through layout techniques like using multi-finger devices and closely spaced substrate contacts. Fig. 2 shows the simplified noise model of the MOS transistor that will be used for the analytical derivations. 2.2. Analytical approach
2. LNA design strategy
i2d ¼ 4KT cgd0 Df ;
The first term models the drain thermal noise current, where gd0 is the zero-bias drain conductance of the device and c is a bias-dependent parameter. For long channel devices in strong inversion c ¼ 2=3 and gd0 ¼ gm . In deep sub-micron technologies, c may be as high as 2 due to hot electron effects. Since the gate and the channel are capacitively coupled, the channel charge fluctuations induce a physical current in the gate terminal. In addition, at high frequencies the gate impedance exhibits a significant shift from its purely capacitive value at lower frequencies. These effects are modeled by the gate noise current source––the second term in Eq. (1)––associated to the 2 real conductance in the gate circuit gg ¼ x2 Cgs =5gd0 . d is also a bias-dependent parameter which is equal to 4/3 in long channel devices but as high as 4 or 6 in short channel MOSFETs. In devices operating at very high frequencies, the induced gate current noise can be the limiting factor to noise performance. Because the two noise sources share a common origin, they are correlated with the complex coefficient c, given by [2]: qffiffiffiffiffiffiffi c ¼ ig id = i2g i2d 0:395j ð2Þ
ð1Þ
The main features of the tuned LNA topology are a very good noise figure, gain and linearity at a low power dissipation [2–4]. The input impedance of the amplifier is given by Zin ¼
ð3Þ
Eq. (3) shows that Ls matches the input impedance to the required value, while Lg tunes the resonance frequency x0 of the input port to the desired operation frequency of the LNA. At resonance, we have Zin ¼
Fig. 2. Noise model of the MOSFET.
gm1 Ls 1 þ sðLg þ Ls Þ þ sCgs1 Cgs1
gm1 Ls Cgs1
and x20 ¼
1 Cgs1 ðLg þ Ls Þ
ð4Þ
The cascode transistor M2 reduces the Miller effect at the input of M1 and increases the reverse isolation, improving the amplifier’s stability. Our design strategy is to obtain a minimum LNA noise figure for a given current consumption. Therefore, the noise factor of the amplifier should be first calcu-
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
lated. Noise factor is defined as the total output noise divided by the total output noise due to the source, which is equivalent to F ¼1þ
iog1 þ iod1 þ iog2 þ iod2 i2oRs
gm1 Ls Cgs1
a bg3 þ 2m1 Id1 gm1
ð10Þ
where a and b are two constants
2 ð5Þ
where iogi is the gate noise of the transistor i, iodi is the gate noise of the transistor i, and ioRs is the noise of the input source impedance Rs , all referred to the LNA output. In the following, we have assumed that the input impedance of the amplifier is matched to the source impedance (which is the output impedance of the RF band-select filter and typically is equal to 50 X) Rs ¼ Rin ¼
F ¼1þ
879
ð6Þ
After some mathematical derivations, the noise factor of the amplifier can be expressed like 2 K1 x0 þ K21 gm1 Rs F ¼1þ gm1 Rs xT1 2 2 x0 x0 þ 4K22 gm2 Rs ð7Þ xT1 xT2 where Rs is the impedance ofpthe ffiffiffiffiffiffiffiffiffiffiffiffiinput source, K1 ¼ d1 =5,K2i ¼ ci þ ðdi =5Þð1 þ 2jcj 5ci =di Þ, and xTi ¼ gmi =Cgsi . Assuming that c1 ¼ c2 and d1 ¼ d2 , we have that K21 ¼ K22 ¼ K2 , and 2 K1 x0 þ K2 gm1 Rs F ¼1þ gm1 Rs xT1 2 2 x0 x0 þ 4K2 gm2 Rs ð8Þ xT1 xT2 In order to achieve the required performance, the cut-off frequency of the devices working at RF must be much higher than the frequency of operation. Therefore, we can trustily consider that xTi > 5x0 . With this assumption, the last factor in Eq. (8) has a small contribution comparing to the other terms and can be neglected (in fact, this is the noise contribution of M2, that is negligible compared to that of M1). In conclusion, the noise factor of the amplifier can be approximated by the noise contribution of the input transistor M1, and it is given by 2 K1 x0 F ¼1þ þ K2 gm1 Rs ð9Þ gm1 Rs xT1 Assuming that the transistors operating in saturation follow the squared low transfer characteristic, Eq. (9) can be further expanded in order to obtain the noise factor as a function of the transconductance gm1 and drain current Id1 of M1:
a¼
K1 ; Rs
b¼
K2 Rs x20 L41;eff 9l2n
ð11Þ
and L1;eff is the channel length of M1 and ln is the electron’s mobility in silicon. The next step is to find the optimum gm1 that minimizes the noise factor F in Eq. (10), for a given current consumption. Taking the derivative of F with respect to gm1 and equating to zero, the optimal value of gm1 and the minimum noise factor are found to be rffiffiffiffiffi pffiffiffiffiffiffi 4 a gm1;opt ¼ Id1 ð12Þ 3b
Fopt
p ffiffiffiffiffiffiffi 4 a3 b ¼ 1 þ 1:755 pffiffiffiffiffiffi Id1
ð13Þ
Finally, the input transistor can be dimensioned using the following relations: Cgs1 ¼
2 gm1;opt L21;eff ; 3Id1 ln
W1 ¼
3 Cgs1 2 L1;eff Cox
ð14Þ
2.3. Proposed design algorithm Taking into consideration the previous relations, we propose the following design algorithm: 1. Specify the desired current consumption Id1 . 2. Calculate the optimal transconductance gm1;opt and the minimum noise factor Fopt using Eqs. (12) and (13). 3. If Fopt does not meet the specs, go to 1 and increase Id1 (considering also a margin of 0.5–1 dB to account for second order effects). 4. Calculate the width of M1 with Eq. (14). 5. Using Eq. (4), determine Ls and Lg for the desired input impedance and frequency of operation. 6. Simulate the circuit to fine tune the previous determined design parameters. The accuracy of the proposed design algorithm is influenced by some minor sources of errors. First, the noise contribution of M2 has been neglected. In order to keep this contribution very small (<0.2 dB) it can be seen from Eq. (8) that the size of M2 should be smaller than that of it M1 (this was also proved in [5]). However, it is difficult to derive a proper methodology for optimizing the size of M2. Second, the assumption that the submicron transistors follow the squared law transfer equation should be carefully considered, especially at
880
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
high current levels. Therefore, circuit simulations with accurate RF models for the employed devices are needed to tune the analytically calculated design parameters.
Table 1 LNA design parameters W1 [lm]
W2 [lm]
Ls [nH]
Lg [nH]
Ld [nH]
Rd [X]
500
50
1.5
3
3.6
900
3. Example design 3.1. Circuit topology In order to validate the proposed methodology, a tuned LNA has been designed. The complete schematic of the LNA is presented in Fig. 3. The drain inductor Ld was added to tune the output of the LNA: it increases the gain while filtering the higher order harmonics of the output signal. In order to reduce the variation of the output impedance due to the spread of the Ld quality factor, a parallel resistor Rd was also introduced. For highly integrated receiver architectures that do not require an external image-reject filter between the LNA and the mixer, the 50 X matching of the LNA output impedance is not required. However, in this design 50 X output matching was employed for testing purposes by using a capacitive transformer made of Cm1 and Cm2 . Thus, the load resistance seen by the LNA is increased from RL ¼ 50 X to 50N 2 X (N ¼ 1 þ Cm2 =Cm1 ), allowing a higher gain. The component values that ensure the output 50 X matching are Cm1 ¼ 1:6 pF, Cm2 ¼ 3:7 pF and Ld ¼ 3:6 nH. In our example, the current through the transistors was limited to 5 mA, which gives an optimum transconductance of 48 mS and a minimum noise figure of approximately 0.7 dB. We should once again mention that the computed noise figure is only a first order approximation, because there are other noise contributors (M2, ESD protection diodes) and parasitics that increase this value. Once the transconductance is known, we can find the width of M1 and its gate source capac-
Fig. 3. Complete schematic of the designed LNA.
itance. Further, Ls and Lg can be determined for a desired operation frequency of 2.4 GHz and for an input impedance of 50 X. The final values employed for the design parameters are summarized in Table 1. They were found after simulations and optimization procedures that will be described in next paragraphs. Taking into account the high operation frequency, the channel length of M1 and M2 is the minimal one allowed by our technology: L1;eff ¼ L2;eff ¼ 0:3 lm. 3.2. ESD protection ESD protection structures are normally included in IC designs to prevent circuit damage by external electrostatic pulses that can occur during handling. One commonly accepted test model for these pulses is the human body model (HBM): a voltage pulse of 2 kV is provided to the tested device by means of a switch action. A current of at least 1 A must be handled by the device under test. If the device is still operational after testing, it is said to be ESD proof under HBM conditions. The protection must be functional for both negative and positive pulses [6]. Standard ESD protection structures offered by our CMOS technology are complex circuits that include diodes, grounded gates NMOS transistors, and resistors. They add series resistance (>50 X) and parallel capacitance (in the range of 1–1.5 pF) to the protected pin, dramatically degrading the performance of the LNA at radio frequencies, mainly through two effects. First, the series resistance in the signal path adds its own noise, increasing the noise figure to unacceptable levels. Second, the parallel capacitance reduces the gain of the amplifier, corrupts the input matching by decreasing the input impedance, and degrades the signal to noise ratio (which also increases the noise figure) [7]. Through circuit simulations, we have found that for our topology the input parasitic capacitance must be limited to 0.5 pF. It is clear, that standard structures cannot be used to ESD to protect our LNA. A possible alternative for ESD protection is to use diodes––see Fig. 4, where D1 is forward biased for a negative pulse and D2 is forward biased for a positive pulse. It was proven in [6] that such ESD devices are capable to handle up to 4 A currents, and can still function after the test. For a standard CMOS process, the voltage drop for 1 A condition (HBM test) over
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
881
3.3. Layout
Fig. 4. ESD protection and bonding pads parasitics.
the diode is approximately 2 V. The same voltage is also across the gate of the input transistor. If this voltage is too large for the employed technology, the input device could be permanently damaged, and a series resistor must be added in the signal path. For our technology with a tolerable voltage of 3.3 V, the 2 V voltage drop is not a problem and no additional resistor is needed. In conclusion, simple diodes are very good ESD devices complying with the HMB test. Because their quality factor is high enough, they can be treated as pure capacitances in the frequency band of interest. As shown in Fig. 5, D1 and D2 were designed to minimize their parasitic capacitance, that was limited to 0.15 pF. The output pad was provided with a standard ESD structure because its parasitics can be included in the matching network.
Fig. 5. Layout of the input pad and ESD protection structures.
The circuit was laid out using the 0.35 lm AMS CMOS technology (3 metal/2 poly) available via Europractice Program. For M1 and M2, multi-finger devices structures were employed to reduce the distributed gate resistance and therefore, its noise contribution. M1 consists of 10 blocks of 10 gates each, while M2 takes only one block. Each gate finger is 5 lm by 0.3 lm. Many substrate contacts have been placed between the component blocks to reduce the substrate resistance and its epi noise. A source of concern regarding the circuit performance is represented by the parasitics introduced by the input pad––the substrate capacitance and resistance Cp1 , Cs1 and Rs1 in Fig. 4. In order to limit their unwanted effects, the pad is shielded from the substrate using the Metal1 layer––see Figs. 4 and 5. The shield is connected to the source terminal of M1, reducing the dependence of the input matching factor on the parasitic input capacitance and minimizing the effects introduced by Rs1 and Cs1 [8]. This technique and the custom ESD structures kept the total capacitance in parallel with the input pad smaller than the allowed value of 0.5 pF. Ld is implemented as on-chip spiral inductor. The structure has been simulated using ASITIC––a simulation tool developed at Berkeley, and resulted that for a 3.6 nH inductance we need 4.25 Metal3 turns with a width of 8 lm and the distance between two windings of 2 lm. The designed inductor is characterized by a quality factor Q ¼ 3:4, a self-resonance frequency of 8.9 GHz and occupies approximately 0.18 · 0.18 mm2 ––see Fig. 6. Taking into account its small value, Ls is implemented as bond wire. Considering an inductance value of 1 nH/ mm, the length of the wire should not exceed 2 mm. Lg is an external inductor because we need a possibility to tune the input resonance frequency and
Fig. 6. LNA micrograph.
882
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
compensate for the tolerances determined by process variations and parasitics. Nevertheless, for very stabile and good characterized processes, Lg can also be integrated on-chip. Cm1 and Cm2 are on-chip poly capacitors. The bias voltage Vb , is generated off chip for flexibility in testing. Our LNA takes five pins and it is housed in a 44-pin package, being part of a multi-chip project. The area of the fully integrated circuit is approximately 0.3 · 0.3 mm2 without bond pads. Fig. 9. Input/output matching.
4. Simulation results Circuit simulations, including the parasitic capacitance and inductances introduced by pads, ESD protection structures and bond wires were performed using SpectreRFTM . Fig. 7 shows that the noise figure of the LNA is about 1.7 dB at 2.4 GHz. As previously mentioned, the parasitics at the input pin and the simplified models used for hand calculations generate a difference of approximately 0.5 dB between the theoretical and simulated minimum noise figures. In addition, a shift in frequency between the two values can be observed. The amplifier has a band-pass behavior achieving a maximum gain of 11 dB at 2.45 GHz––see Fig. 8. Fig. 9 illustrates that the input matching parameter S11 is better than )20 dB, while the output matching parameter S22 is better than )10 dB within the band of
interest of 2.4–2.5 GHz. It is remarkable that this good matching was achieved only with integrable on-chip components. Our circuit features a good reverse isolation between the input and the output port, as indicates the S12 parameter in Fig. 10 (S12 < 43 dB). The LNA was proved to be stable at all frequencies by verifying that K > 1, where K¼
1 þ jDj2 jS11j2 jS22j2 2jS12 S21j
and D ¼ S11 S22 S12 S21. The linearity of the circuit can be described using the 1 dB compression point (1dBCP) and the third order intermodulation point (IP3) parameters. Fig. 11 indi-
Fig. 10. Reverse isolation. Fig. 7. Noise figure.
Fig. 8. Gain.
ð15Þ
Fig. 11. 1 dB compression point.
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
883
5. Conclusions This paper presented an optimal power-constrained design methodology for tuned LNAs. The proposed strategy was validated by an example design of a 2.4 GHz LNA, whose current consumption was limited to 5 mA from a 3.3 V supply voltage. Simulation results indicate a 1.7 dB noise figure, and a gain of about 11 dB while the input and output impedances are matched to 50 X. The LNA has been implemented in the 0.35 lm CMOS AMS technology occupying an active area of 0.3 · 0.3 mm2 . Fig. 12. Test board.
cates a good linearity performance, given that the amplifier exhibits a 1dBCP of )5 dB m, while the inputreferred IP3 can be approximated to 4 dB m. We are currently in process of testing our chip, using a setup that consists in the board presented in Fig. 12 (0.8 mm FR4 dielectric with a constant equal to 3.9 and two copper layers of 35 lm) and a HP 8720A Network Analyzer. In order to obtain accurate measurement results, special care is required when designing the board. Thus, 50 X microstrip lines with a width of 1.4 mm and SMA connectors were employed for contacting the input/output LNA pins. The ground stability is ensured through many via holes that connect the ground lines with the back face ground plane. SMD capacitors and inductors were used for decoupling and RF chokes. Because the ac and dc signals share the input pin, a biastee were employed to separate the two paths. A standard calibration procedure based on short open through line was performed to de-embed the errors introduced by the connection cables. The signal of the network analyzer applied at the LNA input was set to )14 dB m. Some partial measurement results are available showing a good agreement with simulations for the input/output matching and reverse isolation. However, the measured gain is 4–5 dB smaller than the simulated one and shifted at a lower frequency of approximately 2 GHz. The differences between measurements and simulations may occur because the employed RF model for the MOS transistors was not very accurate and the package and test board introduced higher than expected parasitics. The testing process is still in progress for noise figure and linearity performance. Also, more samples are going to be measured in order to confirm these preliminary results.
Acknowledgements The authors would like to thank Dr. A. Garcia-Ortiz and Dipl.-Ing. C. Schlachta from the Institute of Microelectronic Systems, Darmstadt University of Technology, for their valuable help in chip prototyping and PCB design. We also express our gratitude to the colleagues from the High Frequency Department at TU Darmstadt for supporting us in testing the circuits.
References [1] Lee T. The design of CMOS radio––frequency integrated circuits. Cambridge University Press; 1998. [2] Shaeffer D, Lee T. A 1.5-V, 1.5-GHz CMOS low noise amplifier. IEEE J Solid-State Circ 1997;32:745–59. [3] Huang Q, Orsatti P, Piazza F. Broadband, 0.25lm CMOS LNA with sub-2dB NF for GSM applications. In: IEEE Proceedings of Custom Integrated Circuits Conference (CICC), USA, 1998. p. 67–70. [4] Mitrea O, Glesner M. Inductor source degeneration 2.4 GHz CMOS LNA design. In: Proceedings of Kleinheubacher Tagung, Germany, 2001. p. 257–60. [5] Floyd B, Mehta J, Gamero C, O K. A 900-MHz, 0.8 lm CMOS low noise amplifier with 1.2-dB noise figure. In: IEEE Proceedings of Custom Integrated Circuit Conference (CICC), USA, 1999. p. 661–4. [6] Leenaerts D, van der Tang J, Vaucher C. Circuit design for RF transcievers. Kluwer Academic Publishers; 2001. [7] Gramegna G, Paparo M, Erratico PG, De Vita P. A sub-1dB NF 2.3-kV ESD-protected 900-MHz CMOS LNA. IEEE J Solid-State Circ 2001;36:1010–7. [8] Yee D. A design methodology for highly-integrated lowpower receivers for wireless communications. PhD thesis, Berkeley, 2001.
A power-constrained design strategy for CMOS tuned low noise amplifiers O. Mitrea *, M. Glesner Institute of Microelectronic Systems, Darmstadt University of Technology, 64283 Darmstadt, Germany Received 2 October 2003; received in revised form 10 November 2003
Abstract This paper presents a design methodology for tuned low noise amplifiers (LNAs), based on the minimization of the noise figure for a given power consumption. Our proposed design strategy is demonstrated through the design of a 2.4 GHz LNA. Simulation results show that the amplifier draws 5 mA from a 3.3 V supply voltage and features a 1.7 dB noise figure, while keeping the input/output impedance matched to 50 X. The circuit achieves a gain of 11dB and a 1dB compression point of about )5 dB m. Custom ESD structures that do not degrade excessively the LNA performance are used for protection. The chip area (excluding the bonding pads) is approximately 0.3 · 0.3 mm2 . 2004 Elsevier Ltd. All rights reserved.
1. Introduction Today’s wireless receivers are typically manufactured using several integrated circuits and discrete components provided by different suppliers. For example, in a superheterodyne architecture, the RF front-ends––low noise amplifier (LNA), mixer, voltage controlled oscillator––are implemented in GaAs technology, the intermediate frequency blocks––amplifier, mixer––in silicon bipolar and the baseband components––A/D converter, digital baseband circuitry––in silicon CMOS, while the different filters that define the receiver’s selectivity––RF band-select, image-reject and channel-select filters––are discrete ceramic or SAW devices. Thus, the receiver performance is limited by the specifications of these components, which are often individually optimized without taking into account the whole system. Over the last decade, the RFIC designers have focused on implementing wireless receivers in a standard CMOS technology, being motivated by its low cost and highly integration potential. However, in order to take advantage of the CMOS benefits, new design approaches are
*
Corresponding author. Tel.: +49-6151-164939; fax: +496151-164936. E-mail address: [email protected] (O. Mitrea).
needed, especially in the front-end blocks, where the performance requirements are the most demanding. Typically, the LNA is the first block in a receiver chain. Because its noise contribution adds directly to the receiver noise figure, the LNA has to introduce as little noise as possible. Moreover, it should provide enough gain to reduce the mixer noise, but not so much as to cause a premature mixer overload. Other important design issue is to minimize the power consumption, a stringent requirement in any mobile device. The amplifier should also be linear and able to accommodate large input signals with little distortion. Because the previous RF band-select filter is very sensitive to the quality of its terminating impedance, the input impedance of the LNA has to be matched (usually to 50 X) ensuring besides an optimal signal power transfer. The electrostatic discharge (ESD) protection structures needed for increasing the reliability introduce additional constrains and should be carefully designed, because they strongly influence the amplifier performance. It is a challenging task to trade all these issues, at high frequencies, in a monolithic CMOS implementation. In general, it is difficult to meet the LNA design requirements in a single stage amplifier. The most used topology for implementing a LNA is the tuned cascode amplifier that employs inductive degeneration at the source––see Fig. 1. Even if this narrowband approach
0026-2714/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.01.002
878
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
Fig. 1. Tuned-cascode LNA topology.
requires on-chip inductors (which have poor performance in CMOS) for the input matching, it offers a good noise figure and gain with low power consumption. Taking into account the number and the complexity of the required trade-offs between the design parameters, a design methodology is needed for a successful LNA implementation. In this work we present a design strategy that minimizes the noise figure of the amplifier for a given power consumption, while the other requirements––input/output matching, gain, linearity, ESD protection––are fulfilled. The second section of the paper describes the proposed design approach. In Section 3 an example design for a 2.4 GHz LNA and simulation results are reported.
2.1. Noise performance of MOSFETs It is obvious that the noise behavior of the employed active devices plays a crucial role in LNAs design. The noise of a MOS transistor––see Fig. 2––is modeled by the drain and gate current noise generators, that have the power spectral densities [1]: i2g ¼ 4KT dgg Df
The distributed gate resistance and the substrate resistance are additional noise generators, but they can be reduced to negligible levels through layout techniques like using multi-finger devices and closely spaced substrate contacts. Fig. 2 shows the simplified noise model of the MOS transistor that will be used for the analytical derivations. 2.2. Analytical approach
2. LNA design strategy
i2d ¼ 4KT cgd0 Df ;
The first term models the drain thermal noise current, where gd0 is the zero-bias drain conductance of the device and c is a bias-dependent parameter. For long channel devices in strong inversion c ¼ 2=3 and gd0 ¼ gm . In deep sub-micron technologies, c may be as high as 2 due to hot electron effects. Since the gate and the channel are capacitively coupled, the channel charge fluctuations induce a physical current in the gate terminal. In addition, at high frequencies the gate impedance exhibits a significant shift from its purely capacitive value at lower frequencies. These effects are modeled by the gate noise current source––the second term in Eq. (1)––associated to the 2 real conductance in the gate circuit gg ¼ x2 Cgs =5gd0 . d is also a bias-dependent parameter which is equal to 4/3 in long channel devices but as high as 4 or 6 in short channel MOSFETs. In devices operating at very high frequencies, the induced gate current noise can be the limiting factor to noise performance. Because the two noise sources share a common origin, they are correlated with the complex coefficient c, given by [2]: qffiffiffiffiffiffiffi c ¼ ig id = i2g i2d 0:395j ð2Þ
ð1Þ
The main features of the tuned LNA topology are a very good noise figure, gain and linearity at a low power dissipation [2–4]. The input impedance of the amplifier is given by Zin ¼
ð3Þ
Eq. (3) shows that Ls matches the input impedance to the required value, while Lg tunes the resonance frequency x0 of the input port to the desired operation frequency of the LNA. At resonance, we have Zin ¼
Fig. 2. Noise model of the MOSFET.
gm1 Ls 1 þ sðLg þ Ls Þ þ sCgs1 Cgs1
gm1 Ls Cgs1
and x20 ¼
1 Cgs1 ðLg þ Ls Þ
ð4Þ
The cascode transistor M2 reduces the Miller effect at the input of M1 and increases the reverse isolation, improving the amplifier’s stability. Our design strategy is to obtain a minimum LNA noise figure for a given current consumption. Therefore, the noise factor of the amplifier should be first calcu-
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
lated. Noise factor is defined as the total output noise divided by the total output noise due to the source, which is equivalent to F ¼1þ
iog1 þ iod1 þ iog2 þ iod2 i2oRs
gm1 Ls Cgs1
a bg3 þ 2m1 Id1 gm1
ð10Þ
where a and b are two constants
2 ð5Þ
where iogi is the gate noise of the transistor i, iodi is the gate noise of the transistor i, and ioRs is the noise of the input source impedance Rs , all referred to the LNA output. In the following, we have assumed that the input impedance of the amplifier is matched to the source impedance (which is the output impedance of the RF band-select filter and typically is equal to 50 X) Rs ¼ Rin ¼
F ¼1þ
879
ð6Þ
After some mathematical derivations, the noise factor of the amplifier can be expressed like 2 K1 x0 þ K21 gm1 Rs F ¼1þ gm1 Rs xT1 2 2 x0 x0 þ 4K22 gm2 Rs ð7Þ xT1 xT2 where Rs is the impedance ofpthe ffiffiffiffiffiffiffiffiffiffiffiffiinput source, K1 ¼ d1 =5,K2i ¼ ci þ ðdi =5Þð1 þ 2jcj 5ci =di Þ, and xTi ¼ gmi =Cgsi . Assuming that c1 ¼ c2 and d1 ¼ d2 , we have that K21 ¼ K22 ¼ K2 , and 2 K1 x0 þ K2 gm1 Rs F ¼1þ gm1 Rs xT1 2 2 x0 x0 þ 4K2 gm2 Rs ð8Þ xT1 xT2 In order to achieve the required performance, the cut-off frequency of the devices working at RF must be much higher than the frequency of operation. Therefore, we can trustily consider that xTi > 5x0 . With this assumption, the last factor in Eq. (8) has a small contribution comparing to the other terms and can be neglected (in fact, this is the noise contribution of M2, that is negligible compared to that of M1). In conclusion, the noise factor of the amplifier can be approximated by the noise contribution of the input transistor M1, and it is given by 2 K1 x0 F ¼1þ þ K2 gm1 Rs ð9Þ gm1 Rs xT1 Assuming that the transistors operating in saturation follow the squared low transfer characteristic, Eq. (9) can be further expanded in order to obtain the noise factor as a function of the transconductance gm1 and drain current Id1 of M1:
a¼
K1 ; Rs
b¼
K2 Rs x20 L41;eff 9l2n
ð11Þ
and L1;eff is the channel length of M1 and ln is the electron’s mobility in silicon. The next step is to find the optimum gm1 that minimizes the noise factor F in Eq. (10), for a given current consumption. Taking the derivative of F with respect to gm1 and equating to zero, the optimal value of gm1 and the minimum noise factor are found to be rffiffiffiffiffi pffiffiffiffiffiffi 4 a gm1;opt ¼ Id1 ð12Þ 3b
Fopt
p ffiffiffiffiffiffiffi 4 a3 b ¼ 1 þ 1:755 pffiffiffiffiffiffi Id1
ð13Þ
Finally, the input transistor can be dimensioned using the following relations: Cgs1 ¼
2 gm1;opt L21;eff ; 3Id1 ln
W1 ¼
3 Cgs1 2 L1;eff Cox
ð14Þ
2.3. Proposed design algorithm Taking into consideration the previous relations, we propose the following design algorithm: 1. Specify the desired current consumption Id1 . 2. Calculate the optimal transconductance gm1;opt and the minimum noise factor Fopt using Eqs. (12) and (13). 3. If Fopt does not meet the specs, go to 1 and increase Id1 (considering also a margin of 0.5–1 dB to account for second order effects). 4. Calculate the width of M1 with Eq. (14). 5. Using Eq. (4), determine Ls and Lg for the desired input impedance and frequency of operation. 6. Simulate the circuit to fine tune the previous determined design parameters. The accuracy of the proposed design algorithm is influenced by some minor sources of errors. First, the noise contribution of M2 has been neglected. In order to keep this contribution very small (<0.2 dB) it can be seen from Eq. (8) that the size of M2 should be smaller than that of it M1 (this was also proved in [5]). However, it is difficult to derive a proper methodology for optimizing the size of M2. Second, the assumption that the submicron transistors follow the squared law transfer equation should be carefully considered, especially at
880
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
high current levels. Therefore, circuit simulations with accurate RF models for the employed devices are needed to tune the analytically calculated design parameters.
Table 1 LNA design parameters W1 [lm]
W2 [lm]
Ls [nH]
Lg [nH]
Ld [nH]
Rd [X]
500
50
1.5
3
3.6
900
3. Example design 3.1. Circuit topology In order to validate the proposed methodology, a tuned LNA has been designed. The complete schematic of the LNA is presented in Fig. 3. The drain inductor Ld was added to tune the output of the LNA: it increases the gain while filtering the higher order harmonics of the output signal. In order to reduce the variation of the output impedance due to the spread of the Ld quality factor, a parallel resistor Rd was also introduced. For highly integrated receiver architectures that do not require an external image-reject filter between the LNA and the mixer, the 50 X matching of the LNA output impedance is not required. However, in this design 50 X output matching was employed for testing purposes by using a capacitive transformer made of Cm1 and Cm2 . Thus, the load resistance seen by the LNA is increased from RL ¼ 50 X to 50N 2 X (N ¼ 1 þ Cm2 =Cm1 ), allowing a higher gain. The component values that ensure the output 50 X matching are Cm1 ¼ 1:6 pF, Cm2 ¼ 3:7 pF and Ld ¼ 3:6 nH. In our example, the current through the transistors was limited to 5 mA, which gives an optimum transconductance of 48 mS and a minimum noise figure of approximately 0.7 dB. We should once again mention that the computed noise figure is only a first order approximation, because there are other noise contributors (M2, ESD protection diodes) and parasitics that increase this value. Once the transconductance is known, we can find the width of M1 and its gate source capac-
Fig. 3. Complete schematic of the designed LNA.
itance. Further, Ls and Lg can be determined for a desired operation frequency of 2.4 GHz and for an input impedance of 50 X. The final values employed for the design parameters are summarized in Table 1. They were found after simulations and optimization procedures that will be described in next paragraphs. Taking into account the high operation frequency, the channel length of M1 and M2 is the minimal one allowed by our technology: L1;eff ¼ L2;eff ¼ 0:3 lm. 3.2. ESD protection ESD protection structures are normally included in IC designs to prevent circuit damage by external electrostatic pulses that can occur during handling. One commonly accepted test model for these pulses is the human body model (HBM): a voltage pulse of 2 kV is provided to the tested device by means of a switch action. A current of at least 1 A must be handled by the device under test. If the device is still operational after testing, it is said to be ESD proof under HBM conditions. The protection must be functional for both negative and positive pulses [6]. Standard ESD protection structures offered by our CMOS technology are complex circuits that include diodes, grounded gates NMOS transistors, and resistors. They add series resistance (>50 X) and parallel capacitance (in the range of 1–1.5 pF) to the protected pin, dramatically degrading the performance of the LNA at radio frequencies, mainly through two effects. First, the series resistance in the signal path adds its own noise, increasing the noise figure to unacceptable levels. Second, the parallel capacitance reduces the gain of the amplifier, corrupts the input matching by decreasing the input impedance, and degrades the signal to noise ratio (which also increases the noise figure) [7]. Through circuit simulations, we have found that for our topology the input parasitic capacitance must be limited to 0.5 pF. It is clear, that standard structures cannot be used to ESD to protect our LNA. A possible alternative for ESD protection is to use diodes––see Fig. 4, where D1 is forward biased for a negative pulse and D2 is forward biased for a positive pulse. It was proven in [6] that such ESD devices are capable to handle up to 4 A currents, and can still function after the test. For a standard CMOS process, the voltage drop for 1 A condition (HBM test) over
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
881
3.3. Layout
Fig. 4. ESD protection and bonding pads parasitics.
the diode is approximately 2 V. The same voltage is also across the gate of the input transistor. If this voltage is too large for the employed technology, the input device could be permanently damaged, and a series resistor must be added in the signal path. For our technology with a tolerable voltage of 3.3 V, the 2 V voltage drop is not a problem and no additional resistor is needed. In conclusion, simple diodes are very good ESD devices complying with the HMB test. Because their quality factor is high enough, they can be treated as pure capacitances in the frequency band of interest. As shown in Fig. 5, D1 and D2 were designed to minimize their parasitic capacitance, that was limited to 0.15 pF. The output pad was provided with a standard ESD structure because its parasitics can be included in the matching network.
Fig. 5. Layout of the input pad and ESD protection structures.
The circuit was laid out using the 0.35 lm AMS CMOS technology (3 metal/2 poly) available via Europractice Program. For M1 and M2, multi-finger devices structures were employed to reduce the distributed gate resistance and therefore, its noise contribution. M1 consists of 10 blocks of 10 gates each, while M2 takes only one block. Each gate finger is 5 lm by 0.3 lm. Many substrate contacts have been placed between the component blocks to reduce the substrate resistance and its epi noise. A source of concern regarding the circuit performance is represented by the parasitics introduced by the input pad––the substrate capacitance and resistance Cp1 , Cs1 and Rs1 in Fig. 4. In order to limit their unwanted effects, the pad is shielded from the substrate using the Metal1 layer––see Figs. 4 and 5. The shield is connected to the source terminal of M1, reducing the dependence of the input matching factor on the parasitic input capacitance and minimizing the effects introduced by Rs1 and Cs1 [8]. This technique and the custom ESD structures kept the total capacitance in parallel with the input pad smaller than the allowed value of 0.5 pF. Ld is implemented as on-chip spiral inductor. The structure has been simulated using ASITIC––a simulation tool developed at Berkeley, and resulted that for a 3.6 nH inductance we need 4.25 Metal3 turns with a width of 8 lm and the distance between two windings of 2 lm. The designed inductor is characterized by a quality factor Q ¼ 3:4, a self-resonance frequency of 8.9 GHz and occupies approximately 0.18 · 0.18 mm2 ––see Fig. 6. Taking into account its small value, Ls is implemented as bond wire. Considering an inductance value of 1 nH/ mm, the length of the wire should not exceed 2 mm. Lg is an external inductor because we need a possibility to tune the input resonance frequency and
Fig. 6. LNA micrograph.
882
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
compensate for the tolerances determined by process variations and parasitics. Nevertheless, for very stabile and good characterized processes, Lg can also be integrated on-chip. Cm1 and Cm2 are on-chip poly capacitors. The bias voltage Vb , is generated off chip for flexibility in testing. Our LNA takes five pins and it is housed in a 44-pin package, being part of a multi-chip project. The area of the fully integrated circuit is approximately 0.3 · 0.3 mm2 without bond pads. Fig. 9. Input/output matching.
4. Simulation results Circuit simulations, including the parasitic capacitance and inductances introduced by pads, ESD protection structures and bond wires were performed using SpectreRFTM . Fig. 7 shows that the noise figure of the LNA is about 1.7 dB at 2.4 GHz. As previously mentioned, the parasitics at the input pin and the simplified models used for hand calculations generate a difference of approximately 0.5 dB between the theoretical and simulated minimum noise figures. In addition, a shift in frequency between the two values can be observed. The amplifier has a band-pass behavior achieving a maximum gain of 11 dB at 2.45 GHz––see Fig. 8. Fig. 9 illustrates that the input matching parameter S11 is better than )20 dB, while the output matching parameter S22 is better than )10 dB within the band of
interest of 2.4–2.5 GHz. It is remarkable that this good matching was achieved only with integrable on-chip components. Our circuit features a good reverse isolation between the input and the output port, as indicates the S12 parameter in Fig. 10 (S12 < 43 dB). The LNA was proved to be stable at all frequencies by verifying that K > 1, where K¼
1 þ jDj2 jS11j2 jS22j2 2jS12 S21j
and D ¼ S11 S22 S12 S21. The linearity of the circuit can be described using the 1 dB compression point (1dBCP) and the third order intermodulation point (IP3) parameters. Fig. 11 indi-
Fig. 10. Reverse isolation. Fig. 7. Noise figure.
Fig. 8. Gain.
ð15Þ
Fig. 11. 1 dB compression point.
O. Mitrea, M. Glesner / Microelectronics Reliability 44 (2004) 877–883
883
5. Conclusions This paper presented an optimal power-constrained design methodology for tuned LNAs. The proposed strategy was validated by an example design of a 2.4 GHz LNA, whose current consumption was limited to 5 mA from a 3.3 V supply voltage. Simulation results indicate a 1.7 dB noise figure, and a gain of about 11 dB while the input and output impedances are matched to 50 X. The LNA has been implemented in the 0.35 lm CMOS AMS technology occupying an active area of 0.3 · 0.3 mm2 . Fig. 12. Test board.
cates a good linearity performance, given that the amplifier exhibits a 1dBCP of )5 dB m, while the inputreferred IP3 can be approximated to 4 dB m. We are currently in process of testing our chip, using a setup that consists in the board presented in Fig. 12 (0.8 mm FR4 dielectric with a constant equal to 3.9 and two copper layers of 35 lm) and a HP 8720A Network Analyzer. In order to obtain accurate measurement results, special care is required when designing the board. Thus, 50 X microstrip lines with a width of 1.4 mm and SMA connectors were employed for contacting the input/output LNA pins. The ground stability is ensured through many via holes that connect the ground lines with the back face ground plane. SMD capacitors and inductors were used for decoupling and RF chokes. Because the ac and dc signals share the input pin, a biastee were employed to separate the two paths. A standard calibration procedure based on short open through line was performed to de-embed the errors introduced by the connection cables. The signal of the network analyzer applied at the LNA input was set to )14 dB m. Some partial measurement results are available showing a good agreement with simulations for the input/output matching and reverse isolation. However, the measured gain is 4–5 dB smaller than the simulated one and shifted at a lower frequency of approximately 2 GHz. The differences between measurements and simulations may occur because the employed RF model for the MOS transistors was not very accurate and the package and test board introduced higher than expected parasitics. The testing process is still in progress for noise figure and linearity performance. Also, more samples are going to be measured in order to confirm these preliminary results.
Acknowledgements The authors would like to thank Dr. A. Garcia-Ortiz and Dipl.-Ing. C. Schlachta from the Institute of Microelectronic Systems, Darmstadt University of Technology, for their valuable help in chip prototyping and PCB design. We also express our gratitude to the colleagues from the High Frequency Department at TU Darmstadt for supporting us in testing the circuits.
References [1] Lee T. The design of CMOS radio––frequency integrated circuits. Cambridge University Press; 1998. [2] Shaeffer D, Lee T. A 1.5-V, 1.5-GHz CMOS low noise amplifier. IEEE J Solid-State Circ 1997;32:745–59. [3] Huang Q, Orsatti P, Piazza F. Broadband, 0.25lm CMOS LNA with sub-2dB NF for GSM applications. In: IEEE Proceedings of Custom Integrated Circuits Conference (CICC), USA, 1998. p. 67–70. [4] Mitrea O, Glesner M. Inductor source degeneration 2.4 GHz CMOS LNA design. In: Proceedings of Kleinheubacher Tagung, Germany, 2001. p. 257–60. [5] Floyd B, Mehta J, Gamero C, O K. A 900-MHz, 0.8 lm CMOS low noise amplifier with 1.2-dB noise figure. In: IEEE Proceedings of Custom Integrated Circuit Conference (CICC), USA, 1999. p. 661–4. [6] Leenaerts D, van der Tang J, Vaucher C. Circuit design for RF transcievers. Kluwer Academic Publishers; 2001. [7] Gramegna G, Paparo M, Erratico PG, De Vita P. A sub-1dB NF 2.3-kV ESD-protected 900-MHz CMOS LNA. IEEE J Solid-State Circ 2001;36:1010–7. [8] Yee D. A design methodology for highly-integrated lowpower receivers for wireless communications. PhD thesis, Berkeley, 2001.