Design of 2.1 GHz CMOS Low Noise Amplifier

THE JOURNAL OF CHINA UNIVERSITIES OF POSTS AND TELECOMMUNICATIONS Vol.13, No.1, Mar.2006

Design of 2 . 1 GHz CMOS Low Noise Amplifier LI En-ling,

SONG Lin-hong,

YANG Dang-qiang,

XUE Ying,

CHU Meng

Science School. Xi’an University of Technology, Xi’an 710048, P.R. China

Abstract: This paw discusses the design of a fully differential 2 . 1 GHz CMOS low noise amplifier using the TSMC 0.25 p m CMOS process . Intended for use in 3G, the low noise amplifier is fully integrad and without off-chip comfmnents . The design uses an LC tank to replace a large inductor to achieve a s m a l h die area, and uses shielded pad capacitances to improve the noise performance. This paper also presents mluation results of the design. Key words: LNA; LC tank ; noise figure ; shielded pads Article ID: 1005-8885( 2006)Ol-0071-04 CL€ number: TN 492 Document cade: A

1

Introduction

The demand for portable wireless communication systems is driven by the expansion of personal and commercial wireless As a result, the design of portable handsets follows trends that include lower cost, longer battery life, smaller size, and lower weight. After more than a decade intensive research, CMOS technology increasingly takes advantages of present technology advances, which have very low power consumption and make possible the integration of complete communication systems151. So it has become a robust technology for mixed-signal/RF system-on-chip solutions owing to the continued dwindling of channel lengthsL6]. The Low Noise AmplifiedLNA) is the first block in the wireless receiver systems[71. Its design involves tradeoffs among many figures of merits, such as gain, noise, power dissipation, impedance matching, stability, and linearityL8’.For a LNA the low noise figure and high gain are critical performance parameters, and the low power dissipation is also especially essential in portable applications. So LNA design involves tradeoffs among low noise, gain, input matching, power dissipation, etc.. In this paper, a fully integmted 0.25 pm CMOS 2 . 1 GHz LNA was introduced. Design consideration and simulation results are presented in Section 2 and Section 3 respectively. For decreasing the die area, an LC tank is used to replace a large inductor in the output matching circuit, and several shielded pad capacitances are also applied to improve the noise performance.

2

LNA Design

2.1 To Determine the Parameters All of the MOS transistors here have the same channel length - 0.35 pm. The optimum device width of MOS transistor in the input stage is determined by Q.( 1) as follows to achieve a harmony between power dissipation and optimum noise figure”].

where L is the channel length, R s is the resistance of the signal source.

2.2 The Input Match From the input circuit in Fig. 1, the input impedance can be calculated as follow^[^^-^^^ :

zh= s ( L,+

L,)

1

+sc, +

(e)

Ls-

Z;,is specified by

choosing L, and L, to resonate with C,(the capacitance between gate and source of the MI transistor) at the operating frequency with (g,/ C , ) L , set to 50 a.

Fig. 1 The input stage

2.3 Pad Capacitance In the process of practical LNA design, as illustrated in Fig.2, the bonding pad introduces an extra AC current

Received date: 2005-07-04 Foundatloa Item: This work is supported by Planned Scientific Reacareh Project Faundarion of the Educntion Department of Shanxi Province.

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path to ground. In silicon technology, this can severely deteriorate the noise figure if the path contains a resistive component, such as the conductive sub~trate"~-~~ However, ]. if the resistive component is suppressed by replacing the bottom plate of the pad capacitor from the substrate to a metal layer"2-'31 9 % illustrated in Fig. 3, this consequently improves the noise performance and diminishes the noise resistance further. A LNA employing pad capacitance is shown in Fig.4.

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The equivalent impedance of the LC tank ,Z ,

is[153:

(3) R, = 1 -2w2L,(c,&+

c,)

w 2 ( w 2 L L + Rk)(Csub+ c,)'

(4)

L,= L , - ( w 2 L 2 t R L ) ( Csubt c p a ) 1 -2w2L,(C,b+ C,)+ w 2 ( w 2 L k + Ri)(Csub+ C,,)' Fig. 2

(5)

Structure of the unshielded conventional pad 0

Qqu=

Fig. 3

Structure of the shielded pad

(L , - ( w 2 L -!-R 2) ( c s u b -k

c,)

(6)

Rse where R,, L , and Q, are the equivalent series resistance, equivalent inductance and equivalent quality factor respectively. Form a series of computing can conclude that for a certain C,, L,, and R,, will increase and Q, will decreases with the presence of C,. Both the gate inductors LgI, L , and the output matching inductors Lout!, Lw5 can be implemented by

Fig. 4 A LNA employing pad capacitance

2.4 LCTank To avoid the even larger die area, a capacitance is connected in parallel with an inductor to achieve a larger inductance. A simple inductor model is used for analysis (Fig. 5 (a) )[14] : R , is the total series resistance, Csubis the total capacitance to substrate plane, and L , is the inductance. Just as shown in Fig. 5 ( b ) , an equivalent inductor circuit can be obtained after placing a capacitor C, in parallel.

(a) Simplified inductor model

(b) Equivalent circuit with a parallel capacitor

Fig.5 The LC tank

this way, at the price of lower Q factor value. But considering that the equivalent series resistances of the gate inductors become bigger, that means the R , will deteriorate the noise performance. So in this paper only a large inductor in the output matching circuit is replaced by an LC tank, at the price of a little higher noise figure increased by 0.1 dE3. While C,, = 320 pF, the inductance increases from 3.7 nH to 4 . 7 nH and the number of the spiral inductor decreases from 4 to 3.5, obviously it is an effective way to diminish the die area that using a smaller inductor paralleled with a capacitor C, to replace a larger inductor. This method can diminish the die area by 11.25 percent, however it also decreases Q factor value by 21.62 percent. Being different from traditional methods, this method uses a new way to increase the inductance by changing the circuit topology rather than by changing the inductors structure or its process parameters. So as we can conclude this way is easier implemented than other methods. Although the Q factor value becomes lower, it is a worthy of application choice. 2.5 The LNA Implementation The differential 2.1 GHz LNA is shown in Fig. 6. This topology is symmetrical, so here the analysis of just one side of the circuit is given. The amplifier has the commonly cascaded which can provide a good isolation between the input and output

LI En-ling,

No. 1

et

al . : %ign of 2 . 1 GHz CMOS Low Noise Amplifier

73

stages. The inductive degeneration topology is employed drain current for the amplifier. Transistors M5 and &, to get better noise performance for the MITOW band ap- and the resistance R 1, R 3 form the bias voltage circuit. plications. LS1 and Lgl are used to make impedance matching at the input, while the output impedance matching can be obtained by tuning the Lmt1, Ldl and

Simulation Results

3

All the results are obtained through spectre RF simulator of cadence, using TSMC 0.25 pm CMOS process. ductors is replaced by an LC tank, the other is a bond- The simulation results are shown in Table 1 , wire inductor. The pad capacitance Cp, is used to imFig. 7 gives out the Sl1, S 1 2 , S 2 2 and Szl parameters prove the noise performance and diminish the noise as well as N F and II P3. Fmm Fig. 7 ( b ) , the reverse Rort VOLE power gain S 1 2 is - 33.4 dB, which show there is a better isolation between input and output. As shown in the capacitor Cmtl. In the output port, one of the in-

Fig.7(c), the amplifier provides a forward gain S 2 1 of 16.4 dB at 2.1 GHz, which is suitable for 3G mobile communications. From Fig. 7( e) , a minimum noise figure of only 277 dB is achieved at 2 . 1 GHz. The IIP3 can represent the linearity of the entire LNA circuit, the larger of the value, the better of the linearity. From Fig.7(f), the rl.P3 of the LNA is 7.45 dBm, which is suitable for 3G receivers.

Vm

Table 1 Sirnolation resnlts PARAMETER

VALUE

Supply voltage

1.8V 16.4 dE3 2 .1 GHz 2.77 dE3 7.45 dBm - 19.7 dB - 33.4 dB - 18.8 dB 25 m W

Forward gain S21 Center frequency Noise figure

lzp,

Fig. 6 A differential 2 . 1 GHz CMOS LNA

s 11 s 12

resistance. Both the input and the output impedance are matched to 50 a. Cinlis the DC blocking capacitance at the RF input terminal. Transistor

Mg

S22

Dc power

produces the bias

-Mr -40-

@

3

-50 -60-

-

-70-80-

-90 -

u 1.0 2.0 3.0 4.0

-'%

1.0

2.0

3.0

4.0

fIGHz

fIGHz

fIGHz

(a) S,, parameter of the LNA

(b) S,, parameter of the LNA

(c) S,, parameter of the LNA

6.0 r

1.0

2.0 3.0 4.0 fIGHz (d) S, panuneter of the LNA

-

2.0 1.0

1.4

1.8

2.2

2.6

+1 dBIdB *3 dBIdB t 1st order

-1 10

+3rd order

3.0

fIGHz

(e) NF of the LNA

Fig. 7 Simulation results of the LNA

fIGHz (f ) IIPl of the LNA

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The Journal of C H U n

[ 101 SHAEFFER D K, LEE T H. A 1.5-V,1.5-GHzCMOS low noise amplifier [ J ] . IEEE Journal of Solid-state Cir4 Conclusions cuit, 1997, 32(5): . The LNA has been designed using a TSMC 0.25 pm [11] TAO Rui, W"4G %-gong, XIE Ting-ting, et al. 2.9 GHz 0.35 pm CMOS low noise amplifier [ J ] . Acta Electronica CMOS process. It is fully integrated, without off-chip Sinica, 2001, 29(11): 1530- 1532. components. Design procedure and simulation results [ 121 BIBER C E, SCHMATZ M L, MORF T, et al. Technolare given in this paper. For achieving a smaller die area ogy independent degradation of minimum noise figure due and considering the noise performance, an LC tank is to pad parasitics[C] //Proceedings of 1998 IEEE International Microware Symposium Digest, Vol l . Jun 7 - 12, only used to replace the output matching inductors at 1998, Baltimore, MD, USA. Piscataway, NJ. USA: the price of lower Q and a smaller loss of noise figure. IEEE, 1998: 145 - 148.

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~

1 1 1 1 .

[161 ZHANG Zhi-yong. HU Wei, ZHAO Yong, et al. A 950 MHz CMOS LNA design [J 1 . Semiconductor Technology, 2002, 27(5): 36-39. [171 SONG Bei, XIE Ting-ting, CHEN Zhi-heng. The design of deep submicron CMOS LNA [ J 1. Journal of EEE, 2002, 24(6) : 29 - 31. [181 RAZAYI B. Design of analog CMOS integrated d t s [ M ] . New York, NY, USA: McGraw-Hill Inc, 2001. 100 - 107. Biography: LI En-ling, h i a t e Professor in Xi'an University of Technology, research interests include analog integrated circuits design and RF integrated circuits design.