50–830 MHz noise and distortion canceling CMOS low noise amplifier

INTEGRATION the VLSI journal 60 (2018) 63–73

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50–830 MHz noise and distortion canceling CMOS low noise amplifier a,⁎

b

MARK

c

Sana Arshad , Rashad Ramzan , Qamar-ul Wahab a b c

Electronic Design Centre, Department of Electronic Engineering, NED University of Engineering and Technology, P.O. Box 75270, Karachi, Pakistan Electrical Engineering Department, United Arab Emirates University, P.O. Box 15551, Al-Ain, UAE IFM Department, Linkoping University, Sweden

A R T I C L E I N F O

A BS T RAC T

Keywords: CMOS Distortion Feedback FOM Linearity LNA Noise Wideband

In this paper, a modified resistive shunt feedback topology is proposed that performs noise cancelation and serves as an opposite polarity non-linearity generator to cancel the distortion produced by the main stage. The proposed topology has a bandwidth similar to a resistive shunt feedback LNA, but with a superior noise figure (NF) and linearity. The proposed wideband LNA is fabricated in 130 nm CMOS technology and occupies an area of 0.5 mm2. Measured results depict 3-dB bandwidth from 50 to 830 MHz. The measured gain and NF at 420 MHz are 17 dB and 2.2 dB, respectively. The high value of the 1/f noise is one of the key problems in lowfrequency CMOS designs. The proposed topology also addresses this challenge and a low NF is attained at low frequencies. Measured S11 and S22 are better than −8.9 dB and −8.5 dB, respectively within the 0.05–1 GHz band. The 1-dB compression point is −11.5 dBm at 700 MHz, while the IIP3 is −6.3 dBm. The forward core consumes 14 mW from a 1.8 V supply. This LNA is suitable for VHF and UHF SDR communication receivers.

1. Introduction The shrinking CMOS technology has revealed wideband LNAs as promising contenders for accommodating multiple frequency bands in a single unit. In the available wideband topologies, the Distributed Amplifier (DA) [1–3], the Common-Gate (CG) Amplifier [4–11] and the Resistive Shunt Feedback Amplifier [12–15], pose intrinsic broadband behavior [16]. Although the DAs offer a wideband characteristic, the additive distribution of the gain over several stages lead to a high power consumption and inhibit their use in low-power applications. Wideband input impedance in a CG amplifier can be obtained with the aid of one inductor that neutralizes the gate-to-source capacitance Cgs of the transistor. However, the transconductance of the transistor is defined by the input matching criteria, which limits the gain and noise response. The resistive shunt feedback LNAs have broadband response in combination with a Common Source (CS) amplifier, which itself is intrinsically narrowband in nature [12–15]. The input impedance for this topology depends primarily on the feedback resistor, along with the loop gain of the amplifier [12]. For wide bandwidth, the feedback resistor should be small, which on the other hand degrades the NF. Hence it can be inferred that, broadband behavior of the CG and resistive shunt feedback LNAs is limited due to their poor noise response. Positive/ negative

feedback [17–19] and noise-canceling [4–6] techniques are employed to break the correlation between the noise figure, gain and input matching in CG LNAs. In resistive shunt feedback LNAs, series or shunt peaking aids in enhancing the bandwidth, while a large feedback resistor is used to attain a good NF [20]. In this paper, a modified resistive shunt feedback topology is proposed that can deliver optimal bandwidth, NF and gain concurrently without series or shunt peaking. It essentially performs noise and distortion cancelation to achieve the said goals. The proposed LNA depicts measured bandwidth between 50–830 MHz. This LNA can be utilized in multistandard front-ends for VHF and UHF bands. The noise-cancelation feature in the proposed LNA helps to reduce the low-frequency 1/f noise and makes the FETs feasible for low frequency applications, which are classically reserved for BJTs [21]. In general, the 1/f noise of FETs is several orders of magnitude greater compared to the noise at high frequency. The paper is structured as follows. In Section 2, the theory of proposed LNA including detailed derivations of input impedance, noise and distortion cancelation are presented. The LNA component values are listed in Section 3, while fabrication and measurement results are illustrated in Section 4. Section 5 concludes the paper.

⁎ Corresponding author. Present Address: Electronic Design Centre, Department of Electronic Engineering, NED University of Engineering and Technology, Karachi, P.O. Box 75270, Pakistan. E-mail addresses: [email protected] (S. Arshad), [email protected] (R. Ramzan), [email protected] (Q.-u. Wahab).

http://dx.doi.org/10.1016/j.vlsi.2017.07.006 Received 9 March 2017; Received in revised form 22 June 2017; Accepted 26 July 2017 Available online 10 August 2017 0167-9260/ © 2017 Elsevier B.V. All rights reserved.

INTEGRATION the VLSI journal 60 (2018) 63–73

S. Arshad et al.

Fig. 1. Proposed single ended two stage wideband LNA employing modified resistive shunt feedback for input impedance matching and noise cancelation in stage-1 and distortion cancellation in stage-2. All the transistors have length of 130 nm and width given as M1 = 130 µm, M2 = 420 µm, M3 = 30 µm, M4 = 70 µm, M5 = 130 µm and M6 = 90 µm. The resistors are R1 = 1 kΩ, R2 = 212 Ω, R3 = 120 Ω, R4 = 270 Ω while other components are L1 = 772 pH, L2 = 683 pH, L3 = 4.99 nH, L4 = 2.62 nH, C1 = 15 pF, C2 = 15 pF, C3 = 9.3 pF, C4 = 12 pF, C5 = 800 fF, C6 = 1.9 pF, C7 = 1.9 pF, C8 = 13 pF, C9 = 11 pF.

2. LNA circuit theory

2.2. Input Impedance

2.1. Architecture

Fig. 2(a) presents the low-frequency small signal model of the proposed LNA, while the small signal model of feedback part of stage-1 is also drawn separately in Fig. 2(b) for input impedance analysis at low frequency. Due to the addition of the feedback network, the input impedance depends both on the impedance looking into the gates of M1/ M2 and on the impedance looking into the source of M3 (Fig. 1). At low frequency, the transistors M1 and M2 would offer an infinite impedance at the input (gate) node leaving only the feedback path for input impedance matching. Hence, the small signal model of the feedback network of stage-1 is referred from Fig. 2(b), where a test voltage source Vt with current i t is applied at the input. KCL at node B leads to Eq. (1)

Fig. 1 shows the proposed two stage wideband LNA with the proposed feedback. In stage-1, the proposed feedback reduces the noise generated by various components, besides relaxing the input matching criteria, while it enhances the linearity, in stage-2. The transistors M1-M2 in stage-1 and M4 -M5 in stage-2 are placed in an inverter type current-reuse fashion to achieve a high gain with reduced power consumption. The capacitors C1 and C2 couple RF input to the gates of M1-M2 and towards the source of M3 via resistor R2 . The capacitor C3 carries output of stage-1 to the proposed feedback network, which consists of a Source follower M3 with resistances R1 and R2 where R1 serves as the load for M3. The inductors L1 and L 2 enhance the input matching at high frequency, while at low frequency the impedance matching is mainly provided by the feedback network of stage-1. DC blocking capacitor C4 isolates the bias voltages of stage-1 and stage-2. In combination with C5 and L 3, it maintains LNA gain in central region of the simulated passband. In stage-2, C6 and C 7 deliver output of stage-1 to the gates of M4 -M5, respectively. The source follower M6 produces distortion in accordance with the distortion it samples from the output node of M4 -M5. The output of M6 is carried by R4 to the gates of M4 -M5. The difference of the actual input signal and the scaled non-linear feedback signal enhances the linearity as discussed in detail in Section 2.4. The capacitor C9 , inductor L4 and the output impedance of stage-2 collectively generate the 50 Ω output matching for chip measurement without any additional buffer.

i t + gm3Vgs3 =

Vt − i tR2 R1

(1)

where Vgs3 is the gate-to-source voltage of M3 and can be approximated as Va − Vt + i tR2. Here Va is the voltage at node A as per Fig. 1 and gm3 is the transconductance of M3. Using Eq. (1), the low-frequency input impedance (Z in,lf ) for the proposed LNA is given by Eq. (2).

Z in,lf =

R1 + R2(1+gm3R1) 1+gm3R1(1−A1)

(2)

Where A1 is the gain of the forward path of stage-1. In comparison with the resistive shunt feedback topology, which has an input impedance equal to RF/1+ ARSF (with RF , ARSF be the feedback resistor and loop

Fig. 2. (a) Simplified low frequency small signal model of the proposed LNA (b) Small signal model of feedback part of stage-1 drawn individually to find its impedance for input matching. Test voltage source Vt is applied for input impedance calculation.

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to the output node of stage-1 through capacitor C3. The C3 offers a low impedance in the passband, therefore is not shown in Fig. 3. The noise sources for both cases are also illustrated in Fig. 3. For MOSFETs, only the drain-current noise is considered, while thermal noise is considered for the resistors. In Fig. 3(a) and (b), the input node is depicted as a summation node i.e. J, I, K and D, C, E, respectively, to differentiate between the multiple signals and noises appearing at these terminals. It is also assumed that no noise enters from input nodes D and J. The noise current I n1,Rfb and I n2,Rfb , generated by M1,Rfb and M2,Rfb converts into noise voltage at node H after multiplication with the output impedance of stage-1 (rst1). They are then degraded through the feedback resistor R2,Rfb(A2,Rfb), as they reach node I (Fig. 3(a)) [25,26]. As no noise enters from the input node J, noise at K becomes equal to the noise returning from node I. This resulting noise at K, now subtracts (due to difference in polarity) with the input referred noise of node H appearing via the forward path. The left over noise at node K represents the total input referred noise (Vn,in,M1,M2,Rfb ) of M1,Rfb and M2,Rfb (Eq. (4)).

gain of resistive shunt feedback amplifier, respectively [12]), the proposed design (Eq. (2)) relaxes the dependence of input impedance on the feedback resistor by introducing extra terms. It provides an additional degree of freedom in the selection of component values required for input matching. Now R2 , which serves as a conventional feedback resistor in the proposed topology, can be chosen small for wide bandwidth, while the corresponding noise penalty can be eliminated with the aid of noise-cancelation/ reduction mechanism discussed in Section 2.3. Although the inductors L1 and L 2 contribute to the input impedance matching, they are ignored at this time owing to the low-frequency analysis. This is done to obtain simpler and insightful expression of the input impedance. These inductors play a significant role in defining the overall input impedance and gain response of the LNA at high frequencies. They enhance the bandwidth of the LNA, in addition to the proposed feedback mechanism. Revisiting Fig. 1 indicates that both M1 and M2 are two well-known and well-studied inductively degenerated CS amplifiers exploited here in a current-reuse fashion [22–24]. Therefore, referring to [22–24], the high frequency input impedance (Z in,hf ) of the proposed LNA can be written directly as in Eq. (3), where Cgs,M1 and Cgs,M2 indicate the gate-to-source capacitances of M1 and M2 , respectively [22–24]. An impact of the inclusion of the gate-to-drain parasitic capacitances (Cgd) of M1 and M2 , on the high frequency input impedance of the LNA, is discussed in Appendix A. This discussion is useful to estimate the reduction in bandwidth of the LNA during measurements.

Vn,in,M1,M2,Rfb = {((I n2,Rfb)+(−I n1,Rfb))(rst1). AR2,Rfb} ⎧ ((I n2,Rfb)+(−I n1,Rfb))(rst1) ⎫ ⎬ −⎨ A1 ⎭ ⎩ ⎪ ⎪

where rst1 indicates the output resistance of stage-1. Inspection of Eq. (4), indicates that in a resistive shunt feedback architecture, noise reduction occurs at the input node due to the inverted gain of the forward path. In Eq. (4), the second term is smaller than the first term due to the high gain A1 of the forward path. Revisiting Fig. 3(a) and following the same procedure, the signal (−Vin . A1) at node H, also reaches node K (Vsignal,Rfb ) through the feedback and forward paths, rendering total input signal at node K as represented by Eq. (5).

⎛ 1 gm 2 .L1 ⎞ gm1 .L 2 ⎞ ⎛ 1 ⎟⎟ ⎜⎜ ⎟ +s L1 + Z in,hf ≌ ⎜⎜ +s L 2 + Cgs,M2 ⎟⎠ C sC sC ⎝ gs,M1 gs,M1 ⎠ ⎝ gs,M2 ⎛ R + R (1+g R ) ⎞ 2 m3 1 ⎟ ⎜ 1 ⎜ 1+g R (1−A ) ⎟ 1 ⎠ m3 1 ⎝

(3)

Vsignal,Rfb = V

Where gm1 to gm3 represent the transconductances of M1 to M3, respectively. Eq. (3) indicates that, at high frequency, the input impedances of the inductively degenerated CS amplifiers and impedance looking into the feedback network appear in parallel at the input node of the LNA.

K

⎪ ⎪

I

H

C

R 2, Rfb

M1, Rfb

R2

In, 1, Rfb

(a)

Vn, 3

A

M1

M3

B

Vn, R 2

R1

In, 1

(6)

where AM3 refers to the gain of the transistor M3. The second term in the above equation (which is equivalent to the second term in Eq. (4)), is again smaller than the first term because of the high gain A1. If now, first terms of Eqs. (4) and (6) are considered, it is clear that the first term in Eq. (6) is more smaller than the first term in Eq. (4), due to the presence of the source follower with a gain lesser than 1 and more degradation of the noise in the feedback network of the proposed design. Thus e.g., if the second terms in Eqs. (4) and (6) has a magnitude of 0.5 and that of their first terms are 1 and 0.7, respectively, then smaller input noise results from Eq. (6), which is for the proposed architecture. This result is possible when widths of the transistors M1, M2 , and the value of the feedback resistor R2 remain the same for both cases, for similar power consumption and a suitable input matching. The smaller input referred noise can easily be sent to the output node after multiplication with the gain of the LNA to find the smaller output referred noise. The signal (−Vin . A1) at the output node A (Fig. 3(b)), also scales down more through the proposed feedback network and reaches node E (Vsignal ) as in Eq. (7)

M2

E

D

Vn, R 2, Rfb

(5)

⎧ ((I )+( − I n1))(rst1) ⎫ ⎬ −⎨ n2 A1 ⎩ ⎭

In, 2 J

− Vin . A1. AR2,Rfb

Vn,in,M1,M2 = {((I n2)+( − I n1))(rst1). AM3. AR2}

2.3.1. M1 and M2 only The noise-cancelation/ reduction in the proposed feedback scheme is evaluated by initially inspecting the noise response of the resistive shunt feedback architecture. Therefore, Fig. 1 is initially examined and simulated with the proposed feedback in stage-1 (as in Fig. 3(b)) and then after removing M3 and R1 (Fig. 3(a)), to convert it to a resistive shunt feedback. After removing M3 and R1, the resistor R2 is connected

In, 2, Rfb

in

In the proposed feedback, more noise reduction occurs, because the addition of the source follower further reduces the feedback factor, and the noise or signal is degraded even more in the feedback path (Fig. 3(b)) due to the fact that AM3 < 1. Thus, the channel thermal noise (I n1 and I n2 ) of M1 and M2 at node A, generates the total input referred noise Vn,in,M1,M2 (Eq. (6)) after reaching node E through the feedback and forward network.

2.3. Noise analysis of the proposed LNA

M 2, Rfb

(4)

Vn, R1

(b)

Fig. 3. Stage-1 of proposed LNA (a) with source follower M3 and resistor R1 removed i.e. in a Resistive feedback configuration (b) with proposed feedback scheme including M3 , R1 and R2 . Input node is shown as a summation point to explain the incoming/ outgoing signal and noise at these nodes. The feedback and forward path for transferring output signal or noise to input node are also shown.

Vsignal = Vin − Vin . A1. AR2.AM3 65

(7)

INTEGRATION the VLSI journal 60 (2018) 63–73

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the noise of the additional components internally, but enhances the signal in contrast to a resistive shunt topology.

Since the proposed feedback scheme actually reduces the feedback factor and includes M3, therefore, the net signal at node E (Eq. (7)), at the gates of M1 and M2 , is comparatively larger in contrast to a simple resistive feedback (Eq. (5)). Thus, we see that the signal level at the input has increased with the proposed feedback. Similar to the noise, signal in Eq. (7) can easily be sent to the output node, after multiplication with the gain of the LNA. This fact is verified in Section 2.3.3 with schematic level simulations, after the noise analysis of the peripheral components is discussed.

2.3.3. Noise Figure Owing to the discussion in Sections 2.3.1 and 2.3.2, the noise factor of the proposed LNA can be written as Eq. (12)

F = FM1,M2+F

FM1,M2 =

FM3 =

FR2 =

The noise voltage of R1 (Vn,R1) will divide into two components. One

back

M2( −

to

input

through

⎛ 1 ⎞ ⎟ Vn,R1⎜⎜R2 gm3 ⎟ ⎝ ⎠ 1 1 . . ). ⎛ ⎞ A1 AM3 ⎜⎜R2 1 + R1⎟⎟ gm3 ⎝ ⎠

M3

and

.AR2 ), while other travels

then

through

M1

and

(R2

1 gm3

R R2 − 2 . {A1. AM3. AR2}2 Rs Rs

(16)

6

gm3

4 3

(10)

2

Noise of R2 (Vn,R2 ), is actually present at the input terminal of the LNA and experiences a similar cancelation effect as the input signal (Eq. (7)). Total noise at node E (Vn,in,R2 ) due to Vn,R2 is depicted in Eq. (11)

0

200

400 600 Frequency (MHz)

800

1000

(a) 30 S11 and S21 (dB)

Vn,in,R2 = Vn,R2 − Vn,R2. A1. AM3. AR2

With proposed feedback (M3,R1 and R2) With Resistive Shunt Feedback (R2 only)

5

1

)⎧ 1 1 ⎫ ⎬ ⎨AR2 − . A1 AM3 ⎭ + R1) ⎩

(14)

(15)

NF (dB)

Vn,R1(R2

(13)

⎧ ⎫2 γ ⎪ 1 ⎨− + AM3. AR2⎬ gm3R s ⎪ ⎭ ⎩ A1

As can be expected, both components bear

opposite polarity, and cancel each other partially at the input node, which reduce the noise-overhead (Vn,in,R1) generated by R1 as shown in Eq. (10)

Vn,in,R1 =

2

where γ is a noise parameter for deep submicron MOSFETS [28]. In Eqs. (13) and (15), complete channel thermal noise cancelation of M1, M2 and M3 is possible if AM3. AR2 becomes equal to the inverse of A1. Other conditions exist for noises generated by R1 and R2 (Eqs. (14) and (16)). Due to the dissimilarity of these conditions, along with the requirement of a high gain, and a suitable input matching, all these conditions cannot be met simultaneously. As an optimal point, instead of focusing on complete cancelation of any one of the presented noise sources, component values are selected that best reduce the overall NF with the proposed architecture. Thus, Fig. 4(a) presents schematic level NF obtained by simulating Fig. 1 (i.e. with the proposed feedback in stage-1) and then after the removal of M3

(9) ⎛ 1 ⎞ ⎟ Vn,R1⎜⎜R2 gm3 ⎟ ⎝ ⎠ ⎛ ⎞ 1 ⎜⎜R2 + R1⎟⎟ gm3 ⎝ ⎠

γ(gm1 + gm2)(rst1)2 ⎧ 1 ⎫ ⎨AM3. AR2 − ⎬ Rs A1 ⎭ ⎩

⎛ 1 ⎞ R1⎜R2 g ⎟ 2 ⎧ m3 ⎠ ⎝ 1 1 ⎫ ⎨AR2 − ⎬ FR1 = . 2⎞ ⎩ ⎛ A1 AM3 ⎭ 1 R s⎜R2 g + R1 ⎟ m3 ⎝ ⎠

Eq. (8) indicates that a resistive shunt feedback architecture also reduces noise of the feedback resistor R2,Rfb , due to signal inversion in the forward path. Returning to Fig. 3(b), M3, R1 and R2 contribute noise in addition to M1 and M2 . Noise generated by M3 can be modeled as a voltage Vn3 at its gate or at the output node of M1 and M2 . This noise cancels in a similar way as the channel thermal noise of M1 or M2 (Eq. (6)), as explained in Section 2.3.1 rendering Vn,in,M3 as Eq. (9) at node E.

will reach node E through R2 (≌

(12)

2

(8)

⎧ ⎫ 1 Vn,in,M3 = Vn3⎨ − + AM3. AR2⎬ A1 ⎭ ⎩

+ FM3 + FR2

where noise contributed by stage-2 is not considered in accordance with [27]. FM1,M2 , FR1, FM3 and FR2 refer to the individual noise factors of M1- M2 , R1, M3 and R2 displayed accordingly in Eqs. (13)–(16).

2.3.2. Noise from Peripheral Components In this section, noise generated by the components other than the main transistors are considered. Revisiting Fig. 3(a), in the resistive feedback topology, the noise of the feedback resistor R2,Rfb is shown as a voltage (Vn,R2,Rfb ) at the gates of M1,Rfb and M2,Rfb . Since Vn,R2,Rfb is actually present at the input terminal of the LNA, it undergoes cancelation similar to the input signal (Eq. (5)). Therefore, the net noise Vn,in,R2,Rfb at input, due to the feedback resistor R2,Rfb , is as shown in Eq. (8)

Vn,in,R2,Rfb = Vn,R2,Rfb − Vn,R2,Rfb. A1. AR2,Rfb

R1

(11)

Thus, if all the corresponding noises and signals are collected at the input node of the proposed and the resistive shunt feedback schemes, we observe that the proposed feedback reduces the total noise and enhances the signal level at the input of the LNA, thereby improving the noise figure in contrast to a resistive shunt topology. It can be further noted that any other noise (such as the noise from stage-2) appearing at the output node of stage-1, will be reduced similar to the channel thermal noise of M1, M2 or M3, as discussed previously. It can be inferred from the previous analysis that the noise penalty due to the additional components in the proposed feedback topology is not that significant. The proposed method not only cancels

20 10

S21 with proposed feedback (M3,R1 and R2) S21 with resistive shunt feedback (R2 only) S11 with proposed feedback (M3,R1 and R2) S11 with resistive shunt feedback (R2 only)

0 -10 -20 -30

0

200

400 600 Frequency (MHz)

800

1000

(b)

Fig. 4. Schematic level simulation results depicting (a) NF with input matched condition (b) S11 and S21 before and after removal of M3 and R1 (in Fig. 1).

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and R1 to make it a resistive shunt feedback architecture. For both cases, the input matching is maintained, while gain also enhances (Fig. 4(b)) in the proposed scheme due to the enhancement in the signal level, as discussed earlier in Section 2.3.1. A 0.7–0.8 dB reduction in the overall NF is achieved through the proposed architecture in contrast to a resistive shunt feedback topology. The results of the proposed feedback scheme reveal that both the gain and the NF have improved without degradation in the bandwidth and the input matching, but at the cost of power consumption. It shall also be noted that reducing the feedback factor in a resistive shunt feedback can be accomplished by increasing the value of the feedback resistor R2 . In this case, it is well expected that a large feedback resistor will result in a low NF, but with a reduced bandwidth and a degraded input matching. Thus, we can say that the proposed feedback scheme works quite efficiently and can replace resistive shunt feedback topology at the cost of slightly increased power consumption.

Cgs, st 2

Stage − 2

M4

(a)

Distortion canceling feedback circuit

(19)

where rst2 represents the output resistance of stage-2. The non-linear source voltage (Vy ) of M6, due to i6 , can be approximated as in Eq. (20), when the current through Cgs6 and Cgs,st2 is considered negligible and ignored for simplicity.

Vy ≌ i6R3 = (gm6V6 + g2,6V26 + g3,6V36)R3

(20)

The non-linear voltage Vy can be obtained as a function of V2 (shown in Eq. (21)) with the aid of Eqs. (18), (19) and (20) where terms of order, higher than 3, shall be neglected for simplicity in all equations. 2 2 Vy = V2(−R3gm6gm st2rst2) + V22(−R3gm6g2rst2 + R3gm st2 g2,6r st2 ) 2 3 3 +V32(R3gm6g3rst2 + 2R3g2,6g2gm st2r st2 − R3g3,6gm st2 r st2)

(21)

The non-linear voltage (V2,6 ) fed back to the gate of stage-2 (generated due to the non-linearity of M6 and concurrently influenced by M2 ), equals Vy (Eq. (22)), as current through gate-to-source capacitance of stage-2 (Cgs,st2 ) is ignored. However, consideration of this current will bring R4 and Cgs,st2 in series and V2,6 shall then be redefined accordingly, which is not considered here.

V2,6 ≌ Vy

(22)

The non-linear gate-to-source voltage (V2,6 ), generated by M6, is fed back to the input of stage-2. For simplicity, it is assumed that voltage (V2 ) initially present at gates of M4 and M5 is linear. The sum of V2 and V2,6 (V2 + V2,6 = Ve), becomes the new gate-to-source voltage of stage-2, where Ve is expressed in Eq. (23).

⎞ ⎛ 2 2 Ve = V2(1−R3gm6gm st2rst2) + V22⎜R3gm st2 g2,6r st2 −R gm6g2rst2⎟ 3 ⎠ ⎝ 3 3 2 +V32(−R3g3,6gm st2 r st2 +R3gm6g3rst2 + 2R3g2,6g2gm st2r st2 )

M 5, Rfb

(23)

Finally the linearized drain current (ilinearzed,st,2 ) at the output is shown in Eq. (24)

M6 R 4, Rfb U Y V R3

R3

V6 ≌ − ist2 . rst2 = − (gm st2V2 + g2V22 − g3V32)rst2

(18)

R4

i6

third order non-linearity coefficients of i6 , respectively and V6 represents gate-to-source voltage of M6 . As M6 is present at the output node of stage-2, V6 will have an influence of the non-linearity generated by stage-2. An approximate relation between V6 and V2 (assuming negligible input current through Cgs6 ) can be furnished by using Eq. (19).

where gm6 , g2,6 and g3,6 model the main transconductance, second and

Z

V6

Fig. 6. Small signal model of stage-2 of the proposed LNA (from Fig. 1 or Fig. 5(a)), along with the distortion-canceling feedback.

where gm st2 , g2 and g3 represent the main transconductance, second and third order non-linearity coefficients of stage-2, respectively, and V2 represents the net gate-to-source voltage of stage-2. The component g3 is negative as both M4 and M5 operate in strong inversion. The drain current i6 of M6 is shown in Eq. (18)

X

Cgs6

R4

(17)

M5

rst 2

Y

The stage-2 of the proposed LNA is identical in architecture to the stage-1. The signal amplitude becomes large here and can drive the transistors to the edge of linear region or even out of it. Therefore, this stage is optimized for linearity enhancement. For linearity analysis, Fig. 5(a) shows stage-2 of the proposed LNA with the proposed distortion canceling feedback scheme (M6 , R3 and R4 ), while in Fig. 5(b), M6 and R3 are removed to convert it to a resistive shunt feedback. After removing M6 and R3, the resistor R4 is connected to the output node of stage-2 through capacitor C8. The C8 is considered to offer low impedance in the passband therefore is not shown in Fig. 5. In Fig. 5(b), the non-linear feedback signal from node U to input node V, is a downscaled replica of the output signal. This feedback will significantly 'reduce' the fundamental component of the incoming signal due to difference in polarity of the input and feedback signal and introduces higher order non-linear components, which degrades the linearity. In the proposed distortion canceling feedback, presence of a transistor within the feedback network allows it to be used as a nonlinearity generator. The distortion cancelation is accomplished by operating M6 in the sub-threshold region. The small signal model of the proposed feedback from Fig. 5(a) is shown in Fig. 6. The non-linear drain current (ist2 ) of stage-2 is shown in Eq. (17)

i6 = gm6V6 + g2,6V26 + g3,6V36

X

ist 2 V 2 + V 2, 6

2.4. Distortion cancelation

ist2 = gm st2V2 + g2V22 − g3V32

ILinearised, st 2

Z

ilinearzed,st2 = gm st2Ve + g2V2e − g3V3e

M 4, Rfb

(24)

Putting Ve from Eq. (23) in Eq. (24) results in Eq. (25) which is a linearized drain current that we obtain through the proposed feedback as compared to a resistive shunt feedback.

(b)

ilinearzed,st2 = (gm st2 −α f )V2 + (g2 − α 2nd,order + β2nd,order)V22

Fig. 5. Stage-2 of the proposed LNA (from Fig. 1) (a) depicting the proposed feedback scheme (b) altered by removing M6 and R3 to convert it to a resistive shunt feedback scheme.

+(−g3 − α 3rd,order + β3rd,order)V32 67

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Fig. 7(a) reveals 4–5 dBm enhancement in the IIP3 with the proposed distortion cancelation scheme in contrast to a resistive shunt topology. The schematic level gain response for both cases is also shown in Fig. 7(b). Fig. 7 signifies that the proposed scheme not only enhances the IIP3, it also improves the gain of the LNA, which is due to the reduction in β factor of the feedback path as discussed in Section 2.3. It shall also be noted that the transistor M6 is operating in weak inversion therefore, its high frequency response is poor. Its slow response translates into a delay between the feedback and the actual input signal of stage-2. This results in partial cancellation of second/ third order distortion components (Eq. (25)). However, both simulation and measured results (discussed in Section 4), indicate that despite of the slow response of M6 , there is a reasonable improvement in IIP3.

where α f , α 2nd,order and α 3rd,order represent the magnitude of the additional negative terms generated for the fundamental, second order and third order frequency components, respectively, while β2nd,order and β3rd,order represent the magnitude of additional positive terms generated for the second order and third order frequency components, respectively. All these terms are mentioned in Eqs. (26)–(30).

α f = R3gm6gm st2 2rst2

(26)

α 2nd,order = 2g2R3gm6gm st2rst2 + R3g2gm st2gm6rst2

(27)

β2nd,order = g2,6R gm st2 3rst2 2 + g2R32gm6 2gm st2 2rst2 2

(28)

3

α 3rd,order = R3g3,6gm st2 4rst2 3+2R3gm6g 22rst2 +3R32gm6 2gm st2 2rst2 2g3+2R32gm6gm st2 3rst2 3g2g

(29)

2,6

2 R3gm6g3rst2gm st2+2R3g2,6gm st2 g2 rst2 2 +g3R33gm6 3gm st2 3rst2 3+3R3gm6gm st2rst2g3 +2g2,6R3gm st2 2g2r 2+2R32gm6 2gm st2g 22rst2 2 st2

β3rd,order =

3. LNA circuit parameters The first order design equations derived in Section 2 help the designers to develop design insight. The values of the components and the sizes of the transistors for the LNA are selected to achieve an overall optimum in global design space by iterative simulations. The LNA operates with a VDD of 1.8 V and consumes 14 mW in the forward path. A high value of VDD is chosen to obtain better linearity and to ensure that the operation of the transistors (M1, M2 , M4 , M5), is in the linear region. Lowering the VDD will drive the transistors out of the saturation region, resulting in a degraded linearity. The stage-1 carries 2.8 mA of current, with M1 and M2 implemented as multifingered devices, with effective widths of 130 µm and 420 µm, respectively. The width of M3 is 30 µm, while R1 = 1 kΩ and R2 = 212 Ω. The interstage LC network, which is responsible to prevent the gain degradation at mid-band frequencies, is chosen as C4 = 12 pF, C5 = 800 fF and L 3 = 4.99 nH. A 5 mA of current flows through stage-2 of the LNA. The parameters of this stage are optimized to improve the linearity as discussed in Section 2.4. Thus M4 , M5 and M6 are chosen to be 70 µm, 130 µm and 90 µm wide, respectively, with R3 = 120 Ω and R4 = 270 Ω. The inductors are selected to be L1 = 772 pH, L 2 = 683 pH, L4 = 2.62 nH. All the transistors in the LNA are biased with on-chip biasing scheme (shown in Fig. 1), except the feedback transistors (M3 and M6 ), for which the gate voltages are supplied directly. The biasing network carries a total current of 1.55 mA and consumes 2.8 mW of power in addition to the power consumed by the LNA core. Although the value of the supply voltage is same for both the stages, separate VDD and Ground pads are utilized for each branch, as well as for the biasing transistors, to allow independent control of each of them. Sometimes gain programmability is desired to accommodate strong input signals. The gain can be programmed by changing the current through the MOSFETs. Furthermore, in case of on-chip integration, when 50 Ω matching is not required, the current and size of M4 and M5 can be modified to vary the total output impedance (which partially depends on the output impedance of M4 and M5), of the LNA. However, the variation will be limited as both M4 and M5 also contribute to the gain and linearity of the LNA.

(30)

Inspection of Eq. (25) indicates the presence of all terms of the nonlinearized drain current, as mentioned in Eq. (17). It also indicates that the proposed scheme only fractionally reduces the fundamental component of the output drain current. Thus, simulation results indicate that the linearity response of the proposed design is better than the simple resistive shunt feedback architecture. Eq. (25) further implies that the proposed scheme generates multiple positive/ negative, second and third-order distortion components, which reduce each other's effect in addition to the initially present non-linearities (g2 and g3). Resultantly, the input referred 3rd order intercept point (IIP3) of the LNA is improved. This is depicted in Fig. 7(a), where schematic level IIP3 (with tones 40 MHz apart) is plotted for the resistive shunt feedback and for the proposed feedback at several frequencies. The curves are obtained by simulating Fig. 1, i.e. with proposed distortion canceling feedback in stage-2 (Fig. 5(a)) and then after the removal of M6 and R3 (similar to Fig. 5(b)) to make it a resistive shunt topology.

IIP3 (dBm)

2 0 -2

With proposed feedback (M6, R3 and R4) With Resistive Shunt feedback (R4 only)

-4 -6

0

200

800

1000

(a)

25

S21 (dB)

400 600 Frequency (MHz)

20 With Resistive Shunt feedback (R4 only) With proposed feedback (M6, R3 and R4 only)

15

10

0

200

400 600 Frequency (MHz)

800

4. Measurement results The layout of the proposed LNA is designed using the Cadence Layout XL tool, with 130 nm standard CMOS technology from IBM. The proposed LNA consists of a combination of transistors, resistors, capacitors, and inductors. All of these components are integrated onchip. Only the resistances associated with the biasing transistors are implemented off-chip. For simulations, standard BSIM4 transistor model, on-chip MIM and dual MIM capacitors model and on-chip spiral inductors models, available in the technology library are used.

1000

(b) Fig. 7. Schematic level simulation results depicting (a) IIP3 values and (b) gain levels of proposed feedback technique and that of resistive feedback. The figures are obtained by initially simulating Fig. 1 (proposed feedback) and then after removal of M6 and R3 (resistive shunt feedback).

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20

S21 (dB)

15 10 Measured Simulated with bondwire

5 0 -5 0

200

400 600 Frequency (MHz)

800

1000

Fig. 10. Measured and simulated gain of the proposed LNA.

7

NF (dB)

6 Fig. 8. PCB and chip micrograph of the proposed LNA with chip die area of 0.5 mm2.

During fabrication, the chip area is shared between our design and another circuit. The chip area of our LNA is 0.5 mm2 excluding the bond-pads. The fabricated chip is wire-bonded on a double layer FR4 PCB (Fig. 8) for measurement. EM Co-Simulation feature of the Advanced Design System (ADS) is utilized to obtain 50 Ω co-planar waveguides for the RF input and output. Measurements are carried out using the R & S ZVB8 VNA, FSV Signal and Spectrum Analyzer and the Noise source from Noisecom. In Fig. 9, the simulated and measured results of the input and the output reflection coefficients are presented. Both the input and output terminals of the LNA are matched to the 50 Ω source and load impedance, respectively. No external buffer has been included at the output of the LNA, as the combined impedance resulting from the capacitor C9 , inductor L4 and the output impedance of stage-2, rendered a sufficiently wideband output matching. The simulated S11 and S22 are better than −10 dB and −8 dB, respectively, in the 200– 850 MHz frequency range. Measured S11 is below −8.9 dB between the 50–1000 MHz frequency range, while measured S22 remains below −8.5 dB in the 180–1000 MHz band. In Fig. 10, the measured and simulated gain of the LNA are presented. A maximum gain value of 17 dB is obtained in measurements, with maximum simulated value of around 18.16 dB. Fig. 11 presents the simulated and measured NF of the LNA. The minimum NF available in band is as low as 2.2 dB at 400 MHz, while the average NF is 3.35 dB. Measured 1-dB compression point (P1dB) and the input referred third-order intercept point (IIP3), are shown in Figs. 12 and 13, respectively. The value of P1dB = −11.5 dBm at 700 MHz. Two tones (700 MHz and 740 MHz), with 40 MHz spacing, are selected to test the IIP3 of the LNA. The IIP3 is found to be −6.3 dBm. The simulated IIP3 for the complete bandwidth are plotted in Fig. 7(a). The degradation in the measured values can be attributed to the additional PCB bond-pad capacitance and the parasitic inductance

Measured Simulated with bondwire

5 4 3 2 0

200

400 600 Frequency (MHz)

800

1000

Fig. 11. Measured and simulated NF of the proposed LNA with minimum measured NF of 2.2 dB at 400 MHz.

Fig. 12. Measured 1 dB compression point is −11.5 dBm at 700 MHz.

Fig. 13. Measured IIP3 is −6.3 dBm (with 700 MHz and 740 MHz tones).

S11 and S22 (dB)

0

Measured S11 Simulated S11 with bondwire Measured S22 Simulated S22 with bondwire

-5

introduced due to long bond-wires, which differ from the 1 nH inductance value considered in simulations, assuming 1 mm length of bond-wire. Since bond-wiring is done by a third party, we had no control on the length and the physical orientation of the RF bondwires, which should be short for a reduced inductance. The degradation in the NF can also be owed to the small resistivity of the substrate material, which is 2 Ωcm for our case. In addition, the parasitic capacitances in a MOSFET become dominant at high frequency. Due to these parasitic capacitances, especially the Cgd , the high frequency poles shift to low frequency, resulting in a reduced bandwidth of the LNA. Moreover, due to the non-linear behavior of these capacitances, they are extremely difficult to model, especially for the extremely wide

-10

-15

0

200

400 600 Frequency (MHz)

800

1000

Fig. 9. Measured and simulated input and output reflection coefficients of the proposed LNA.

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Table 1 Comparison with recently published similar LNAs. Specification

This work

MWCL 2014 [36]

MEJ 2013 [35]

MWCL 2017 [34]

RFIC 2007 [33]

JSSC 2007 [32]

RE 2010 [31]

JSSC 2005 [29]

ASSCC 2005 [30]

I. VLSI.J 2011 [15]

Technology (nm) Bandwidth3-dB (GHz)

130 0.05– 0.83 ≤ −8.9 17 ≤ −8.5 2.2^ 14 1.8 -11.5 −6.3 0.5 0.14

180 DC−1.4

180 3.1–10.6

180 0.4–1

90 0.4–1

130 0.1–0.93

180 0.2–2

180 2–4.6

180 0.4–0.9

180 0.47–3

< −15 16.4 – 3^ 12.8 1.8

< −10 9.7 < −12 4.2 11 1.5 – −8.5 0.925 0.17

−13.6* 17 −15 4.2 6.21 1 – −17* 0.27 7.9e-3

−10 16 – 3.5–5.3 16.8 1.2 – −17 0.07 1.2e-3

< −10 13 −10 4 0.72 1.2 −18 −10.2 0.27 0.3

−8* 18 – 4.5 20 1.8 – −7# 0.18 0.07

−9 9.8 −11 2.3–5.2 12.6 1.8 NA −7 0.9 0.09

−9.5 21.5 −8.5 4 43 1.8 −20.3 −12.7 0.568 4.5e-3

−10 11.3 – < 2.5 27 1.8 −15 −3.5 0.52 0.19

S11 (dB) S21 (dB) S22 (dB) NF (dB) Pdiss (mW) VDD (V) PldB (dBm) IIP3 (dBm) Area (mm2) FOM

−13.3 0.038 0.03

*avg; #simulation only; ^min.

with noise and distortion-canceling capabilities to improve the noise, gain and linearity response, in contrast to a resistive shunt feedback topology. The proposed LNA operates within the 3-dB bandwidth from 50 to 830 MHz with maximum measured gain of 17 dB and a mid-band NF of 2.2 dB. Other specifications (linearity, power consumption and Si area) are better than or comparable to the best reported designs published recently in literature. The main feature of the LNA is the excellent noise performance at lower frequencies where the 1/f noise dominates the overall noise. This LNA has applications in cable modems, VHF, and UHF TV and communication receivers.

transistors, like the ones used in this design. This results in discrepancies between the simulated and measured results of the input impedance, gain and noise figure at high frequency. However, keeping the above factors in consideration, measurement results are in good agreement with the simulation results. A performance comparison of the proposed LNA with other state of the art LNAs reported in open literature is presented in Table 1. The LNAs in Table 1 are compared with respect to a Figure of Merit (FOM) shown in Eq. (25) [37]. The proposed LNA depicts better NF, gain, IIP3 and a reasonable power consumption, compared to the reported designs from extremely prestigious journals [14,27–36]. These results are also visible in the FOM of our LNA (Table 1).

FOM =

BW[GHz].Gain[abs].IIP3[mW] PDC[mW].(NF[abs]−1)

Acknowledgement

(25)

A more elaborate discussion on the FOM for LNAs is reported by the authors in [38].

The authors would like to thank NED University, Karachi, Pakistan, for bearing the chip fabrication cost and UAE University, Alain, UAE, for assistance in PCB manufacturing via UAE University Grant 31N157.

5. Conclusion In this paper, a modified resistive shunt feedback LNA is proposed

Appendix A. The high frequency input impedance of the proposed LNA in presence of the gate-to-drain capacitance Cgd To find the high frequency input impedance of the LNA including the gate-to-drain capacitance Cgd , consider the high frequency small signal model of the forward path (from Fig. 1) of stage-1 as shown in Fig. A-1. Since the input impedance offered by the feedback network of stage-1 appears in parallel to the input impedance offered by M1 and M2 , we will include it directly in the final expression. Applying KVL at the input node on the NMOS M1 side in Fig. A-1 we get

−Vin + Vgs1 + VL2 = 0

(A-1)

where the voltage across the inductor L 2 (VL2 ) is

VL2 = (i1 + gm1Vgs1)sL 2

(A-2)

As i1 can be written as Vgs1sCgs,M1, the Eq. (A-2) becomes

VL2 = (Vgs1sCgs,M1 + gm1Vgs1)sL 2

(A-3)

Putting VL2 from Eq. (A-3) into Eq. (A-1) renders

Vgs1 =

Vin 1+s2Cgs,M1L 2 + gm1sL 2

(A-4)

Similarly, we can find for PMOS M2 from Fig. A-1 that

i3 = Vgs2sCgs,M2

(A-5)

and 70

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VL1 i3

Vin

L1

gm 2 Vgs2 C gs, M 2 Vgs2 iin C Cgd, T A Vo1 i2 i1 Vgs1 Cgs, M1 gm1Vgs1 VL2 L 2

Fig. A1. High frequency small signal model of the forward path of stage-1 of the proposed LNA.

Vgs2 =

Vin 1+s2Cgs,M21L1 + gm2sL1

(A-6)

Also, it can be seen from Fig. A-1, that Cgd,T represents the total gate-to-drain capacitance (Cgd1 + Cgd2 ) offered by both M1 and M2 , while Vo1 refers to the output voltage of stage-1. Now the current i2 is given by

i2 = (Vin − Vo1)sCgd,T

(A-7)

where Vo1 is equal to −VinA1, in which A1 refers to the gain of stage-1. Therefore,

i2 = Vin(1+A1)sCgd,T

(A-8)

Using Fig. A-1, we can represent the input current i in of the LNA as

i in = i1 + i2 + i3

(A-9)

Putting the values of currents from the previous analysis

i in = Vgs1sCgs,M1 + Vin(1+A1)sCgd,T +V sCgs,M2

(A-10)

gs2

and using Eqs. (A-4) and (A-6), Eq. (A-10) becomes

i in =

VinsCgs,M1 1+s2Cgs,M1L 2 + gm1sL 2

+ Vin(1+A1)sCgd,T +

VinsCgs,M2 1+s2Cgs,M21L1 + gm2sL1

(A-11)

Eq. (A-11) can be rearranged to find the ratio Vin /i in

⎛ 1 g L2 ⎞ Vin = ⎜⎜ +sL 2 + m1 ⎟⎟ C i in sC ⎝ gs,M1 gs,M1 ⎠

⎛ 1 g L1 ⎞ ⎜⎜ +sL1 + m2 ⎟⎟ C sC ⎝ gs,M2 gs,M2 ⎠

⎛ ⎞ 1 ⎜ ⎟ ⎜ (1+A )sC ⎟ 1 gd,T ⎠ ⎝

(A-12)

where Eq. (A-12) represents the high frequency input impedance offered by the forward path of the proposed LNA including the gate-to-drain capacitance. If now the effect of the feedback network is included from Eq. (2), Eq. (A-12) modifies to the high frequency input impedance offered by the proposed LNA including the gate-to-drain capacitance as shown in Eq. (A-13)

⎛ 1 g L2 ⎞ Z in,hf,Cgd ≌⎜⎜ +sL 2 + m1 ⎟⎟ Cgs,M1 ⎠ ⎝ sCgs,M1

⎛ 1 g L1 ⎞ ⎜⎜ +sL1 + m2 ⎟⎟ Cgs,M2 ⎠ ⎝ sCgs,M2

⎛ ⎞ R + R (1+g R ) 1 2 m3 1 ⎜ ⎟ 1 ⎜ (1+A )sC ⎟ 1+g R (1−A ) 1 gd,T ⎠ 1 m3 1 ⎝

(A-13)

Inspection of Eq. (A-13) reveals that both the gate-to-drain and gate-to-source parasitic capacitances of the transistors M1 and M2 contribute to the input impedance and are responsible to reduce the bandwidth of the LNA at high frequency. However, the effect of the gate-to-drain capacitance is more dominant due to its multiplication with the gain of the stage-1. Appendix B The interstage LC network (comprising of C4 , C5 and L 3) shown in Fig. 1, improves the quick roll-off, of the gain of the LNA, starting from central region of the simulated passband. It helps the gain to stay constant over a wider bandwidth. This results in an enhancement of the 3-dB bandwidth of the LNA. The S21 curves for the proposed LNA with and without the interstage LC network are shown in Fig. B-1. The S11 response of the proposed LNA with and without the interstage LC network are shown in Fig. B-2, which indicates an improved response in presence of the interstage network.

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22

S21 (dB)

20 18 16

With interstage LC network Without interstage LC network

14 12

0

500

1000 1500 Frequency (MHz)

2000

Fig. B1. The S21 curves for the proposed LNA with and without the interstage LC network (comprising of C4 , C5 and L 3 ).

S11 (dB)

0 S11 with interstage LC network S11 without interstage LC network

-10

-20

-30

0

500

1000 1500 Frequency (MHz)

2000

Fig. B2. The S11 curves for the proposed LNA with and without the interstage LC network (comprising of C4 , C5 and L 3 ).

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INTEGRATION the VLSI journal 60 (2018) 63–73

S. Arshad et al. Sana Arshad received her B.E. degree in Electronic Engineering and M.S. degree in Micro System Design from NED University of Engineering and Technology, Karachi, Pakistan, in 2004 and 2008, respectively. She is currently a PhD student and working towards the completion of her degree at NED UET, Pakistan. Her research is focused on Flexible RF LNAs for Software Defined Radio. Other research interests include high speed and low noise CMOS Analog circuits. She has published three journals and three conference papers internationally

Qamar ul Wahab received his Master and M. Phil. degree in Physics from Quaid-e-Azam University, Islamabad Pakistan. He earned his PhD in 1994 from Linköping University, Sweden in the area of SiC materials and devices. Current research interests are in modeling and simulations of microwave power transistors and amplifiers in LDMOS, CMOS and wide bandgap SiC, GaN technologies.

Rashad M. Ramzan (SM.04, M. 09, SM, 11) did his B.Sc. from the University of Engineering and Technology (UET),Lahore, Pakistan, M.Sc. from the Royal Institute of Technology (KTH), Stockholm, and PhD from Linkoping University, Sweden in 1994, 2003 and 2009, respectively, all in Electronics Engineering. He has more than eight years of industrial experience. He has been involved in research and development throughout his professional carrier. He has designed SMPS, Low Noise Electronics, digital ASICS and RFICs. One of his designed LNA was published in ISSCC, 2007. He has got two best paper awards and is reviewer of several IEEE journals. His area of interest are RFICs, Microwave Sensors, Low Power Biomedical Circuits. and Energy Harvesting Circuits. He has published more than fifty journals and conference papers.

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