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A three-dimensional nonlinear analysis of electromigration-induced resistance change and Joule heating in microelectronic interconnects
Solid-State Electronics 45 (2001) 341±346
A three-dimensional nonlinear analysis of electromigrationinduced resistance change and Joule heating in microelectronic interconnects S.H. Kang a,*, E. Shin b a
Bell Laboratories, Lucent Technologies, 9333 S. John Young Parkway, Orlando, FL 32819, USA b Department of Mathematics, Purdue University, West Lafayette, IN 47906, USA
Received 12 September 2000; received in revised form 15 October 2000; accepted 27 October 2000
Abstract This paper reports a three-dimensional nonlinear numerical model developed for the deep submicron interconnects that carry high current densities in integrated circuits. This model can solve a thermoelectrically coupled ®eld to analyze resistance variation and Joule heating as a function of electromigration-induced voiding in various interconnect structures. As a result, the model can identify the critical void volume that is directly related to the time to electromigration failure. The model is particularly useful as an analytical tool that can quantitatively evaluate the eects of the architecture and physical properties of various refractory ®lms and diusion barriers on the electromigration reliability. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: Microelectronic interconnects; Electromigration; Finite element analysis; Via/contact; Reliability
1. Introduction An integrated circuit (IC) contains a dense array of metallic contacts and interconnects that carry electric current between the various devices on the chip. One of the primary concerns in the manufacture of an IC is to ensure that those metals do not fail by electromigration throughout its expected lifetime. Electromigration damage appears as voids that can grow to raise the electrical resistance to unacceptable values. In general, electromigration failure of deep submicron contacts and interconnects is dominated by voiding at the ends of the metal stripes where vacancies preferentially accumulate under an electric ®eld. This failure mode has been studied extensively [1±4]. It is then well recognized that the resistance escalation that causes interconnects failure is a consequence of void growth. *
Corresponding author. Tel.: +1-407-371-3851; fax: +1-407371-3547. E-mail address: [email protected] (S.H. Kang).
Prior work has shown that the failure kinetics controlled by the void-growth mechanism can be described by two parameters: the critical void volume (Vc ) and the drift velocity (vd ) [2]. These are incorporated in the following equation tg
Vc kT Vc =A ; vd A eZ Dqj
1
where tg is the time to grow a void to failure, A is the cross-sectional area of the metal stripe, k is the Boltzmann constant, T is the metal temperature, e is the electronic charge, Z is an eective charge number, D is the diusion coecient, q is the resistivity of the metal, and j is the eective current density. The critical void volume (Vc ) is de®ned by the amount of materials that must be depleted away from the metal to meet a failure criterion, while the drift velocity (vd ) represents the rate of void growth to Vc . Finding Vc and vd has been a subject of technological interest since electromigration lifetimes can be calculated using Eq. (1). The drift velocity is understood relatively well; vd is a function of the
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S.H. Kang, E. Shin / Solid-State Electronics 45 (2001) 341±346
driving force (T and j ) and the mechanism (D and Z ) of electromigration [2,5]. At this writing, however, there is very little probative data on Vc . Some possible way of ®nding Vc in realistic metallization structures is ®nite element analysis [6]. In contrast to simpli®ed analytical calculations [7], a ®nite element method can solve a nonlinear, coupled thermoelectric phenomenon like electromigration-induced resistance change even for complex multilevel interconnects. Using the method, the work reported here demonstrates a three-dimensional (3-D) nonlinear thermoelectric model that simulates resistance and temperature changes as a function of electromigration-induced material depletion. This work will show that the model provides an eective way to determine Vc for a variety of metallization con®gurations.
2. Model The 3-D thermoelectric model presented here is written using a general ®nite element code [8], while it is constructed on various forms of user-de®ned functions and macroprograms. The elements used are eight-node hexahedrons that have two degrees of freedom (scalar electric potential and temperature) per node. In the model the electric ®eld causes Joule heating (coupled problem), and both the electric and thermal properties are temperature dependent (nonlinear problem). Hence, a set of the following two constitutive formulations should be solved [9]. First, the formulation for the electrical conduction problem is given by K e fV g fIg;
2
where [K e ], {V}, and {I} are the electrical conductivity matrix, the nodal electric potential, and the applied load vector (current), respectively. Second, the formulation for the heat conduction problem is given by oT fQg 0; 3 K t fT g C ot where [K t ], {T}, {C}, and {Q} are the thermal conductivity matrix, the nodal temperature vector, the heat capacity matrix, and the thermal load vector, respectively. Note that [K e ], [C], and [K t ] depend on {T} while {Q} depends on {T} and {V}. Consequently, Eqs. (2) and (3) must iteratively be solved, i.e., the Joule heat from electrical analysis is passed to thermal analysis as a heat source {Q} while the computed temperatures {T} are used to revise the electrical conductivities {K e } for subsequent iteration. The model ®rst performs a current conduction analysis under a direct-current load at a constant substrate temperature (in this work T 250°C), and determines the electrical potential and current density distribution.
In general, when the simulation is conducted at relatively low current densities (J < 106 A/cm2 ), the eect of Joule heating on the metallization temperature is essentially negligible [6,10]. Hence, reasonably accurate resistance solutions may be obtained without the subsequent thermal simulation. However, the eect of Joule heating is substantial when current densities are larger locally or globally. For this reason the model reported here always requires a heat conduction analysis. An example of the simulated W-via 0:36 0:36 0:9 lm3 structure is shown in Fig. 1. This represents an interconnect that consists of the lower (M1) and the upper (M2) level Al±0.5Cu (wt.%) stripes (width: 0:36 lm, thickness: 0:45 lm, length: 240 lm). These Al± Cu stripes are coated with an overlayer of 25 nm thick TiN and an underlayer of 30 nm Ti/60 nm TiN, 15 nm Ti/30 nm TiN, or 25 nm TiN. We postulate that the narrow Al±Cu stripes have bamboo microstructures. Voiding should then occur predominantly at the end of the Al±Cu stripes, as shown in Fig. 1 (electron ¯ow from M1 to M2). For the purpose of comparison, however, we will apply the model also to the case of ``internal'' voiding. In this work, the temperature-dependent electrical data were measured experimentally. The temperature-dependent thermal data were taken from various literature sources [11,12]. 3. Calculation of the critical void size (Vc ) The calculated initial resistance R0 of the W-via structure in Fig. 1(a) is 160.8 X at T 250°C. The resistance starts to increase as electromigration depletes the Al±Cu under the electric current (J 106 A/cm2 ). Provided that the depleted volume has a hexahedron shape (Fig. 1(b)), the void size is represented by the edge depletion length L. It follows that Vc =A in Eq. (1) can be represented by the critical depletion length Lc . An electromigration failure then occurs when L reaches Lc , i.e., the void volume reaches Vc . Using the common 10% or 20% failure criteria (DRf ), Vc in this work is the void volume when the resistance increase DR R R0 is equal to 16.1 X or 32.2 X, respectively. The results of resistance calculation caused by voiding in the vicinity of the via are plotted in Fig. 2 for three common types of refractory ®lms. For reference, the resistance change due to the void in the middle of the line (internal voiding) is also plotted. Note that, except the case of internal voiding, there are only subtle resistance changes until L reaches the via size. Even when there is no Al±Cu left over the via (i.e. L 0:36 lm), DR is less than 2 X. Thus DR=R0 is less than 1.2%, which is far smaller than the failure criteria. Up to this point, therefore, voiding cannot be a threat to the interconnect reliability. This result is in agreement with experimental ®ndings [2,4].
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Fig. 1. (a) Schematic illustration of the cross-sectional view of the two-level interconnects with the W-via (size: 0.36 lm). (b) A ®nite element model showing the W-via region when the Al±Cu depletion length L is 0.24 lm.
As shown in Fig. 2, however, the resistance starts to increase abruptly when L exceeds the via size. This sudden increase in resistance is associated with the fact that the highly resistive underlayers are the only conducting path to the via after the Al±Cu is completely depleted from the via. The resistance increase with L is linear. However, as listed in Table 1, the slopes of the curves in Fig. 2 are largely dierent, so that the metal stacks have dierent resistance values even when they have the identical void size. Consequently, Vc is a function of the underlayer type. Table 1 lists Lc and Vc under two common failure criteria. Among the three types studied here, Vc is the largest for the 30 nm Ti/60 nm TiN bilayer. For example, using DRf 10%, Vc of the 30 nm Ti/60 nm TiN underlayer is about 60% larger than Vc of the 25 nm TiN underlayer. In addition, Vc is also a function of failure criterion; Vc becomes larger when DRf 20% is used. It has long been recognized that the refractory layers like TiN and Ti are incorporated to conduct electricity in the absence of Al±Cu due to voiding. The model developed in this work is useful in quantitatively deter-
mining this well-known current-shunting eect. In light of Eq. (1), for example, the data in Fig. 2 and Table 1 show that the metal stack with the 30 nm Ti/60 nm TiN underlayer should have the longest electromigration lifetime among the three cases; using DRf 10%, the lifetime with the 30 nm Ti/60 nm TiN bilayer is expected to be about 60% longer than that with the 25 nm TiN underlayer. Furthermore, Table 1 shows that this lifetime dierence should become even larger when DRf 20% is used. 4. Joule heating due to electromigration voiding The current-shunting eect is limited if the current crowding in the refractory layer causes signi®cant Joule heating. Note that both TiN and Ti are electrically more resistive than Al±Cu, but that they must withstand even larger current densities when L exceeds the via size. For this reason, as the Al±Cu is depleted, Joule heating occurs in the refractory layer of the depleted region. This localized Joule heating is responsible for two reliability
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S.H. Kang, E. Shin / Solid-State Electronics 45 (2001) 341±346
Fig. 2. Eect of the refractory layer con®guration on the resistance increase as a function of the Al±Cu depletion length L (T 250°C; j 106 A/cm2 ). Using the 10% or 20% failure criteria, failures occur when DR is equal to 16.1 X or 32.2 X, respectively. Table 1 The rate of resistance increase d DR=dL for the depletion length L larger than the W-via size, and the critical void length Lc and volume Vc under the 10% and 20% electromigration failure criteria DRf DRf 10%
DRf 20%
Lc (lm)
Vc (lm3 )
Lc (lm)
Vc (lm3 )
34.7
0.772
0.125
1.24
0.201
71.4
0.568
0.092
0.79
0.128
141.9
0.469
0.076
0.58
0.094
d DR=dL (X/lm) 60 nm TiN 30 nm Ti 30 nm TiN 15 nm Ti 25 nm TiN
consequences. First, the Joule heating in the depleted region increases also the temperature of the Al±Cu stripe next to the void front, so that the rate of electromigration is locally accelerated. Second, the larger the Joule heating, the larger the slope d DR=dL in the plot like Fig. 2, since the resistivity of the metal stack increases gradually with T. Fig. 3 plots the temperature increases DT at the hot spots of the refractory layers as a function of L. When L < 0:36 lm, there is essentially no temperature increase. This is not surprising, since the Al±Cu is still in contact with, at least, a part of the W-via. However, DT becomes substantial when L > 0:36 lm, particularly, for the 25 nm TiN ®lm that is the thinnest underlayer in Fig. 3. Coupling these results with those in Fig. 2, it is clear that, the lower the resistance of the
Fig. 3. Eect of Joule heating on the temperature increase DT in the refractory layer of the depleted region as a function of the Al±Cu depletion length L. The substrate T is 250°C.
refractory layer, the better the reliability of the metal stack against electromigration failures. 5. Evaluation of contact misalignment Another subject that can be studied using the model developed here is the eect of contact misalignment on electromigration characteristics. Fig. 4 schematically illustrates the geometrical dierence between a precisely aligned contact and a misaligned contact as much as 0.12 lm. The initial resistance of the metal stack including the contact is 87 X at 250°C, and the simulation results of electromigration voiding as a function of L are shown in Fig. 5. Note that, for the misaligned contact, a sudden resistance increase is observed at L 0:24 lm, which is smaller than 0.36 lm for the aligned contact. This result is expected, since the misaligned case there is no Al(Cu) above the W-contact as soon as the depletion length reaches only 0.24 lm, in contrast to 0.36 lm for the aligned case. Hence, the critical void volume is smaller for the misaligned contact, causing that it is more susceptible to failure. The impact of misalignment on the contact reliability may not be serious if its magnitude is relatively small with respect to the contact size. But, the results suggest that the reliability loss can become a serious concern as the interconnect feature size continuously decreases. 6. Implication From the technological perspective, this work substantiates the fact that the electromigration reliability of the metal stacks is strongly aected by the architecture
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tric ®lms [13,14]. But, note that this diusion barrier is much thinner than the refractory ®lms studied above. As a consequence, it is expected that the rate of resistance increase d DR=dL for Cu interconnects is larger than those in Fig. 2, so that the critical void size for Cu interconnects may be substantially smaller than that for Al±Cu interconnects. We are currently investigating the reliability consequence of incorporating this type of thin diusion barrier by examining experimental results from Cu interconnects using the model developed in this work [17]. 7. Summary
Fig. 4. A ®nite element model showing (a) a precisely aligned and (b) a misaligned contact (depletion length: 0.18 lm).
This paper has presented a 3-D nonlinear thermoelectric ®nite element model to simulate resistance variation and Joule heating as a function of electromigration-induced material depletion. The results demonstrate that the model provides a useful way to calculate the electrical and thermal consequence of voiding by electromigration in multilevel interconnects. Furthermore, the model identi®es Vc (critical void volume) for various interconnect con®gurations. The model is particularly useful in quantitatively evaluating the eect of the architecture and physical properties of refractory ®lms and diusion barriers on the electromigration reliability.
Acknowledgements The authors wish to thank Dr. A.S. Oates at Bell Laboratories, Lucent Technologies and Dr. S. Rzepka at Dresden University of Technology, Germany for their help and valuable discussion. References Fig. 5. Eect of contact misalignment on the resistance increase due to electromigration-induced Al(Cu) depletion.
and properties of the refractory ®lms. The results suggest that it is critical to control the sheet resistance and the thickness of the refractory ®lms. In addition, the refractory ®lms must be defect free since any discontinuity, for example, a microcrack will lead to a catastrophic resistance increase. In this work, we have applied the thermoelectric model to the Al±Cu metallization only. However, the model is applicable also to the Cu metallization that has recently been under extensive investigation [15,16]. The Cu ®lm is coated with a ®lm like Ta or TaN to prevent Cu diusion through dielec-
[1] Hu C-K, Small MB, Ho PS. Electromigration in Al(Cu) two-level structures: eect of Cu and kinetics of damage formation. J Appl Phys 1993;74:969±78. [2] Oates AS. Electromigration failure of contacts and vias in sub-micron integrated circuit metallizations. Microelectron Reliab 1996;36:925±53. [3] Oates AS, Martin EP, Alugbin D, Nkansah F. Comparison of Al electromigration in conventional Al-alloy and Wcontacts to silicon. Appl Phys Lett 1993;62:3273±5. [4] Kawasaki H, Lee C, Anderson SGH, Pintchovski F. The eect of test structure and stress condition on electromigration failure. Third International Workshop on StressInduced Phenomena in Metallization, AIP, Palo Alto, 1995. p. 185. [5] Hu C-K, Lee KY, Lee KL, Cabral C, Colgan EG, Stanis C. Electromigration drift velocity in Al-alloy and Cu-alloy lines. J Electrochem Soc 1996;143:1001±6.
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[6] Kang SH, Oates AS, Obeng YS. 3-D electrical resistance model of via and contact reliability in integrated circuit metallization. Proceedings of 1999 Advanced Metallization Conference, MRS, Pittsburgh, 2000. p. 713±9. [7] Grosjean DE, Okabayashi H. 1-D model of current distribution and resistance changes for electromigration in layered lines. IEEE Trans Electron Dev 1997;44:744±9. [8] ANSYSâ , Version 5.6, 1999. [9] Zienkiewicz OC, Taylor RL. The ®nite element method, vol. 2, 4th ed., Maidenhead: McGraw-Hill; 1991. [10] Hunter WR. The implications of self-consistent current density design guidelines comprehending electromigration and Joule heating for interconnect technology evolution. IEDM Tech Dig 1995;483±6. [11] Robertson SR, Liao K-L. Finite element analysis of nonlinear, coupled thermoelectric problems: the memory switch. J Appl Phys 1991;70:63±8. [12] Rzepka S, Banerjee K, Meusel E, Hu C. Characterization of self-heating in advanced VLSI interconnect lines based on thermal ®nite element simulation. IEEE Trans Comp Packag Manufact Tech 1998;21:406±11.
[13] Clevenger LA, Bojarczuk NA, Holloway K, Harper JME, Cabral C, Schad RG, Cardone F, Stolt L. Comparison of high-vacuum and ultrahigh-vacuum tantalum diusion barrier performance against Cu penetration. J Appl Phys 1993;73:300±8. [14] Tsai MH, Sun SC, Tsai CE, Chuang SH, Chiu HT. Comparison of the diusion barrier properties of chemicalvapor-deposited TaN and sputtered TaN between Cu and Si. J Appl Phys 1996;79:6932±8. [15] Stamper AK, Klaasen WA, Wachnik RA. Critical reliability issues for sub-0.25-micron generation copper wiring. Proceedings of 1999 Advanced Metallization Conference, MRS, Pittsburgh, 2000. p. 9±15. [16] Wu W, Kang SH, Yuan JS, Oates AS. Thermal eect on electromigration performance for Al/SiO2, Cu/SiO2, and Cu/low-k interconnect systems. Solid-State Electron, submitted for publication. [17] Kang SH, Merchant S, Karthikeyan S, Kamat N, Oates AS. Eect of diusion barrier architecture on the electromigration reliability of electroplated Cu interconnects, unpublished work.
A three-dimensional nonlinear analysis of electromigrationinduced resistance change and Joule heating in microelectronic interconnects S.H. Kang a,*, E. Shin b a
Bell Laboratories, Lucent Technologies, 9333 S. John Young Parkway, Orlando, FL 32819, USA b Department of Mathematics, Purdue University, West Lafayette, IN 47906, USA
Received 12 September 2000; received in revised form 15 October 2000; accepted 27 October 2000
Abstract This paper reports a three-dimensional nonlinear numerical model developed for the deep submicron interconnects that carry high current densities in integrated circuits. This model can solve a thermoelectrically coupled ®eld to analyze resistance variation and Joule heating as a function of electromigration-induced voiding in various interconnect structures. As a result, the model can identify the critical void volume that is directly related to the time to electromigration failure. The model is particularly useful as an analytical tool that can quantitatively evaluate the eects of the architecture and physical properties of various refractory ®lms and diusion barriers on the electromigration reliability. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: Microelectronic interconnects; Electromigration; Finite element analysis; Via/contact; Reliability
1. Introduction An integrated circuit (IC) contains a dense array of metallic contacts and interconnects that carry electric current between the various devices on the chip. One of the primary concerns in the manufacture of an IC is to ensure that those metals do not fail by electromigration throughout its expected lifetime. Electromigration damage appears as voids that can grow to raise the electrical resistance to unacceptable values. In general, electromigration failure of deep submicron contacts and interconnects is dominated by voiding at the ends of the metal stripes where vacancies preferentially accumulate under an electric ®eld. This failure mode has been studied extensively [1±4]. It is then well recognized that the resistance escalation that causes interconnects failure is a consequence of void growth. *
Corresponding author. Tel.: +1-407-371-3851; fax: +1-407371-3547. E-mail address: [email protected] (S.H. Kang).
Prior work has shown that the failure kinetics controlled by the void-growth mechanism can be described by two parameters: the critical void volume (Vc ) and the drift velocity (vd ) [2]. These are incorporated in the following equation tg
Vc kT Vc =A ; vd A eZ Dqj
1
where tg is the time to grow a void to failure, A is the cross-sectional area of the metal stripe, k is the Boltzmann constant, T is the metal temperature, e is the electronic charge, Z is an eective charge number, D is the diusion coecient, q is the resistivity of the metal, and j is the eective current density. The critical void volume (Vc ) is de®ned by the amount of materials that must be depleted away from the metal to meet a failure criterion, while the drift velocity (vd ) represents the rate of void growth to Vc . Finding Vc and vd has been a subject of technological interest since electromigration lifetimes can be calculated using Eq. (1). The drift velocity is understood relatively well; vd is a function of the
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driving force (T and j ) and the mechanism (D and Z ) of electromigration [2,5]. At this writing, however, there is very little probative data on Vc . Some possible way of ®nding Vc in realistic metallization structures is ®nite element analysis [6]. In contrast to simpli®ed analytical calculations [7], a ®nite element method can solve a nonlinear, coupled thermoelectric phenomenon like electromigration-induced resistance change even for complex multilevel interconnects. Using the method, the work reported here demonstrates a three-dimensional (3-D) nonlinear thermoelectric model that simulates resistance and temperature changes as a function of electromigration-induced material depletion. This work will show that the model provides an eective way to determine Vc for a variety of metallization con®gurations.
2. Model The 3-D thermoelectric model presented here is written using a general ®nite element code [8], while it is constructed on various forms of user-de®ned functions and macroprograms. The elements used are eight-node hexahedrons that have two degrees of freedom (scalar electric potential and temperature) per node. In the model the electric ®eld causes Joule heating (coupled problem), and both the electric and thermal properties are temperature dependent (nonlinear problem). Hence, a set of the following two constitutive formulations should be solved [9]. First, the formulation for the electrical conduction problem is given by K e fV g fIg;
2
where [K e ], {V}, and {I} are the electrical conductivity matrix, the nodal electric potential, and the applied load vector (current), respectively. Second, the formulation for the heat conduction problem is given by oT fQg 0; 3 K t fT g C ot where [K t ], {T}, {C}, and {Q} are the thermal conductivity matrix, the nodal temperature vector, the heat capacity matrix, and the thermal load vector, respectively. Note that [K e ], [C], and [K t ] depend on {T} while {Q} depends on {T} and {V}. Consequently, Eqs. (2) and (3) must iteratively be solved, i.e., the Joule heat from electrical analysis is passed to thermal analysis as a heat source {Q} while the computed temperatures {T} are used to revise the electrical conductivities {K e } for subsequent iteration. The model ®rst performs a current conduction analysis under a direct-current load at a constant substrate temperature (in this work T 250°C), and determines the electrical potential and current density distribution.
In general, when the simulation is conducted at relatively low current densities (J < 106 A/cm2 ), the eect of Joule heating on the metallization temperature is essentially negligible [6,10]. Hence, reasonably accurate resistance solutions may be obtained without the subsequent thermal simulation. However, the eect of Joule heating is substantial when current densities are larger locally or globally. For this reason the model reported here always requires a heat conduction analysis. An example of the simulated W-via 0:36 0:36 0:9 lm3 structure is shown in Fig. 1. This represents an interconnect that consists of the lower (M1) and the upper (M2) level Al±0.5Cu (wt.%) stripes (width: 0:36 lm, thickness: 0:45 lm, length: 240 lm). These Al± Cu stripes are coated with an overlayer of 25 nm thick TiN and an underlayer of 30 nm Ti/60 nm TiN, 15 nm Ti/30 nm TiN, or 25 nm TiN. We postulate that the narrow Al±Cu stripes have bamboo microstructures. Voiding should then occur predominantly at the end of the Al±Cu stripes, as shown in Fig. 1 (electron ¯ow from M1 to M2). For the purpose of comparison, however, we will apply the model also to the case of ``internal'' voiding. In this work, the temperature-dependent electrical data were measured experimentally. The temperature-dependent thermal data were taken from various literature sources [11,12]. 3. Calculation of the critical void size (Vc ) The calculated initial resistance R0 of the W-via structure in Fig. 1(a) is 160.8 X at T 250°C. The resistance starts to increase as electromigration depletes the Al±Cu under the electric current (J 106 A/cm2 ). Provided that the depleted volume has a hexahedron shape (Fig. 1(b)), the void size is represented by the edge depletion length L. It follows that Vc =A in Eq. (1) can be represented by the critical depletion length Lc . An electromigration failure then occurs when L reaches Lc , i.e., the void volume reaches Vc . Using the common 10% or 20% failure criteria (DRf ), Vc in this work is the void volume when the resistance increase DR R R0 is equal to 16.1 X or 32.2 X, respectively. The results of resistance calculation caused by voiding in the vicinity of the via are plotted in Fig. 2 for three common types of refractory ®lms. For reference, the resistance change due to the void in the middle of the line (internal voiding) is also plotted. Note that, except the case of internal voiding, there are only subtle resistance changes until L reaches the via size. Even when there is no Al±Cu left over the via (i.e. L 0:36 lm), DR is less than 2 X. Thus DR=R0 is less than 1.2%, which is far smaller than the failure criteria. Up to this point, therefore, voiding cannot be a threat to the interconnect reliability. This result is in agreement with experimental ®ndings [2,4].
S.H. Kang, E. Shin / Solid-State Electronics 45 (2001) 341±346
343
Fig. 1. (a) Schematic illustration of the cross-sectional view of the two-level interconnects with the W-via (size: 0.36 lm). (b) A ®nite element model showing the W-via region when the Al±Cu depletion length L is 0.24 lm.
As shown in Fig. 2, however, the resistance starts to increase abruptly when L exceeds the via size. This sudden increase in resistance is associated with the fact that the highly resistive underlayers are the only conducting path to the via after the Al±Cu is completely depleted from the via. The resistance increase with L is linear. However, as listed in Table 1, the slopes of the curves in Fig. 2 are largely dierent, so that the metal stacks have dierent resistance values even when they have the identical void size. Consequently, Vc is a function of the underlayer type. Table 1 lists Lc and Vc under two common failure criteria. Among the three types studied here, Vc is the largest for the 30 nm Ti/60 nm TiN bilayer. For example, using DRf 10%, Vc of the 30 nm Ti/60 nm TiN underlayer is about 60% larger than Vc of the 25 nm TiN underlayer. In addition, Vc is also a function of failure criterion; Vc becomes larger when DRf 20% is used. It has long been recognized that the refractory layers like TiN and Ti are incorporated to conduct electricity in the absence of Al±Cu due to voiding. The model developed in this work is useful in quantitatively deter-
mining this well-known current-shunting eect. In light of Eq. (1), for example, the data in Fig. 2 and Table 1 show that the metal stack with the 30 nm Ti/60 nm TiN underlayer should have the longest electromigration lifetime among the three cases; using DRf 10%, the lifetime with the 30 nm Ti/60 nm TiN bilayer is expected to be about 60% longer than that with the 25 nm TiN underlayer. Furthermore, Table 1 shows that this lifetime dierence should become even larger when DRf 20% is used. 4. Joule heating due to electromigration voiding The current-shunting eect is limited if the current crowding in the refractory layer causes signi®cant Joule heating. Note that both TiN and Ti are electrically more resistive than Al±Cu, but that they must withstand even larger current densities when L exceeds the via size. For this reason, as the Al±Cu is depleted, Joule heating occurs in the refractory layer of the depleted region. This localized Joule heating is responsible for two reliability
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S.H. Kang, E. Shin / Solid-State Electronics 45 (2001) 341±346
Fig. 2. Eect of the refractory layer con®guration on the resistance increase as a function of the Al±Cu depletion length L (T 250°C; j 106 A/cm2 ). Using the 10% or 20% failure criteria, failures occur when DR is equal to 16.1 X or 32.2 X, respectively. Table 1 The rate of resistance increase d DR=dL for the depletion length L larger than the W-via size, and the critical void length Lc and volume Vc under the 10% and 20% electromigration failure criteria DRf DRf 10%
DRf 20%
Lc (lm)
Vc (lm3 )
Lc (lm)
Vc (lm3 )
34.7
0.772
0.125
1.24
0.201
71.4
0.568
0.092
0.79
0.128
141.9
0.469
0.076
0.58
0.094
d DR=dL (X/lm) 60 nm TiN 30 nm Ti 30 nm TiN 15 nm Ti 25 nm TiN
consequences. First, the Joule heating in the depleted region increases also the temperature of the Al±Cu stripe next to the void front, so that the rate of electromigration is locally accelerated. Second, the larger the Joule heating, the larger the slope d DR=dL in the plot like Fig. 2, since the resistivity of the metal stack increases gradually with T. Fig. 3 plots the temperature increases DT at the hot spots of the refractory layers as a function of L. When L < 0:36 lm, there is essentially no temperature increase. This is not surprising, since the Al±Cu is still in contact with, at least, a part of the W-via. However, DT becomes substantial when L > 0:36 lm, particularly, for the 25 nm TiN ®lm that is the thinnest underlayer in Fig. 3. Coupling these results with those in Fig. 2, it is clear that, the lower the resistance of the
Fig. 3. Eect of Joule heating on the temperature increase DT in the refractory layer of the depleted region as a function of the Al±Cu depletion length L. The substrate T is 250°C.
refractory layer, the better the reliability of the metal stack against electromigration failures. 5. Evaluation of contact misalignment Another subject that can be studied using the model developed here is the eect of contact misalignment on electromigration characteristics. Fig. 4 schematically illustrates the geometrical dierence between a precisely aligned contact and a misaligned contact as much as 0.12 lm. The initial resistance of the metal stack including the contact is 87 X at 250°C, and the simulation results of electromigration voiding as a function of L are shown in Fig. 5. Note that, for the misaligned contact, a sudden resistance increase is observed at L 0:24 lm, which is smaller than 0.36 lm for the aligned contact. This result is expected, since the misaligned case there is no Al(Cu) above the W-contact as soon as the depletion length reaches only 0.24 lm, in contrast to 0.36 lm for the aligned case. Hence, the critical void volume is smaller for the misaligned contact, causing that it is more susceptible to failure. The impact of misalignment on the contact reliability may not be serious if its magnitude is relatively small with respect to the contact size. But, the results suggest that the reliability loss can become a serious concern as the interconnect feature size continuously decreases. 6. Implication From the technological perspective, this work substantiates the fact that the electromigration reliability of the metal stacks is strongly aected by the architecture
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tric ®lms [13,14]. But, note that this diusion barrier is much thinner than the refractory ®lms studied above. As a consequence, it is expected that the rate of resistance increase d DR=dL for Cu interconnects is larger than those in Fig. 2, so that the critical void size for Cu interconnects may be substantially smaller than that for Al±Cu interconnects. We are currently investigating the reliability consequence of incorporating this type of thin diusion barrier by examining experimental results from Cu interconnects using the model developed in this work [17]. 7. Summary
Fig. 4. A ®nite element model showing (a) a precisely aligned and (b) a misaligned contact (depletion length: 0.18 lm).
This paper has presented a 3-D nonlinear thermoelectric ®nite element model to simulate resistance variation and Joule heating as a function of electromigration-induced material depletion. The results demonstrate that the model provides a useful way to calculate the electrical and thermal consequence of voiding by electromigration in multilevel interconnects. Furthermore, the model identi®es Vc (critical void volume) for various interconnect con®gurations. The model is particularly useful in quantitatively evaluating the eect of the architecture and physical properties of refractory ®lms and diusion barriers on the electromigration reliability.
Acknowledgements The authors wish to thank Dr. A.S. Oates at Bell Laboratories, Lucent Technologies and Dr. S. Rzepka at Dresden University of Technology, Germany for their help and valuable discussion. References Fig. 5. Eect of contact misalignment on the resistance increase due to electromigration-induced Al(Cu) depletion.
and properties of the refractory ®lms. The results suggest that it is critical to control the sheet resistance and the thickness of the refractory ®lms. In addition, the refractory ®lms must be defect free since any discontinuity, for example, a microcrack will lead to a catastrophic resistance increase. In this work, we have applied the thermoelectric model to the Al±Cu metallization only. However, the model is applicable also to the Cu metallization that has recently been under extensive investigation [15,16]. The Cu ®lm is coated with a ®lm like Ta or TaN to prevent Cu diusion through dielec-
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