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Thermomechanical failures in microelectronic interconnects
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Microelectron. Reliab., Vol. 38, No. 4, pp. 523±529, 1998 # 1998 Elsevier Science Ltd All rights reserved. Printed in Great Britain 0026-2714/98 $19.00 + 0.00 S0026-2714(97)00226-6
THERMOMECHANICAL FAILURES IN MICROELECTRONIC INTERCONNECTS J. W. EVANS Institute for Advanced Engineering, Ajou University Dept. of Systems Engineering, Yong-in Complex, PO Box 25, Kyonggi-do, 449-800, Korea
J. Y. EVANS Dept. of Industrial Engineering, Korea University, Seoul, Korea
P. LALL Advanced Manufacturing Technology, Motorola Corp., Boca Raton, FL, U.S.A.
and S. L. CORNFORD Reliability Engineering Section, Jet Propulsion Laboratory, Pasadena, CA, U.S.A. (Received 14 August 1997; in revised form 17 November 1997) AbstractÐThermomechanical fatigue failures are an important class of failures in microelectronic interconnect structures. Thermomechanical stresses arise from dierences in the coecients of thermal expansion of the various materials comprising a microelectronics circuit. Polymer dielectrics and adhesives have larger coecients of expansion than metal conductors. Dielectrics and adhesives may also exhibit large anisotropy in the coecient of expansion, producing signi®cant thermomechanical stresses in vias or other metal interconnect structures. During ambient thermal cycling or operational power dissipation, cyclic stresses are induced, which cause fatigue failures. The basic elements of thermomechanical fatigue behavior of microelectronic interconnect structures, such as lines and vias, are presented in this paper. In addition, a case study illustrating many of the concepts is presented for a complex 3-D interconnect. # 1998 Elsevier Science Ltd. All rights reserved.
1. INTRODUCTION
The need for size reduction and performance enhancements have consistently driven electronic packaging engineers to develop smaller and highly integrated assemblies. Performance oriented multi-chip modules, dense 3-D memory stacks and lower cost ¯ip-chip on laminate are examples of high density packaging technologies that have emerged into products and systems. The next generation of microsystems will incorporate even greater integration. The emergence of such technologies has resulted in the implementation of a variety of materials to create packaging architectures. Combinations of adhesives and various polymers, such as polyimide, are common for dielectric structures. Copper, gold and aluminum are employed for conductors, while solders and adhesives are used for the ¯ip chip. The materials are combined to create a variety of interconnect structures for microelectronics circuits, including vias, bus lines and bumps which must survive reliably in thermal cycling or thermomechanical environments. 523
2. MATERIALS, THERMOMECHANICAL LOADING AND FATIGUE
The variety of available electronic materials has enabled advancements in size reduction. However, implementation of materials into complex microstructures is not without signi®cant challenges [1]. The typical sets of materials vary greatly in their properties. This presents challenges from a process perspective, but also from a reliability and applications perspective. As shown in Table 1, there are signi®cant dierences in coecients of thermal expansion and modulus of elasticity. The property dierences, combined with temperature changes as a major source of loading, result in stresses in interconnect structures. Power cycling and ambient temperature changes give rise to cyclic stresses. Hence, fatigue induced by temperature cycling is a signi®cant concern in the development of complex structural elements needed for interconnects. 2.1. Dielectric and adhesive materials behavior Dielectrics and adhesives, depending upon their processing, may be highly anisotropic. As re¯ected
524
J. W. Evans et al. Table 1. Interconnect properties [2±4]
Material Polyimide (Kapton) Polyimide (PI 2611) Epoxy adhesives Copper Gold Aluminum Silicon
CTE (ppm/8C)
Modulus elasticity (GPa)
21 x±y, 112 z
4.0±5.0
3 x±y, 148 z 20±40 x±y, 85 z 17 14 25 2.5
3.0±5.0 4.0±5.0 110 82 62 190
in Table 1, various investigators have shown that the out-of-plane coecients of expansion of polyimides, generally the dielectric of choice in advanced interconnects, is much greater than the in-plane expansion. For example, the in-plane coecient of expansion of PI-2611, is 3 ppm/8C, where as the out-of-plane expansion is 148 ppm/8C [2]. Signi®cantly larger out-of-plane coecients of expansion have been reported for other polyimides as well, with the variation depending on the type of polyimide [3]. This eect occurs at the expense of restraining the in-plane expansion, since overall volumetric expansion tends to remain constant [2]. The coecients of thermal expansion will also depend on temperature and thickness. Anisotropy can be expected in thin-®lm epoxy adhesives, as well. Epoxies are generally the choice for adhesives. This is due in part to their superior strength and stability. Overall, the coecient of thermal expansion of epoxies can be expected to range from about 20±40 ppm/8C [4]. When constrained, the out-of-plane expansion may be as high as 85 ppm/8C [5]. In many cases, the lower modulus of elasticity of polymer dielectrics and adhesives is a bene®t leading less load transferred to the interconnect structure. In addition, stress relaxation can occur in the polymer reducing loads on the metal interconnects. Polyimides for example will undergo appreciable creep deformation at elevated test temperatures when hold times exceed 10 minutes [6]. Hence, ®nite element analysis including non-linear constitutive behavior, is often necessary to analyze complex interconnect structures. However, the dimensions of conductors are often much smaller than the dielectrics, leaving the out-of-plane expansion behavior of polymers to dominate when an interconnection is made through dielectric layers. 2.2. Loading in interconnect structures The magnitude of strains induced in a structure as a result of temperature change is a function of the magnitude of the temperature change and the coecient of linear expansion, as expressed by the following familiar relationship: DE aDT
1
a represents the linear coecient of the expansion, De is the thermally induced strain range and D T represents the magnitude of a temperature change. We can understand the generation of stresses by considering the elementary case of elastic deformation in a single direction. Hooke's law for linear elastic materials can be expressed by the simple equation showing the relationship between stress and strain as a linear function of the elastic modulus, E. In this case, the stress in a constrained body can be expressed in terms of Hooke's Law and Equation (1) as follows Ds EDaDT
2
where Da represents the dierence in the coecients of thermal expansion between the restrained body and its supporting structure and Ds represents the stress range induced by a temperature change of D T. Unfortunately, the behavior is often more complex then the simple linear assumptions shown above. In many microelectronic devices, the stress may exceed the yield strength of metal conductors requiring the consideration of elastic and plastic behavior. The geometry of metal structures, such as a vias, may also be relatively complex. Finite element analysis may be necessary to accommodate the complexities of geometry and materials behavior. Finite element analysis has been successfully employed to analyze strains in via structures in aluminum and copper [5, 7]. Linear assumptions in ®nite element analysis or other approaches to structural analysis should be validated in consideration of the loading environment and materials. The linear elastic assumption may only be appropriate for an initial approximation. 2.3. Fatigue in microelectronic metal interconnects The process of fatigue is the mechanism which is responsible for limiting interconnect life in an environment of changing temperature. Fatigue occurs with cyclic loading and unloading with changing environmental temperature or power cycling. Under cyclic loading, localized slip will initiate a crack as a metal interconnect structure is repetitively loaded and unloaded. The crack grows in a stable manner until the cross-section of the structure under load is reduced severely and the nominal load can longer be endured. At this point, failure occurs. Fatigue is generally divided into two regimes. The ®rst is low cycle fatigue. Low cycle fatigue is characterized by high stresses, relative to the yield strength and may involve localized plastic strains. Life is considered to be less than about 104 cycles. High cycle fatigue is characterized by lower stresses and elastic behavior. The cyclic life is generally 105 cycles or greater. It is unfortunate that for vias, bus lines and solder bumps, that fatigue is often in the low cycle or short life regime.
Thermomechanical failures in microelectronic interconnects
Fatigue behavior is described generally by a stress life or strain life approach. The stress-life or S-N approach is the most basic modeling technique and may be applied when there is little knowledge of the fatigue performance of the materials. In this case, Basquin's equation is used to relate the number of cycles to failure to the applied stress range. Basquin's equation may be expressed as: Ds s 0 Nf b
3
s' and b are constants and Nf is the number of cycles to failure. In the application of the stress life approach, one data point may be taken as the ultimate strength of the metal interconnect, provided it is known, where failure is assumed to occur in one cycle. Plotting the log of the stress amplitude, versus the log of Nf results in a straight line. However, a transition in the slope will generally occur within the range of 104±105 cycles as the damage mechanism shifts from low cycle to high cycle fatigue. The Manson±Con fatigue model describes both low and high cycle fatigue regimes, but it is most often used to relate low cycle fatigue behavior DE s 0f 2Nf b E 0f 2Nf c 2 E
4
In this expression, s'f and e'f are constants known as the fatigue strength coecient and the fatigue ductility coecient, respectively, and b and c are known as the fatigue strength exponent and the fatigue ductility exponent, respectively. 2Nf is a reversal and is de®ned to allow for analysis of complex loading spectra. In general, for thermal cycling, there are simply two reversals per cycle. The general approach has been applied to aluminum-silicon alloy interconnects with reasonable accuracy [7]. Fatigue material constants are material properties that may contain considerable variability which contributes to the stochastic nature of fatigue. Several modi®cations to the basic Manson±Con fatigue model have been proposed. Englemaier has proposed the special case of plated copper used in microelectronics. In this case, the Engelmaier modi®cation is expressed as: 5 Su exp Df 0:1785 log 10 =Nf 0:75 DE Nÿ0:6 D 0:9 5 f f E 0:36 In this modi®cation, Df is the measured ductility of plated copper which varies according to plating conditions and may range from 10±30%. The Engelmaier modi®cation has been applied to copper vias for microelectronic interconnects [5, 8]. An examination of the equations expressed above, clearly indicates the need for good materials characterization to be able to apply fatigue prediction models. Bulk materials properties are not adequate. Unfortunately, data for thin ®lm structures are often lacking. An iterative approach, which con-
525
siders sources of variability, should be part of fatigue modeling [7, 9]. Evans et al. [10] have shown the value of applying Monte Carlo simulation coupled to fatigue models to account for sources of variability in life prediction.
3. RELIABILITY ASSESSMENT AND ACCELERATED TESTING
In the development process, characterization and assessment of a materials set selected for interconnect applications is essential. In addition, an assessment of the fatigue life of micro-structural circuit elements through thermal cycling is necessary to evaluate the limitations of devices in use environments. The process necessary to achieve the goal of assessing thermomechanical life is shown in Fig. 1. The advantages of the reliability assessment process in microelectronic and microsystem development are explained in [10]. Accelerated testing is an essential part of reliability assessment for thermomechanical fatigue. Testing must be performed rapidly during the product development process necessitating accelerated testing. Accelerated tests provide the necessary data to validate models and to estimate fatigue life. Models can then be used to project test data to various conditions to assess structural life in application environments. Accelerated thermal cycling tests can be performed over several temperature ranges. Typically, ÿ55 to +125 8C or ÿ65 to +150 8C are ranges applied for accelerated thermal cycling in microelectronics. In these cases, accurate assessment of the interconnect structure thermomechanical performance is essential for proper projection of test results to ®eld or use conditions. In the projection of thermal cycling data, the stresses generated are proportional to the temperature range used in the test as shown by inspection of Equations (1) and (2) . If creep is not a consideration, then Ds A DT and it follows from Equation (3) that:
Fig. 1. Reliability assessment process necessary for eective evaluation of thermomechanical fatigue during development of microelectronic devices.
526
J. W. Evans et al.
Nf use Nf test
DT test DT use
ÿ1=b
6
where b is the exponent from Basquin's equation. It should also be noted that thermal shock tests with ramp rates of greater than 20 8C/minute are undesirable as they may create unrealistic thermal gradients. When creep is a consideration, dwell time must be considered in the projection of test data to use conditions. Finally, sucient sample sizes are needed to characterize the variability of the fatigue life. Life data can best be described by the three parameter Weibull distribution for a given cyclic condition. 4. CASE STUDY IN ADVANCED MICROELECTRONIC DEVICE DEVELOPMENT: 3-D MEMORY STACKS
As we have discussed, cyclic loading induces fatigue crack growth in metal interconnect structures leading to failure. The impact of failure in thermal cycling is to produce an open or intermittent circuit. In the following section, we present a case study in the development of advanced microelectronic devices. Concepts presented earlier in this paper are demonstrated by this analysis. The study presents a fatigue reliability assessment of bus metal fatigue life in a 3-D memory device. In this case, an initial assessment of fatigue behavior of a gold bus metal structure was determined from accelerated test results and ®nite element analysis. A typical 3-D device structure is shown schematically in cross-section in Fig. 2. Descriptions of 3-D
fabrication processes, technologies and related problems may be found in [1, 11]. In considering a 3-D memory stack, the reliability of bus metal structures in thermal cycling is of signi®cant concern. An open bus line in a serial structure will cause the loss of one or more die in the memory stack with corresponding impact to the system. In this case, gold metal bus structures were evaluated by thermal cycling the devices from ÿ55 to +125 8C. The devices were periodically inspected using environmental scanning electron microscopy (ESEM). This allowed for periodic observation with no specimen preparation. The surface of the metal bus was observed and the point of the appearance of cracks was noted. As shown in Fig. 3, cracks were ®rst observed in the structure within 100 cycles followed by observations of cracking at 750 cycles. The test was halted at 1000 cycles. A detailed description of testing procedures may be found in [10]. For modeling the test conditions elastic behavior of the materials was assumed. In this case, creep strains in the polyimide are negligible in the 10 minute hold time of the test [6] and the overall magnitude of the strains in the polyimide is small. In the case of the gold bus lines, the elastic assumption will yield predicted stresses that may be conservatively large, if they exceed the yield strength expected in plated gold. Extensions of the modeling to describe more general materials behavior obviously requires more complex constitutive relationships. However, data for gold thin ®lms is quite sparse. The geometry of the con®guration was taken from measurements obtained in the initial destruc-
Fig. 2. Schematic representation of the cross-section of a 3-D die stack.
Thermomechanical failures in microelectronic interconnects
Fig. 3. ESEM micrograph showing cracking extending across two gold metal bus lines of a 3-D die stack after 100 thermal cycles.
Fig. 4. Von Mises stress distribution in thermal cycling from an FEM analysis of the gold metallization structure used in a 3-D die stack. The boundary conditions and overall structure are shown in Fig. 2.
527
528
J. W. Evans et al. Table 2. Test data analysis
Test stress estimate (MPa) 180 110
Ultimate strength Au (MPa) Basquin's equation exponent 220 240
tive experimental analysis. The boundary conditions, con®guration and materials lay-up are summarized in Fig. 2. The module was assumed to be symmetric and one-half the overall structure was analyzed. The axis of symmetry was along the constrained vertical boundary. Figure 4 shows the distribution of combined Von-Mises stress in the gold metallization in test conditions. At the location that cracks were observed to occur in the ESEM inspections, the maximum Von Mises stress was 180 MPa at the site observed during testing. The stress occurring in this region is of particular interest, since it is known when cracks were observed to initiate during thermal cycling. Therefore, this stress can be related to the time necessary to produce failure. The analysis shows larger stresses at the polyimide-gold interface indicating cracking likely began well before an observed crack was apparent. The actual stresses may be lower due to plastic deformation. The importance of this assumption is discussed later. The yield strength of electroplated gold can be expected to be about 110±120 MPa, while the tensile strength can be expected to be about 220±240 MPa. Consequently, further analysis would require detailed knowledge of the plastic behavior of gold. For gold structures, the material constants in the Manson±Con equation are generally not characterized. Consequently, a stress-life approach can be used as an alternative, to interpret test and analysis data. Since two cyclic regimes were not tested, the ultimate strength for electroplated gold can be used at a life of 1 cycle as an initial data point. The second data point, used to establish an initial S±N curve, was the estimated stress near the surface of the gold bus metallization and the number of cycles at which cracks were ®rst observed in the bus metal in the ESEM. This was at 100 cycles at a range of ÿ55 to +125 8C. In Table 2 we examined the results of the analysis. In considering the simple fatigue model selected, we can estimate the exponent for Basquin's equation. At an ultimate stress of 240 MPa, the exponent, b, is ÿ0.062, considering the FEM results of 180 MPa. This value leads to a projected life, at an industrial use range of ÿ20 to +65 8C of 1.8 107 cycles. This is a typical range for an application such as a robot control box. Considering the elastic assumption of the FEM analysis may yield a non-conservative life projection, we can examine the potential for error by using a lower stress value than the estimated FEM stress. If we take the yield strength as a lower bound and consider the lower
ÿ0.62 ÿ0.15
Use life ÿ20 to +65 8C (cycles) 1.8 107 1.5 104
bound behavior as elastic-perfectly plastic, we can estimate the exponent as b = ÿ 0.15. This yields a lower bound life projection of 1.5 104 cycles, based upon Basquin's equation. This result is within the model boundary. The upper bound of the exponent in Basquin's equation shown in Table 2 compares favorably to published data on thermal cycling induced fatigue in thin ®lms. Data reported by [12] where m = ÿ 1/ b and ranges from 3±6 for most metals in which creep is not a major deformation mechanism. Blish [12] also reported an m value of 5.1 for crack propagation in gold wire bonds, under thermal cycling conditions. It is clear that the elastic assumption, which gives conservative stress estimates, will likely introduce signi®cant error and that a revised ®nite element analysis is necessary to improve accuracy. The approach in this case represents a method to provide initial estimates of the fatigue performance for an electroplated bus metal structure. Ongoing research and materials characterization are needed to improve life estimates. However, the performance of the gold bus metal was demonstrated to be relatively robust for typical use environments based on the small sample size.
5. CONCLUSIONS
The stresses in an interconnect structure are driven by dierences in the coecients of expansion between the various materials which comprise the structure. Signi®cant stresses will result during operation temperature changes. In polyimides and epoxies which are used for dielectrics and adhesives, the dierence in the coecient of thermal expansion between these materials and surrounding structures, such as metal bus lines, can be signi®cant. Polyimides in particular, are anisotropic, and their out-of-plane coecient of thermal expansion can be one to two orders of magnitude greater than inplane. This can signi®cantly increase out-of-plane stresses and limit cyclic life. An overview of thermomechanical fatigue in microelectronics, including a methodology of reliability assessment embodied in Fig. 1, has been presented. This paper underscores the need for implementation of eective reliability assessment and fatigue evaluation. This requires knowledge of materials, accelerated testing and application of appropriate fatigue models. The case study, presented on the development of 3-D interconnects, shows the
Thermomechanical failures in microelectronic interconnects
implementation of the process and demonstrates the problems encountered in advanced device development. AcknowledgementsÐThe authors would like to express their appreciation to Dr. Michael Pecht and Dr. Abhijit Dasgupta of the University of Maryland CALCE Electronic Packaging Research Center for their advice and to Dr. Mark Fan of Swales and Associates in Greenbelt, Maryland and Dr. Mary Li of the University of Maryland, Center for Microanalysis for their contributions to the case study. REFERENCES 1. Pecht, M., Dasgupta, A., Evans, J. and Evans, J., Quality Conformance and Quali®cation of Microelectronic Packages and Interconnects, John Wiley and Sons, New York, 1994. 2. Pottinger, M., Coburn, J. and Edman, I., Journal of Polymer ScienceÐPart B, Polymer Physics 1994, 32(5). 3. Pecht, M. and Wu, X., Characterization of polyimides used in high density interconnects, Proceedings of the IEEE Transactions on Components, Packaging and Manufacturing TechnologyÐPart B, Vol. 17, No. 4, November, 1994. 4. Evans, J. Y. and Evans, J. W., Electronic Materials and Properties, Handbook of Electronic Package Design. M. Pecht, ed. Marcel Dekker, New York, 1991.
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5. Prabhu, A., Barker, D. B., Pecht, M., Evans, J., Grieg, W., Bernard, E. and Smith, E. A., in Proceedings of the ASME International, Intersociety Electronic Packaging Conference. Lahaina, Hawaii, 1995. 6. Ho, P., SRC Report, Semiconductor Research Corporation, U.S.A., 1995. 7. Newell, J. N., Larson, T. W. and Cornford, S. L., A thermo-mechanical stress analysis of an MCM-D interconnect, in Proceedings of the Pan Paci®c Microelectronics Symposium, Honolulu, Hawaii, 1996. 8. Evans, J. W., Evans, J. Y., Prabhu, A. and Dasgupta, A., Software environment for reliability assessment of advanced interconnect technologies, in Proceedings of ASME International, Intersociety Electronic Packaging Conference, Lahaina, Hawaii, 1995. 9. Evans, J. W., Evans, J. Y. and Yu, B. K., Designing and building in reliability in advanced microelectronics assemblies and structures. IEEE Transactions on Components Packaging and Manufacturing TechnologyÐPart A, No. 1, March, 1997. 10. Evans, J. Y., Evans, J. W. and Li, M. J., Eects of humidity and temperature cycling on 3-D packaging, in Proceedings of the IEEE IPFA Conference, Singapore, 1997. 11. Evans, J. Y., High density 3-D electronic packaging technology, in Proceedings of the World Technology Conference, Seoul, Korea, 1993. 12. Blish, R. C., Temperature cycling and thermal shock failure rate modeling. 35th IEEE IRPS Symposium, 1997.
Microelectron. Reliab., Vol. 38, No. 4, pp. 523±529, 1998 # 1998 Elsevier Science Ltd All rights reserved. Printed in Great Britain 0026-2714/98 $19.00 + 0.00 S0026-2714(97)00226-6
THERMOMECHANICAL FAILURES IN MICROELECTRONIC INTERCONNECTS J. W. EVANS Institute for Advanced Engineering, Ajou University Dept. of Systems Engineering, Yong-in Complex, PO Box 25, Kyonggi-do, 449-800, Korea
J. Y. EVANS Dept. of Industrial Engineering, Korea University, Seoul, Korea
P. LALL Advanced Manufacturing Technology, Motorola Corp., Boca Raton, FL, U.S.A.
and S. L. CORNFORD Reliability Engineering Section, Jet Propulsion Laboratory, Pasadena, CA, U.S.A. (Received 14 August 1997; in revised form 17 November 1997) AbstractÐThermomechanical fatigue failures are an important class of failures in microelectronic interconnect structures. Thermomechanical stresses arise from dierences in the coecients of thermal expansion of the various materials comprising a microelectronics circuit. Polymer dielectrics and adhesives have larger coecients of expansion than metal conductors. Dielectrics and adhesives may also exhibit large anisotropy in the coecient of expansion, producing signi®cant thermomechanical stresses in vias or other metal interconnect structures. During ambient thermal cycling or operational power dissipation, cyclic stresses are induced, which cause fatigue failures. The basic elements of thermomechanical fatigue behavior of microelectronic interconnect structures, such as lines and vias, are presented in this paper. In addition, a case study illustrating many of the concepts is presented for a complex 3-D interconnect. # 1998 Elsevier Science Ltd. All rights reserved.
1. INTRODUCTION
The need for size reduction and performance enhancements have consistently driven electronic packaging engineers to develop smaller and highly integrated assemblies. Performance oriented multi-chip modules, dense 3-D memory stacks and lower cost ¯ip-chip on laminate are examples of high density packaging technologies that have emerged into products and systems. The next generation of microsystems will incorporate even greater integration. The emergence of such technologies has resulted in the implementation of a variety of materials to create packaging architectures. Combinations of adhesives and various polymers, such as polyimide, are common for dielectric structures. Copper, gold and aluminum are employed for conductors, while solders and adhesives are used for the ¯ip chip. The materials are combined to create a variety of interconnect structures for microelectronics circuits, including vias, bus lines and bumps which must survive reliably in thermal cycling or thermomechanical environments. 523
2. MATERIALS, THERMOMECHANICAL LOADING AND FATIGUE
The variety of available electronic materials has enabled advancements in size reduction. However, implementation of materials into complex microstructures is not without signi®cant challenges [1]. The typical sets of materials vary greatly in their properties. This presents challenges from a process perspective, but also from a reliability and applications perspective. As shown in Table 1, there are signi®cant dierences in coecients of thermal expansion and modulus of elasticity. The property dierences, combined with temperature changes as a major source of loading, result in stresses in interconnect structures. Power cycling and ambient temperature changes give rise to cyclic stresses. Hence, fatigue induced by temperature cycling is a signi®cant concern in the development of complex structural elements needed for interconnects. 2.1. Dielectric and adhesive materials behavior Dielectrics and adhesives, depending upon their processing, may be highly anisotropic. As re¯ected
524
J. W. Evans et al. Table 1. Interconnect properties [2±4]
Material Polyimide (Kapton) Polyimide (PI 2611) Epoxy adhesives Copper Gold Aluminum Silicon
CTE (ppm/8C)
Modulus elasticity (GPa)
21 x±y, 112 z
4.0±5.0
3 x±y, 148 z 20±40 x±y, 85 z 17 14 25 2.5
3.0±5.0 4.0±5.0 110 82 62 190
in Table 1, various investigators have shown that the out-of-plane coecients of expansion of polyimides, generally the dielectric of choice in advanced interconnects, is much greater than the in-plane expansion. For example, the in-plane coecient of expansion of PI-2611, is 3 ppm/8C, where as the out-of-plane expansion is 148 ppm/8C [2]. Signi®cantly larger out-of-plane coecients of expansion have been reported for other polyimides as well, with the variation depending on the type of polyimide [3]. This eect occurs at the expense of restraining the in-plane expansion, since overall volumetric expansion tends to remain constant [2]. The coecients of thermal expansion will also depend on temperature and thickness. Anisotropy can be expected in thin-®lm epoxy adhesives, as well. Epoxies are generally the choice for adhesives. This is due in part to their superior strength and stability. Overall, the coecient of thermal expansion of epoxies can be expected to range from about 20±40 ppm/8C [4]. When constrained, the out-of-plane expansion may be as high as 85 ppm/8C [5]. In many cases, the lower modulus of elasticity of polymer dielectrics and adhesives is a bene®t leading less load transferred to the interconnect structure. In addition, stress relaxation can occur in the polymer reducing loads on the metal interconnects. Polyimides for example will undergo appreciable creep deformation at elevated test temperatures when hold times exceed 10 minutes [6]. Hence, ®nite element analysis including non-linear constitutive behavior, is often necessary to analyze complex interconnect structures. However, the dimensions of conductors are often much smaller than the dielectrics, leaving the out-of-plane expansion behavior of polymers to dominate when an interconnection is made through dielectric layers. 2.2. Loading in interconnect structures The magnitude of strains induced in a structure as a result of temperature change is a function of the magnitude of the temperature change and the coecient of linear expansion, as expressed by the following familiar relationship: DE aDT
1
a represents the linear coecient of the expansion, De is the thermally induced strain range and D T represents the magnitude of a temperature change. We can understand the generation of stresses by considering the elementary case of elastic deformation in a single direction. Hooke's law for linear elastic materials can be expressed by the simple equation showing the relationship between stress and strain as a linear function of the elastic modulus, E. In this case, the stress in a constrained body can be expressed in terms of Hooke's Law and Equation (1) as follows Ds EDaDT
2
where Da represents the dierence in the coecients of thermal expansion between the restrained body and its supporting structure and Ds represents the stress range induced by a temperature change of D T. Unfortunately, the behavior is often more complex then the simple linear assumptions shown above. In many microelectronic devices, the stress may exceed the yield strength of metal conductors requiring the consideration of elastic and plastic behavior. The geometry of metal structures, such as a vias, may also be relatively complex. Finite element analysis may be necessary to accommodate the complexities of geometry and materials behavior. Finite element analysis has been successfully employed to analyze strains in via structures in aluminum and copper [5, 7]. Linear assumptions in ®nite element analysis or other approaches to structural analysis should be validated in consideration of the loading environment and materials. The linear elastic assumption may only be appropriate for an initial approximation. 2.3. Fatigue in microelectronic metal interconnects The process of fatigue is the mechanism which is responsible for limiting interconnect life in an environment of changing temperature. Fatigue occurs with cyclic loading and unloading with changing environmental temperature or power cycling. Under cyclic loading, localized slip will initiate a crack as a metal interconnect structure is repetitively loaded and unloaded. The crack grows in a stable manner until the cross-section of the structure under load is reduced severely and the nominal load can longer be endured. At this point, failure occurs. Fatigue is generally divided into two regimes. The ®rst is low cycle fatigue. Low cycle fatigue is characterized by high stresses, relative to the yield strength and may involve localized plastic strains. Life is considered to be less than about 104 cycles. High cycle fatigue is characterized by lower stresses and elastic behavior. The cyclic life is generally 105 cycles or greater. It is unfortunate that for vias, bus lines and solder bumps, that fatigue is often in the low cycle or short life regime.
Thermomechanical failures in microelectronic interconnects
Fatigue behavior is described generally by a stress life or strain life approach. The stress-life or S-N approach is the most basic modeling technique and may be applied when there is little knowledge of the fatigue performance of the materials. In this case, Basquin's equation is used to relate the number of cycles to failure to the applied stress range. Basquin's equation may be expressed as: Ds s 0 Nf b
3
s' and b are constants and Nf is the number of cycles to failure. In the application of the stress life approach, one data point may be taken as the ultimate strength of the metal interconnect, provided it is known, where failure is assumed to occur in one cycle. Plotting the log of the stress amplitude, versus the log of Nf results in a straight line. However, a transition in the slope will generally occur within the range of 104±105 cycles as the damage mechanism shifts from low cycle to high cycle fatigue. The Manson±Con fatigue model describes both low and high cycle fatigue regimes, but it is most often used to relate low cycle fatigue behavior DE s 0f 2Nf b E 0f 2Nf c 2 E
4
In this expression, s'f and e'f are constants known as the fatigue strength coecient and the fatigue ductility coecient, respectively, and b and c are known as the fatigue strength exponent and the fatigue ductility exponent, respectively. 2Nf is a reversal and is de®ned to allow for analysis of complex loading spectra. In general, for thermal cycling, there are simply two reversals per cycle. The general approach has been applied to aluminum-silicon alloy interconnects with reasonable accuracy [7]. Fatigue material constants are material properties that may contain considerable variability which contributes to the stochastic nature of fatigue. Several modi®cations to the basic Manson±Con fatigue model have been proposed. Englemaier has proposed the special case of plated copper used in microelectronics. In this case, the Engelmaier modi®cation is expressed as: 5 Su exp Df 0:1785 log 10 =Nf 0:75 DE Nÿ0:6 D 0:9 5 f f E 0:36 In this modi®cation, Df is the measured ductility of plated copper which varies according to plating conditions and may range from 10±30%. The Engelmaier modi®cation has been applied to copper vias for microelectronic interconnects [5, 8]. An examination of the equations expressed above, clearly indicates the need for good materials characterization to be able to apply fatigue prediction models. Bulk materials properties are not adequate. Unfortunately, data for thin ®lm structures are often lacking. An iterative approach, which con-
525
siders sources of variability, should be part of fatigue modeling [7, 9]. Evans et al. [10] have shown the value of applying Monte Carlo simulation coupled to fatigue models to account for sources of variability in life prediction.
3. RELIABILITY ASSESSMENT AND ACCELERATED TESTING
In the development process, characterization and assessment of a materials set selected for interconnect applications is essential. In addition, an assessment of the fatigue life of micro-structural circuit elements through thermal cycling is necessary to evaluate the limitations of devices in use environments. The process necessary to achieve the goal of assessing thermomechanical life is shown in Fig. 1. The advantages of the reliability assessment process in microelectronic and microsystem development are explained in [10]. Accelerated testing is an essential part of reliability assessment for thermomechanical fatigue. Testing must be performed rapidly during the product development process necessitating accelerated testing. Accelerated tests provide the necessary data to validate models and to estimate fatigue life. Models can then be used to project test data to various conditions to assess structural life in application environments. Accelerated thermal cycling tests can be performed over several temperature ranges. Typically, ÿ55 to +125 8C or ÿ65 to +150 8C are ranges applied for accelerated thermal cycling in microelectronics. In these cases, accurate assessment of the interconnect structure thermomechanical performance is essential for proper projection of test results to ®eld or use conditions. In the projection of thermal cycling data, the stresses generated are proportional to the temperature range used in the test as shown by inspection of Equations (1) and (2) . If creep is not a consideration, then Ds A DT and it follows from Equation (3) that:
Fig. 1. Reliability assessment process necessary for eective evaluation of thermomechanical fatigue during development of microelectronic devices.
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Nf use Nf test
DT test DT use
ÿ1=b
6
where b is the exponent from Basquin's equation. It should also be noted that thermal shock tests with ramp rates of greater than 20 8C/minute are undesirable as they may create unrealistic thermal gradients. When creep is a consideration, dwell time must be considered in the projection of test data to use conditions. Finally, sucient sample sizes are needed to characterize the variability of the fatigue life. Life data can best be described by the three parameter Weibull distribution for a given cyclic condition. 4. CASE STUDY IN ADVANCED MICROELECTRONIC DEVICE DEVELOPMENT: 3-D MEMORY STACKS
As we have discussed, cyclic loading induces fatigue crack growth in metal interconnect structures leading to failure. The impact of failure in thermal cycling is to produce an open or intermittent circuit. In the following section, we present a case study in the development of advanced microelectronic devices. Concepts presented earlier in this paper are demonstrated by this analysis. The study presents a fatigue reliability assessment of bus metal fatigue life in a 3-D memory device. In this case, an initial assessment of fatigue behavior of a gold bus metal structure was determined from accelerated test results and ®nite element analysis. A typical 3-D device structure is shown schematically in cross-section in Fig. 2. Descriptions of 3-D
fabrication processes, technologies and related problems may be found in [1, 11]. In considering a 3-D memory stack, the reliability of bus metal structures in thermal cycling is of signi®cant concern. An open bus line in a serial structure will cause the loss of one or more die in the memory stack with corresponding impact to the system. In this case, gold metal bus structures were evaluated by thermal cycling the devices from ÿ55 to +125 8C. The devices were periodically inspected using environmental scanning electron microscopy (ESEM). This allowed for periodic observation with no specimen preparation. The surface of the metal bus was observed and the point of the appearance of cracks was noted. As shown in Fig. 3, cracks were ®rst observed in the structure within 100 cycles followed by observations of cracking at 750 cycles. The test was halted at 1000 cycles. A detailed description of testing procedures may be found in [10]. For modeling the test conditions elastic behavior of the materials was assumed. In this case, creep strains in the polyimide are negligible in the 10 minute hold time of the test [6] and the overall magnitude of the strains in the polyimide is small. In the case of the gold bus lines, the elastic assumption will yield predicted stresses that may be conservatively large, if they exceed the yield strength expected in plated gold. Extensions of the modeling to describe more general materials behavior obviously requires more complex constitutive relationships. However, data for gold thin ®lms is quite sparse. The geometry of the con®guration was taken from measurements obtained in the initial destruc-
Fig. 2. Schematic representation of the cross-section of a 3-D die stack.
Thermomechanical failures in microelectronic interconnects
Fig. 3. ESEM micrograph showing cracking extending across two gold metal bus lines of a 3-D die stack after 100 thermal cycles.
Fig. 4. Von Mises stress distribution in thermal cycling from an FEM analysis of the gold metallization structure used in a 3-D die stack. The boundary conditions and overall structure are shown in Fig. 2.
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Test stress estimate (MPa) 180 110
Ultimate strength Au (MPa) Basquin's equation exponent 220 240
tive experimental analysis. The boundary conditions, con®guration and materials lay-up are summarized in Fig. 2. The module was assumed to be symmetric and one-half the overall structure was analyzed. The axis of symmetry was along the constrained vertical boundary. Figure 4 shows the distribution of combined Von-Mises stress in the gold metallization in test conditions. At the location that cracks were observed to occur in the ESEM inspections, the maximum Von Mises stress was 180 MPa at the site observed during testing. The stress occurring in this region is of particular interest, since it is known when cracks were observed to initiate during thermal cycling. Therefore, this stress can be related to the time necessary to produce failure. The analysis shows larger stresses at the polyimide-gold interface indicating cracking likely began well before an observed crack was apparent. The actual stresses may be lower due to plastic deformation. The importance of this assumption is discussed later. The yield strength of electroplated gold can be expected to be about 110±120 MPa, while the tensile strength can be expected to be about 220±240 MPa. Consequently, further analysis would require detailed knowledge of the plastic behavior of gold. For gold structures, the material constants in the Manson±Con equation are generally not characterized. Consequently, a stress-life approach can be used as an alternative, to interpret test and analysis data. Since two cyclic regimes were not tested, the ultimate strength for electroplated gold can be used at a life of 1 cycle as an initial data point. The second data point, used to establish an initial S±N curve, was the estimated stress near the surface of the gold bus metallization and the number of cycles at which cracks were ®rst observed in the bus metal in the ESEM. This was at 100 cycles at a range of ÿ55 to +125 8C. In Table 2 we examined the results of the analysis. In considering the simple fatigue model selected, we can estimate the exponent for Basquin's equation. At an ultimate stress of 240 MPa, the exponent, b, is ÿ0.062, considering the FEM results of 180 MPa. This value leads to a projected life, at an industrial use range of ÿ20 to +65 8C of 1.8 107 cycles. This is a typical range for an application such as a robot control box. Considering the elastic assumption of the FEM analysis may yield a non-conservative life projection, we can examine the potential for error by using a lower stress value than the estimated FEM stress. If we take the yield strength as a lower bound and consider the lower
ÿ0.62 ÿ0.15
Use life ÿ20 to +65 8C (cycles) 1.8 107 1.5 104
bound behavior as elastic-perfectly plastic, we can estimate the exponent as b = ÿ 0.15. This yields a lower bound life projection of 1.5 104 cycles, based upon Basquin's equation. This result is within the model boundary. The upper bound of the exponent in Basquin's equation shown in Table 2 compares favorably to published data on thermal cycling induced fatigue in thin ®lms. Data reported by [12] where m = ÿ 1/ b and ranges from 3±6 for most metals in which creep is not a major deformation mechanism. Blish [12] also reported an m value of 5.1 for crack propagation in gold wire bonds, under thermal cycling conditions. It is clear that the elastic assumption, which gives conservative stress estimates, will likely introduce signi®cant error and that a revised ®nite element analysis is necessary to improve accuracy. The approach in this case represents a method to provide initial estimates of the fatigue performance for an electroplated bus metal structure. Ongoing research and materials characterization are needed to improve life estimates. However, the performance of the gold bus metal was demonstrated to be relatively robust for typical use environments based on the small sample size.
5. CONCLUSIONS
The stresses in an interconnect structure are driven by dierences in the coecients of expansion between the various materials which comprise the structure. Signi®cant stresses will result during operation temperature changes. In polyimides and epoxies which are used for dielectrics and adhesives, the dierence in the coecient of thermal expansion between these materials and surrounding structures, such as metal bus lines, can be signi®cant. Polyimides in particular, are anisotropic, and their out-of-plane coecient of thermal expansion can be one to two orders of magnitude greater than inplane. This can signi®cantly increase out-of-plane stresses and limit cyclic life. An overview of thermomechanical fatigue in microelectronics, including a methodology of reliability assessment embodied in Fig. 1, has been presented. This paper underscores the need for implementation of eective reliability assessment and fatigue evaluation. This requires knowledge of materials, accelerated testing and application of appropriate fatigue models. The case study, presented on the development of 3-D interconnects, shows the
Thermomechanical failures in microelectronic interconnects
implementation of the process and demonstrates the problems encountered in advanced device development. AcknowledgementsÐThe authors would like to express their appreciation to Dr. Michael Pecht and Dr. Abhijit Dasgupta of the University of Maryland CALCE Electronic Packaging Research Center for their advice and to Dr. Mark Fan of Swales and Associates in Greenbelt, Maryland and Dr. Mary Li of the University of Maryland, Center for Microanalysis for their contributions to the case study. REFERENCES 1. Pecht, M., Dasgupta, A., Evans, J. and Evans, J., Quality Conformance and Quali®cation of Microelectronic Packages and Interconnects, John Wiley and Sons, New York, 1994. 2. Pottinger, M., Coburn, J. and Edman, I., Journal of Polymer ScienceÐPart B, Polymer Physics 1994, 32(5). 3. Pecht, M. and Wu, X., Characterization of polyimides used in high density interconnects, Proceedings of the IEEE Transactions on Components, Packaging and Manufacturing TechnologyÐPart B, Vol. 17, No. 4, November, 1994. 4. Evans, J. Y. and Evans, J. W., Electronic Materials and Properties, Handbook of Electronic Package Design. M. Pecht, ed. Marcel Dekker, New York, 1991.
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5. Prabhu, A., Barker, D. B., Pecht, M., Evans, J., Grieg, W., Bernard, E. and Smith, E. A., in Proceedings of the ASME International, Intersociety Electronic Packaging Conference. Lahaina, Hawaii, 1995. 6. Ho, P., SRC Report, Semiconductor Research Corporation, U.S.A., 1995. 7. Newell, J. N., Larson, T. W. and Cornford, S. L., A thermo-mechanical stress analysis of an MCM-D interconnect, in Proceedings of the Pan Paci®c Microelectronics Symposium, Honolulu, Hawaii, 1996. 8. Evans, J. W., Evans, J. Y., Prabhu, A. and Dasgupta, A., Software environment for reliability assessment of advanced interconnect technologies, in Proceedings of ASME International, Intersociety Electronic Packaging Conference, Lahaina, Hawaii, 1995. 9. Evans, J. W., Evans, J. Y. and Yu, B. K., Designing and building in reliability in advanced microelectronics assemblies and structures. IEEE Transactions on Components Packaging and Manufacturing TechnologyÐPart A, No. 1, March, 1997. 10. Evans, J. Y., Evans, J. W. and Li, M. J., Eects of humidity and temperature cycling on 3-D packaging, in Proceedings of the IEEE IPFA Conference, Singapore, 1997. 11. Evans, J. Y., High density 3-D electronic packaging technology, in Proceedings of the World Technology Conference, Seoul, Korea, 1993. 12. Blish, R. C., Temperature cycling and thermal shock failure rate modeling. 35th IEEE IRPS Symposium, 1997.