A tunable CMOS Wilkinson power divider using active inductors

Int. J. Electron. Commun. (AEÜ) 66 (2012) 655–658

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A tunable CMOS Wilkinson power divider using active inductors Sen Wang ∗ , Rui-Xian Wang Graduate Institute of Computer and Communication Engineering, National Taipei University of Technology, 1, Sec. 3, Chung-hsiao E. Road, Taipei 10608, Taiwan, ROC

a r t i c l e

i n f o

Article history: Received 22 September 2011 Accepted 6 December 2011 Keywords: Active inductors Wilkinson power dividers Lumped circuits CMOS

a b s t r a c t This paper presents the design and implementation of a tunable CMOS Wilkinson power divider using active inductors. Compared to a conventional active inductor topology, the proposed active inductor features higher inductance tuning range, higher self-resonant frequency, and lower power consumption by introducing two additional transistors. Benefitting from the superior inductor, the low-loss Wilkinson power divider is practical while maintaining a wide tuning range. The design consuming 10.2 mW demonstrates an insertion loss of 0.67 dB, a return loss of 27 dB, and an isolation of 22.6 dB at 8 GHz. Moreover, the tuning range of the circuit is between 5.8 GHz and 10.4 GHz, rendering a 4.6 GHz bandwidth. The active chip size of the lumped design is merely 0.25 mm × 0.15 mm. © 2012 Elsevier GmbH. All rights reserved.

1. Introduction Conventional Wilkinson power dividers (WPDs) are widely used in the radio-frequency (RF) frond-end of communication systems for equal power splitting with in-phase responses at different output ports [1–4]. Recently, many dual-band, multi-band, and unequal power splitting WPDs are reported for facilitating the system integration and simplifying the architecture of the RF fontend [5–7]. However, these transmission line (TL) based WPDs on the printed-circuit board (PCB) still occupy large chip area compared to on-chip circuits, and thus increase the cost and incur additional power consumption of packaging. CMOS technologies feature low-cost manufacturing and high-volume integrating capabilities, and rapid developments of wireless communications make systems on a single chip (SOC) practical [8,9]. However, frequencyscaling and TL-based circuits do not benefit from the accelerated process scaling of CMOS technologies. Therefore most of on-chip distributed circuits are implemented at millimeter-wave frequencies for the chip area and insertion loss consideration. [10,11]. Moreover, peak-Q factors of CMOS inductors suffering from its lowresistivity substrate are around 10, which limits lumped designs by LC components at microwave frequencies. Typically, acceptable performances of the passive circuits require inductors with Q-factor of 30 at least. To reduce the circuit size of distributed TLs and low-Q passive inductors, many applications of active inductors which are suitable for monolithic system integration are presented [12–15]. Advantages of the active inductor include the high-Q factor, reduced

∗ Corresponding author. Tel.: +886 2 2771 2171x2226; fax: +886 2 2731 7120. E-mail addresses: [email protected] (S. Wang), [email protected] (R.-X. Wang). 1434-8411/$ – see front matter © 2012 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2011.12.005

chip area, and easily integrated with other circuits in a single chip. These circuits successfully demonstrate a good electrical performance and a significant area reduction due to the active inductors. However, the transistor-based inductors also pay for a high power dc consumption, high noise level, poor linearity, and low operating frequencies. In this paper, a tunable Wilkinson power divider using active inductors is designed and fabricated. Compared to a conventional active inductor topology, the proposed active inductor features higher inductance tuning range, higher self-resonant frequency, and lower power consumption by introducing two additional transistors. With the high-Q factors and tunable inductances provided by the proposed active inductors, the WPD exhibits enhanced performance in terms of insertion loss, return loss, and port isolation while maintaining a wide frequency tuning range. The design will be detailed in the following sections. In Section 2, the design of the tunable Wilkinson power divider will be presented. Moreover, simulated and measured results of the design implemented in a standard 0.18-␮m CMOS process are also reported in Section 3. Finally, Section 4 concludes this work.

2. Design of tunable Wilkinson power divider Fig. 1(a) depicts a conventional TL-based WPD with two 3/4long TLs and one isolation resistor between the output ports. A distributed TL with a characteristic impedance of Z0 and an electrical length of ˇl can be equivalent to its lumped equivalent T-networks as shown in Fig. 1(b). The lumped LC components can be derived from the ABCD matrices of a 3/4-long TL and the lumped T-network. Therefore, by equating the matrices in (1) the corresponding Cs and Lp can be obtained as shown in (2) and (3). Where ω is the operating frequency, and Z0 is 50  in the equations. Typically, inferior Q-factors of CMOS inductors degrade the

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S. Wang, R.-X. Wang / Int. J. Electron. Commun. (AEÜ) 66 (2012) 655–658 Table 1 Circuit parameters of the Wilkinson power divider.

Fig. 1. (a) A distributed Wilkinson power divider. (b) A lumped Wilkinson power divider.

electrical characteristics such as insertion losses, return losses, and isolation of a WPD. To improve the low-Q factors and to avoid the area-consuming passive inductors, a high-Q and high self-resonant frequency active inductor with low-power consumption is developed for the lumped WPD.



cos ˇl jY0 sin ˇl

jZ0 sin ˇl cos ˇl





=

⎡

1−

=

−jZ0 0

0 −jY0

⎢ ⎣ 1

1 ω2 Lp Cs

jωLp



1 2 − jωCs jω3 Cs2 Lp 1 1− 2 ω Lp Cs

1 Cs = √ 2Z0 ω √ 2Z0 Lp = ω

⎤ ⎥ ⎦ (1)

Unit

Designed value

M1 M2 M3 M4 R C I1 I2 I3 Vd Vt

␮m/␮m ␮m/␮m ␮m/␮m ␮m/␮m  pF mA mA mA V V

62/0.18 49.6/0.18 32/0.18 50.4/0.18 100 0.28 0.68–1.45 0.9–2.1 0.28–1.8 1.5–1.8 1.4–2

unstable, especially at high frequencies. In order to avoid the body effect of M2 and M3 , these transistors are all implemented in separate regions and wells. By adding the M4 , the term gds4 /gm4 will result in a decrease of Req because gm4 is much larger than gds4 . Therefore, the M4 can be controlled by varying I3 or Vt , and the Q factors of the inductor can be tuned independently at operating frequencies. Moreover, the M4 is designed to minimize circuit power consumption and maintain circuit stability, which will not degrade the inductor at high frequencies. Table 1 summarizes the design parameters and the current settings of the proposed circuit. Leq 

(2)

(3)

Fig. 2 shows the complete schematic of the proposed lumped WPD using two active inductors. A conventional active inductor only consists of a back-to-back configuration of transistors M1 and M2 [12–15]. And the equivalent inductance and Q factors can be merely tuned by the aspect ratio and trans-conductance of the two transistors. Moreover, this topology is impractical due to the excess phase error and trans-conductance degradation contributed by the intrinsic device capacitances at higher frequencies (>5 GHz) [16]. The proposed active inductor introduces two additional transistors M3 and M4 as shown in Fig. 2. In order to simplify the analysis, two assumptions gm  gds and Cgs  Cgd in the transistors are supposed, and the analysis procedure is similar to [17]. Then the input impedance Zin including an inductance Leq in series with a resistance Req can be approximated Eqs. (4) and (5). The transistor M3 stacking on top of M1 contributes a negative resistance to compensate resistive losses of the inductor. The active inductor is mainly determined by M1 , M2 , and M3 . Typically, a large Cgs3 while maintaining circuit stability is favorable for a high-Q inductor with low-power consumption. And unnecessary negative resistances of the active inductor would result in circuit potentially

Fig. 2. Schematic of the proposed Wilkinson power divider.

Device and setting

Req 

2 C gm2 gm3 Cgs2 + ω2 Cgs2 gs3 2 g 2 2 gm1 gm2 m3 + ω gm1 gm3 Cgs2

gm2 gds3 gds1 (gds4 /gm4 ) + ω2 Cgs2 (gm3 Cgs2 − gm2 Cgs3 ) 2 g 2 2 gm1 gm2 m3 + ω gm1 gm3 Cgs2

(4)

(5)

The active inductor is conducted by the advanced design system (ADS) simulator, and the capacitors or interconnections are conducted by the full-wave electromagnetic, or high frequency structure simulator (HFSS). Fig. 3 shows the simulated inductances and quality factors of the active inductor under different biasing conditions and power consumptions. The aspect ratio of M1 , M2 , M3 , and M4 is (62 ␮m/0.18 ␮m), (49.6 ␮m/0.18 ␮m), (32 ␮m/0.18 ␮m), and (50.4 ␮m/0.18 ␮m), respectively. The self-resonant frequencies of the proposed inductor are all higher than 8 GHz, and the tunable inductance ranges from 0.89 nH (at 10.4 GHz) to 2.55 nH (at 5.8 GHz) as shown in Fig. 3(a). The power consumption of each tunable curve is also marked. Typically, the active inductor consumes higher power at higher frequencies. Moreover, the peak-Q factors tuned by Vd and Vt are 39 at least which are acceptable for the low-loss WPD design. The proposed WPD operates at 8 GHz, and therefore the corresponding Cs of 0.28 pF and Lp of 1.4 nH are required. A further tunable design can be achieved by adjusting the bias conditions. 3. Implementation, measurement, and discussion The circuit is fabricated in a standard mixed-signal/RF bulk 0.18␮m CMOS process. Typically, 1.8 V-NMOS transistors of the process feature a threshold voltage (Vt ) of 0.42 V, gate oxide thickness (tox ) of 4.08 nm, and transit frequency (ft ) of 48 GHz. The process also provides poly silicon resistors, metal-oxide-metal (MOM) capacitors with a 1.1-fF/␮m2 capacitance density, and six metal layers (M1 to M6). The MOM capacitors are implemented from M1 to M5 layers for achieving high capacitance density. Fig. 4(a) shows the chip photo of the fabricated Wilkinson power divider. The chip area including all test pads is 0.64 mm × 0.61 mm, where the active area occupies only 0.25 mm × 0.15 mm. The upper and lower pads provide dc supply for the circuit, and the power lines are realized from the top metal layer (M6) to the M5 layer through via to avoid

S. Wang, R.-X. Wang / Int. J. Electron. Commun. (AEÜ) 66 (2012) 655–658

a

8 6

5.1mW

4 2 0 Vd=1.5V Vt=1.4V Vd=1.7V Vt=1.6V Vd=1.8V Vt=2.0V

-2 -4 2

4

6

Vd=1.5V Vt=1.4V Vd=1.7V Vt=1.6V Vd=1.8V Vt=2.0V

100

2.8mW

Quality Factor

Inductance (nH)

b 120

10mW

8

657

10mW

80 60

5.1mW

40 2.8mW 20 0

10

12

14

Frequency (GHz)

2

4

6

8

10

12

14

Frequency (GHz)

Fig. 3. (a) Simulated inductances and (b) quality factors of the active inductor under different biasing conditions.

unnecessary voltage drop. The left-hand and right-hand pads are the input and output ports as marked in the chip photo. Three-port S-parameter experiments of the lumped circuit were characterized by on-wafer measurements. The undesired parasitic of pads and interconnections were removed by a de-embedding procedure. Good agreements between simulated and measured results are also observed to validate the design methodology. Fig. 4(b) shows the simulated and measured results of the lumped power divider operating at a center frequency of 8 GHz. The circuit consumes 10.2 mW, and the isolation between output ports is about 22.6 dB. Moreover, the insertion loss and return loss is

0.67 dB and 27 dB at the frequency of interest. The tuning range of the circuit is between 5.8 GHz and 10.4 GHz, demonstrating a 4.6 GHz bandwidth. The measured insertion loss at 5.8 GHz and 10.4 GHz is 1.1 dB and 0.65 dB, respectively. The tunable divider operating at 5.8 GHz and 10.4 GHz consumes 5.6 mW and 20 mW, respectively. Typically, higher operating frequencies of the circuit demonstrate higher power consumption as shown in Fig. 4(c). The input P1 dB of the tunable circuit is also investigated. Typically, the circuit at higher frequencies features better input P1 dB due to the high supply voltage providing large voltage swings at transistors as shown in Fig. 4(d). Table 2 summarizes the comparisons of the two

Fig. 4. (a) Chip photo. (b) Simulated and measured results of the circuit operating at 8 GHz. (c) Measured |S21 | of the tunable circuit. (d) Input P1 dB versus operating frequency of the tunable circuit.

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S. Wang, R.-X. Wang / Int. J. Electron. Commun. (AEÜ) 66 (2012) 655–658

Table 2 Comparisons with the two lumped Wilkinson power dividers. Parameter

[12]

This work

Process

0.18 ␮m CMOS

0.18 ␮m CMOS

Topology of active inductor

Conventional (M1 and M2 )

f0 (GHz) Insertion loss (dB) Return loss (dB) Isolation (dB) Input P1 dB (dBm) PDC (mW) Overall chip area (mm2 )

4.0 0.68 26 19.7 N.A. 15.6

4.5 0.16 30.1 27 −10 16.7 0.385

CMOS Wilkinson power dividers using active inductors. It reveals that the proposed design demonstrate high operating frequencies, wide tuning range, and low power consumption. 4. Conclusion In this paper, a compact and tunable Wilkinson power divider using active inductors in a standard 0.18-␮m CMOS process is presented. Due to the lumped design concept, a significant area reduction is achieved, especially for applications at microwave frequencies. Compared to a conventional active inductor topology, the proposed active inductor features higher inductance tuning range, higher self-resonant frequency, and lower power consumption by introducing two additional transistors (M3 and M4 ). With the high-Q factors and tunable inductances provided by the active inductors, the WPD exhibits enhanced performance in terms of insertion loss, return loss, and port isolation while maintaining a wide frequency tuning range. Good agreement between measured and simulated results and good electrical characteristics of the WPD demonstrate the feasibility of lumped designs using the active inductor beyond 10 GHz. It is believed that the active inductor is suitable for further practical applications such as filters and phase shifters. Acknowledgements The authors would like to thank the Chip Implementation Center (CIC) and National Science Council (NSC) of Taiwan for the chip implementation and financial supports. References [1] Wu Y, Liu Y, Li S, Yu C, Liu X. closed-form design method of an N-way dualband Wilkinson hybrid power divider. Progress in Electromagnetics Research 2010;101:97–114. [2] Wang D, Zhang H, Xu T, Wang H, Zhang G. Design and optimization of equal split broadband microstrip Wilkinson power divider using enhanced particle swarm optimization algorithm. Progress in Electromagnetics Research 2011;118:321–34. [3] Wu Y, Liu Y, Xue Q. An analytical approach for a novel coupled-line dualband Wilkinson power divider. IEEE Transactions on Microwave Theory and Techniques 2011;59(2):286–94. [4] Oraizi H, Sharifi A-R. Design and optimization of broadband asymmetrical multisection Wilkinson power divider. IEEE Transactions on Microwave Theory and Techniques 2006;54(5):2220–31. [5] Wu Y, Liu Y, Li S. Dual-band modified Wilkinson power divider without transmission line stubs and reactive components. Progress in Electromagnetics Research 2009;96:9–20.

Proposed (M1 , M2 , M3 , M4 ) 5.0 0.7 22.6 23 N.A. 19.4

5.8 1.1 21 15 −24.4 5.6

8.0 0.67 27 22.6 −18.2 10.2 0.39

10.4 0.65 29 17.4 −14.8 20

[6] Wu Y, Liu Y, Li S. An unequal dual-frequency Wilkinson power divider with optional isolation structure. Progress in Electromagnetics Research 2009;91:393–411. [7] Li J-C, Nan J-C, Shan X-Y, Yan Q-F. A novel modified dual-frequency Wilkinson power divider with open stubs and optional/isolation. Journal of Electromagnetic Waves and Applications 2010;24(16):2223–35. [8] Hassan H, Anis M, Elmasry M. Impact of technology scaling on RF CMOS. In: International SOC Conference Digest, September. 2004. p. 97–101. [9] Doan C-H, Emami S, Niknejad A-M, Brodersen R-W. Millimeter-wave CMOS design. IEEE Journal of Solid-State Circuits 2005;40(1):144–55. [10] Sun S, Shi J, Zhu L, Rustagi S-C, Mouthaan K. Millimeter-wave bandpass filters by standard 0.18-␮m CMOS technology. IEEE Electron Device Letter 2007;28(3):220–2. [11] Shie C-I, Cheng J-C, Chou S-C, Chiang Y-C. Design of CMOS quadrature VCO using on-chip trans-directional couplers. Progress in Electromagnetics Research 2010;106:91–106. [12] Lu L-H, Liao Y-T, Wu CR. A miniaturized Wilkinson power divider with CMOS active inductors. IEEE Microwave Wireless Component Letters 2005;15(4):775–7. [13] Hsieh H-H, Liao Y-T, Lu L-H. A compact quadrature hybrid MMIC using CMOS active inductors. Transactions on Microwave Theory and Techniques 2007;55(4):607–15. [14] Lu L-H, Liao Y-T. A 4-GHz phase shifter MMIC in 0.18-␮m CMOS. IEEE Microwave Wireless Component Letters 2005;10:694–6. [15] Saaverdra C-E, Zheng Y. Frequency response comparison of two common active inductors. Progress in Electromagnetics Research Letters 2010;13:113–9. [16] Wang Y-T, Abidi A. CMOS active filter design at very high frequency. IEEE Journal of Solid-State Circuits 1990;25(6):1562–74. [17] Thanachayanont A, Payne A. VHF CMOS integrated active inductor. IET Electronics Letters 1996;32(5):999–1000. Sen Wang received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2004, the M.S. degree and Ph.D. degree in graduate institute of communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2006 and 2009, respectively. He joined the Faculty of the Department of Electronic Engineering, National Taipei University of Technology, Taipei, Taiwan, as an Assistant Professor in February 2010. His research interests include the design of microwave/millimeter-wave passive circuits, CMOS RF integrated circuits, and radar system engineering.

Rui-Xian Wang was born in Taichung, Taiwan, R.O.C., in 1987. He received the B.S. degree in electrical engineering from the National United University, Miaoli, Taiwan, R.O.C., in 2010. He is currently working toward the M.S. degree in Graduate Institute of Computer and Communication engineering at the National Taipei University of Technology, Taipei, Taiwan, R.O.C. His research interests include CMOS RF integrated circuits.