Analytical model of gate leakage current through bilayer oxide stack in advanced MOSFET

Superlattices and Microstructures 80 (2015) 20–31

Contents lists available at ScienceDirect

Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices

Analytical model of gate leakage current through bilayer oxide stack in advanced MOSFET Rathin Basak a,⇑, Biswajit Maiti b, Abhijit Mallik c a b c

Department of Physics, Kalyani Govt. Engineering College, Kalyani, Nadia, West Bengal, India Department of Physics, Darjeeling Govt. College, Darjeeling, West Bengal, India Department of Electronic Science, University of Calcutta, West Bengal, India

a r t i c l e

i n f o

Article history: Received 12 December 2014 Accepted 17 December 2014 Available online 30 December 2014 Keywords: Density of states Fowler–Nordheim tunneling MOSFET Quantum tunneling Quantum well Tunneling probability WKB approximation

a b s t r a c t A compact model for gate tunneling current in advanced nano-scale MOSFET has been developed on the basis of both direct and Fowler–Nordheim tunneling through dual layer Silicon oxide–Hafnium oxide stack used as gate dielectric. Calculation includes the effect of different subbands of the semiconductor conduction band those arise due to quantum confinement of charge carriers in the oxide–substrate interface. Effect of charge trapping in the bulk of the oxides and at the localized energy levels at different interfaces of the oxides has also been taken into consideration. Tunneling probability as a function of gate bias has been determined considering Wentzel–Kramers–Brillouin (WKB) approximation to account for varying potential profile. Probability amplitude of an electron for tunneling has been calculated by solving Schrodinger equations at different regions in the effective mass approximation model of class I crystal interface. Tunneling current as a function of effective oxide thickness and gate bias estimated in this model shows substantial reduction in gate leakage current if HfO2 as high-k dielectric is used along with 1 nm thick SiO2 with almost negligible change in threshold voltage. Ó 2015 Elsevier Ltd. All rights reserved.

1. Introduction PRESENT generation MOSFET technology is using 45 nm-node or below that. As a result of this aggressive decrease in dimension, gate leakage current is increased to a large extent and also the reli⇑ Corresponding author. E-mail address: [email protected] (R. Basak). http://dx.doi.org/10.1016/j.spmi.2014.12.018 0749-6036/Ó 2015 Elsevier Ltd. All rights reserved.

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

21

ability and control over the device is being affected. When SiO2 thickness is reduced below 2 nm, in traditional MOS device, the leakage current density may go beyond 10A/cm2 [1]. Beside the adverse effect of high direct tunneling current, there is the problem of Boron diffusion into and through oxide layers from poly-Si gate electrode in p-channel devices even at low electric field [2]. This severely degrades the device performance over time. So people think of using different high-k dielectric materials like La2O3, ZrO2, HfO2 etc. instead of SiO2 alone. Among the rare earth oxides HfO2 is the most promising high-k dielectric material because of its good thermal stability with Si. Introduction of the rare earth oxides help in reducing gate-leakage current to some extent but in the turn device reliability is affected from defect states inherent to these materials. These defect states act as trap centers which are mainly accumulated near the interfacial layers, as a result the mobility of electrons along the MOS channel is affected [3]. Also mechanical strain generated due to lattice mismatch between Si substrate and rare earth oxide over layer causes the trap centers to be distributed along the interface. To circumvent this problem stacked films of oxides/nitrides as high-k dielectrics on thin SiO2 layer have gain much attention in recent years [4–8]. It is very important to maintain the quality of the interfacial layers in high-k gate dielectric stacks those often act as critical factors in affecting the transistor performance and reliability [9]. Ultra thin gate oxide and high substrate doping concentration in these MOSFETs create very high electric field at the oxide–semiconductor interface that causes severe band bending at the interface. The width of electron accumulation/depletion layer near the interface is too narrow to cause energy quantization and the resulting 2D electron gas tunnels through thin oxide layers constituting major part of gate tunneling current. The quantum tunneling in MOS devices has often been analyzed through direct tunneling [10–12], Fowler–Nordheim tunneling [13,14], trap-assisted tunneling [15–17]. In most of the cases, semi-empirical model involving solution of Schrodinger–Poisson equation has been used [18,19] to determine the current–voltage characteristics and the tunneling characteristics in MOS devices. Wu et al. [20] have introduced a modified semi-empirical relation based on WKB approximation and quantum mechanical simulation based on three-subband model to study the gate voltage and surface potential dependence of gate leakage current density for different high-k dielectrics. They have showed that direct tunneling is the dominant mechanism at low voltages. However, in their calculation of electron energy level, well known triangular potential well approximation has been used. Later, Mondal et al. [21] has modified the energy expression by considering electric field penetration inside the bulk of the substrate. The result showed a 25% decrease in the ground state energy of electron in the potential well at the interface. In their article they have truly taken the approach of calculating wave function of inversion layer electrons and found non-zero value at the interface. This is indicative of tunneling of electrons into the oxide layer. This approach is quite different from most of the others found in literatures [22] but we find it to be physically more correct in devising a fully analytical model for gate tunneling current. Over the last decade substantial amount of works have been dedicated to finding an effective analytical, rather semi-empirical model those represent physical basis for the performance of multi-oxide nano-MOS device. But a simple fully analytical model that encompasses all the controlling parameters of these devices is still to be developed. In this article we have tried to analyze the effectiveness of SiO2-HfO2 stack as a viable alternative and have tried to determine the effective electron density at the semiconductor oxide interface more accurately by taking into account the variation of inversion layer thickness with gate bias and in turn, its effect on the subband energy levels. The article is organized in the following way: In section-II, Schrodinger equation is solved rigorously at different regions considering exact potential profile from gate to substrate. The effect of gate biasing, band offset, substrate doping concentration, quantum confinement effects at the inversion layer and trap states distribution at the interfaces and in oxides have been taken into account to determine the exact potential profile. Then an analytical model for gate tunneling current is derived considering corrected electron flux density appearing at the oxide interface. Regime of different tunneling mechanisms depending on gate bias has been investigated. In this way a fully analytical model with no fitting parameter has been formulated in section-II. In section-III, gate-tunneling current as a function of gate bias and effective oxide thickness have been demonstrated. Finally we make our conclusion in sectionIV.

22

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

2. Model description and formulation of gate tunneling current Detail analysis of simple linear MOS configuration considering all the effects of gate biasing, band offset, substrate doping concentration, quantum confinement effects at the inversion layer and trap states distribution at the interfaces and in the bulk of oxides is sufficient to throw light into the mechanism of tunneling through gate dielectric. Therefore, we have tried to analyze a simple double oxide linear MOS structure having 1 nm thick SiO2 and 1–4 nm thick HfO2 placed between lightly doped p-Si substrate and metal gate. The band diagram is shown in shown in Fig. 1. For simplicity the effect of non-parabolicity of conduction bands has not been considered so that we can assume single effective mass for electrons for a particular material and as the condition of equilibrium, their Fermi-levels are considered aligned so that there is direct band to band tunneling of electrons from the inversion layer to the conduction band of gate-metal. The effect of gate bias voltage on the band-to-band tunneling is studied and compared with the data available in the literature. At equilibrium condition, to account for the alignment of Fermi level across the MOS structure, depletion of holes takes place at the p-Si–SiO2 interface creating a depletion layer, while depletion of electron will occur at the metal–HfO2 interface. Since the density of free electrons is too high in metal, band bending is more profound in Si compared to metal. As a result, change of band offset in metal–HfO2 is negligible compared to that in Si–SiO2. With positive applied gate bias, VGB this band offset increases rapidly to form an inversion layer of electrons within a narrow sheet of width, Dd near the interface. At the onset of strong inversion the band offset remains almost constant as the density of electrons becomes too high at the inversion layer. The potential balance across the MOS structure demands that [23]

V GB ¼ V FB þ V 1 þ V 2 þ /S

ð1Þ

where VGB is the gate bias voltage in reference to the substrate and VFB = /MS is the flat-band voltage indicating the difference in Fermi levels between gate-metal and p-Si substrate. V1 and V2 are the voltage drops in HfO2 and SiO2 respectively. /S is the surface potential at the bulk of the substrate and in the regime of strong inversion it approaches a constant value, /S ¼ 2/F þ 6/T , where /F ¼ /t lnðN A =ni Þ is the quasi-Fermi level of the p-Si with respect to the intrinsic Fermi level of the semiconductor and /t = KT/q is the voltage equivalent of temperature. NA is the substrate doping concentration and ni is the intrinsic carrier concentration in the bulk of the semiconductor. Then the respective potential drops across the oxides can be expressed as

ðd2 =e1 Þ ðV GB  V FB  /S Þ ðd1 =e2 þ d2 =e1 Þ ðd1 =e2 Þ V2 ¼ ðV GB  V FB  /S Þ ðd1 =e2 þ d2 =e1 Þ

V1 ¼

ð2Þ

Fig. 1. Band diagram of dual oxide planar MOSFET structure with p-Si substrate and metal gate. 1 nm thick SiO2 and 1–4 nm thick HfO2 dual layer acts as dielectric. Whole structure is divided into four regions for the purpose of analysis. The band off-sets are taken with respect to the conduction band edge at the Si–SiO2 interface.

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

23

and the corresponding electric fields are

V1 e2 ¼ ðV GB  V FB  /S Þ d2 d1 e1 þ d2 e2 V2 e1 ¼ ðV GB  V FB  /S Þ E2 ¼ d1 d1 e1 þ d2 e2

E1 ¼

ð3Þ

In the inversion region of width, Dd electrons act as quantum confined 2D electron gas [24] the energy levels of which are calculated by solving Schrodinger equation with triangular potential well approximation. Therefore, near the interface the quantized energy of the ith subband of Si conduction band is expressed as [25]

Ei ¼

!1=3    2=3 h2 3 3 iþ p ðqnS Þ2=3 2 4 2mSi

ð4Þ

where i indicates the subband index and mSi is the effective mass of the conduction band electrons. The lowest subband, considered as the ground state is obtained from the above expression by simply putting j = 0

h2 2mSi

E0 ¼

!1=3  2=3 9p qnS 8

ð5Þ

in which nS is ffi the effective electric field in Si and is given by nS ¼ qðN ST þ N D Þ=eSi , where pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi N D ¼ 2qN A eSi /S is the concentration of depletion layer charge. NA is the concentration of acceptor doping in the Si-substrate which is assumed to be fully ionized at room temperature. NST = NS + NSS is the concentration of sheet charges that includes concentration of inversion layer charge, NS and concentration of interfacial trap charges, NSS. The effect of electric field penetration in the bulk of the semiconductor has been incorporated in our study in terms of change in inversion layer thickness leading to increase in the concentration of inversion layer charge, NS. The variation of the concentration of inversion layer charge with applied gate voltage is obtained by applying Gauss’s theorem of electric field

NS ¼ C OX

ðV GB  /S  V FB Þ  ND q

ð6Þ

where C OX ¼ e1 e2 =ðd1 e2 þ d2 e1 Þ is the effective capacitance of the linear double oxide MOS structure and d1, d2 and e1, e2 are the respective thicknesses and dielectric constants of SiO2 and HfO2. VFB is the flat band voltage and has been modified as VFB = /MS  (QS/COX), where /MS is metal–semiconductor work function difference and QS is the concentration of total sheet charges including the concentration of trap charges coming from the defect states distribution at the interface and is given by

Q S ¼ q½NS FðEi  EFS Þ þ NSS FðESS  EFn Þ

ð7Þ

where NSS is the concentration of defect states at the interface, EFn is the corresponding Fermi level and is approximately equal to EFS, the equilibrium Fermi level at Si. The first term in the bracket indicates Fermi distribution of inversion layer charges and the second term indicates that of the interfacial trap charges which is given by FðESS  EFn Þ ¼ 1=½1 þ expððESS  EFn Þ=K B TÞ. In this expression energy of the defect states, ESS = EC  DEt is assumed little below the conduction band edge of the semiconductor. The effect of volume distribution of defect states in the bulk of oxides is accounted for by the tunneling life time of the electrons through the oxides. It causes decrease of tunneling probability, PT by a factor, fi termed as impact frequency which is given by

f i ¼ R Dd  0

qn0S ffi ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffi   2mSi = hki ðxÞ dx 2 2mSi Ei 1

ð8Þ

Factor, ½ in the above expression comes from the averaging over the thickness of the inversion layer. Thus the effective tunneling probability as calculated by WBK approximation will be PTeff = fiPT. Here n0S is the modified electric field in Si in presence of volume distribution of trap states in the bulk of the

24

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

oxides. If uniform distribution is assumed in HfO2 and SiO2 is assumed defect free then n0S ¼ nS þ qOX d1 =e1 where qOX is the volume density of trap states in the bulk of HfO2. Then in presence of the volume distribution of defect states in HfO2 the effective electric field nS in (4) and (5) has to be replaced by n0S . At the strong inversion regime, the density of states (DOS) of 2D electron gas behave as step functions [26] and with the consideration of conduction band of Si as a single parabolic band the DOS for ith subband will be

Di ðEi Þ ¼

g i mdi

ð9Þ

ph2

where gi is the degeneracy factor and mdi is the density of states effective mass of the electrons at the ith subband. Then the electron concentration per unit area at the inversion layer will be

NS ¼

X X F j ðEi ÞDij ðEi Þ ¼ ij

ij

Dij ðEi Þ 1 þ exp ½ðEi  EFS Þ=K B T 

ð10Þ

Here all the energies are measured with respect to the conduction band edge at the interface. EFS is the Fermi level in Si and is aligned accordingly in the equilibrium condition. In the strong inversion regime and at room temperature due to severe band bending /S is increased to such an extent that the conduction band edge may go below the Fermi level and one must consider the degenerate Fermi distribution. At this condition in the asymptotic limit when EFS ii0 following Sommerfeld expansion of the Fermi inteðjþ1Þ gral of order j the approximate solution for DOS, DðEi Þ ¼ Eji =Cðj þ 1Þ would be F j ðEFS Þ ! EFS =Cðj þ 2Þ. In the case of 2D electron gas DOS, Di(Ei) for a particular subband is constant, i.e., j = 0 and then the solution is the zeroth order Fermi function F 0 ðEFS Þ ! EFS  K B T ln½1 þ expðEFS =K B TÞ. Here EFS is measured from conduction band edge which is taken as the reference of energy. Therefore, one may write

NS ¼

X K B TDi ðEi Þ ln½1 þ expðEFS =K B TÞ

ð11Þ

i

Combining (11) with (6) proper expression of inversion layer charge density can be evaluated. In the strong inversion regime since, E0, the ground state energy of the lowest subband of the conduction band, is pretty close to the equilibrium Fermi level, most of the electrons will be at the ground state at room temperature. So, contribution to tunneling current is effectively comes only from a few subbands above the ground state, beside the maximum contribution coming from the ground state. Therefore, one can write

NS ¼

X g mdi K B T ln ½1 þ expðEFS =K B TÞ i 2 ph i

ð12Þ

and corresponding to ground state energy it will be

NS ¼

X g md0 K B T ln ½1 þ expðEFS =K B TÞ 0 2 ph i

As E0 can easily be determined using (3) it is convenient to shift the reference level of energy from the conduction band edge of Si at the interface to E0 in determining EFS. Then substituting E0FS ¼ EFS  E0 in place of EFS in (8) the inversion layer electron concentration per unit area will be



 g 0 md0 NS ¼ K B T ln ð1 þ expðE0FS =K B TÞ  expðE0 =K B TÞ ph2

ð13Þ

where the ground state energy E0 is

E0 ¼

h2 2msi

!1=3 

2=3 9p C ox ðV GB  V FB  /S Þ q 8 eSi

ð14Þ

Contributions of other subbands may well be calculated by introducing the energy values E1, E2 etc. along with their degeneracy factor and electron effective mass in (12) and the subsequent modification of (13).

25

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

Here the effect of VGB is to modify the electric field throughout the MOS structure in such a way as to account for the accumulation of electrons in the inversion layer and the overall effect is to increase the energy of the accumulated electrons. Therefore at the regime of strong inversion, when /S ¼ 2/F þ 6/T , NS will increase in higher order polynomial with VGB as is evident from the above expression. But, before the onset of strong inversion an approximate linear relation between NS and VGB may be assumed. At that region, sheet charge density, NS can be evaluated as a function of applied gate voltage with the starting value of NS as

NS ¼ C OX

ðV GB  V T Þ q

ð15Þ

and after a few iterations the final value of NS and /S is arrived at. Here, V T ¼ 2/F þ V FB  ðqN D =C OX Þ is the threshold of strong inversion. Four to five iterations are found sufficient to get nearly exact value to match with the value obtained from (9) at the threshold of strong inversion. It must be clear that not all of the accumulated electrons, NS will take part equally in the tunneling process through gate oxide. The effective amount of charge carriers that will take part in the tunneling mechanism can be obtained through multiplying NS by the probability density of electrons jwIII ð0Þj2 at the Si–SiO2 interface of the MOS structure. Therefore the effective interfacial charge density responsible for tunneling will be

nj0 ¼ NS jwIII ð0Þj2

ð16Þ 2

In order to determine the probability density of electrons, jwIII ð0Þj the entire MOS structure is divided into four regions starting from gate-metal as shown in Fig. 1. Exact solution of the Schrodinger equations for electrons corresponding to different regions of the double oxide linear MOS structure have been determined considering ballistic tunneling of electrons from the inversion region to the gatemetal, so that there is no scattering or energy loss of the electrons inside the oxide regions. This will be a fairly good approximation if the defect or trap-charge density distribution in the body of the oxides is small. Therefore, electrons are supposed to tunnel with the same velocity, assumed to be the electron Fermi velocity in the metal. Further, as it is assumed that electrons are being transferred from the inversion region to the conduction band of the metal through the conduction bands of the oxides in between, the solutions of Schrodinger equations at different regions are obtained with their conduction band energy as the potential height which is modulated as a function of applied gate bias. With this assumption of direct band to band tunneling electrons should have same kinetic energy, but different potentials in different regions lead to different effective masses of electrons mI, mII, mIII, mIV corresponding to these regions. Taking Ec1 , Ec2 as the conduction band offsets of HfO2 and SiO2 with respect to the conduction band edge of the substrate at the Si–SiO2 interface and /S as the surface potential, i.e., the conduction band energy in the bulk of the substrate the solutions of the Schrodinger equations yield the probability density of electrons at the gate-metal interface as

   

1 1 2ad1 a 2 2ðabÞd1 1 a2 1  2 e2ad1  d1 e 1  e2ad2 þ 1þ e  ð1  e2bd1 Þ þ 2a 8b 2 b b  2    2  1 a 1b a ðabÞd1 a ðaþbÞd1 2 e e  1  ð1  e2bd1 Þe2ðaþbÞd1 þ 1 þ  1  8b 8 c2 b b b ( )   2   sinð2c  DdÞ 1 b a 2ðabÞd1 a 2 2ðaþbÞd1  1   Dd  1þ e e 2c 8 c2 b b     1 a ðabÞd1 a ðaþbÞd1 2 e e 1þ þ 1  ðcos ð2c  DdÞ  1Þ þ 8 b b       sinð2c  DdÞ 1 b a ðabÞd1 b a ðaþbÞd1 þ e e  Dd þ þ  sin ðc  DdÞ   2c 8d c c c c     #1=2 

A¼

 sin ðc  DdÞ þ 1 þ

a b

eðabÞd1  cosðc  DdÞþ 1 

a b

2

eðaþbÞd1  cosðc  DdÞ

ð17Þ

26

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31 1=2

Here,

a ¼ f2mI ðEc1  E0 Þ=h2 g 1=2 c ¼ ð2mIII E0 =h2 Þ

2 1=2

b ¼ f2mII ðEc2  E0 Þ= h g

2 1=2

d ¼ f2mIII ðq/S  E0 Þ= h g

are the parameters related to the electron energies at different regions. The effective mass approximation (EMA), boundary conditions of continuity of wave functions and their first derivatives at the interfaces we assume class I type crystal interface where BenDaniel–Duke boundary condition for slowly varying envelop function to Bloch function is employed. This is applied to all the hetero interfaces since here, the MOS structure involves wide band gap semiconductors with low conduction band effective mass. Evaluation of these boundary conditions lead to the determination of the value of inversion layer thickness ‘‘Dd’’

         a b a b a c b 2bd1 1 þ e2bd1 þ 1  1 1þ tan1 1þ  e d d c b b b d c     a c b þ þ 1 b d c

Dd ¼

1

ð18Þ

Now, the amplitude of the wave function at the Si–SiO2 interface is

jwIII ð0Þj ¼

A 2

     a ðabÞd1 a ðaþbÞd1 e e þ 1 1þ b b

ð19Þ

This accounts for the effectiveness of the inversion layer electrons to be tunneled through the gateoxide. As it is multiplied by the tunneling probability it will give the amount of inversion layer charge that will appear at the gate. Tunneling probability is calculated by using modified WKB approximation in the varying potential profile along the diffusion path through the oxide layers. The interfacial electrons tunnel through the oxide layers and is assumed to be direct band-to-band tunneling. It is further assumed that no charge is accumulated or distributed in the body of the oxide regions. These assumptions simplify the process of calculation of tunneling probability. In this process the rectangular barrier height is tailored to obtain the actual Fowler–Nordheim triangular barrier height, EcOX ðxÞ because of the different work function of the materials and due to the effect of band bending caused by the applied gate voltage. Wave vectors, KOX are deduced from the parabolic energy band dispersion relation assuming spherical constant energy surface at the inversion region

K OX

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  ffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  ffi 2mOX 2mOX c ¼ ½U OX  E0  ¼ EOX ðxÞ h2 h2

ð20Þ

Electron transmission probability is then calculated by using WKB approximation along the resulting triangular barrier by

 Z PT ¼ exp 2

tOX

 K OX dx

ð21Þ

0

with the barrier height, EcOX ðxÞ faced by the tunneling electrons at different regions being as follows At position 1 (x = 0): EcOX ðxÞ ¼ Ec2 þ q/S  Eo . At region between 1 and 2: EcOX ðxÞ ¼ Ec2 þ q/S  Eo  qE2 x. At position 2 (x = d1): EcOX ðxÞ ¼ Ec2 þ q/S  Eo  qE2 d1 . At region between 2 and 3: EcOX ðxÞ ¼ Ec1 þ q/S  Eo  qE1 ðx  d1 Þ. At position 3 (x = d1 + d2): EcOX ðxÞ ¼ Ec2 þ q/S  Eo  qE1 d2 . Depending on the amount of applied gate bias different tunneling processes may take place gradually and those can be represented as function of VGB in the following situations Case I: Direct tunneling both in SiO2 and HfO2 with x1 ¼ d1 ; x2 ¼ d1 þ d2 Case II: Direct tunneling in SiO2 and Fowler–Nordheim tunneling x1 ¼ d1 ; x2 ¼ d1 þ ðEc1 þ q/S  E0 Þ=ðqE1 Þ

in

HfO2

with

27

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

Case III: Direct tunneling in SiO2 with x1 = x2 = d1 Case IV: Fowler–Nordheim tunneling in SiO2 with x1 ¼ x2 ¼ ðEc2 þ q/S  E0 Þ=ðqE2 Þ The tunneling current density Jn through the linear MOS structure with SiO2–HfO2 dielectric stack can be calculated using the relation

J n ¼ qnjðd1 þd2 Þ v m

ð22Þ

where njðd1 þd2 Þ is the electron density at the metal–HfO2 interface and vm is taken as the Fermi velocity of the electrons in metal and is assumed to be same throughout the MOS structure as it has been considered that tunneling occurs through the dielectric stack via direct band to band tunneling. Ultimately we get the final expression for tunneling current density as

J n ¼ qN S jwIII ð0Þj2 v m P Teff

ð23Þ

3. Results and discussion It is important to note in the above expression of tunneling current density that the parameters, sheet charge density, NS, electron probability density, jwIII ð0Þj2 at the interface and the tunneling probability, PT all are functions of gate bias voltage, VGB. Therefore, with the material parameters taken from Table 1 below gate tunneling current as a function of VGB has been estimated and is presented graphically. The effect of increasing gate bias is to accumulate more and more electrons in the inversion region at the Si–SiO2 interface and it is narrowed down to merely a 2D sheet of electrons at the strong inversion regime. This is quite evident from Fig. 2 where it is observed that the inversion layer thickness decreases sharply within VGB = 0.4 V and then remains rather flat indicating the onset of strong inversion near VGB = 0.4 V.

Table 1 Material Parameters Used In Model. Material SiO2 HfO2

j [20]

Dielectric constant

Effective mass (mo) [20]

Band gap Eg(eV) [28]

Barrier height DEc (eV) w.r.t. Si conduction band [28]

3.9 20

0.4 0.22

9.0 5.7

3.0 1.5

Fig. 2. Variation of inversion layer thickness with gate bias for different EOT (1 nm SiO2 + HfO2 of varying thicknesses).

28

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

Fig. 3. Penetration of electron wave function into the substrate as a function of gate bias.

Fig. 4. Variation of inversion layer charge density with gate bias voltage for different EOT (1 nm SiO2 + HfO2 of varying thicknesses).

Also, the peak of electron probability density, jwIII ð0Þj2 , against the penetration depth inside the substrate as presented in Fig. 3, shifts toward the interface as gate voltage is increased. Sharpness of the plot and larger peak value at higher gate bias supports the previous logic too. As a result of this decrease of the thickness of inversion region, Dd the subband energy intervals of 2D electron gas will increase, i.e., the lowest subband, E0 comes down toward the Fermi level of Si and it, in turn, affects jwIII ð0Þj2 . This implies effective number of electrons to participate in the tunneling process will be higher for higher values of VGB. Unlike the article of Mondal et al. [21] since the effect of electric field is incorporated in the determination of inversion layer width, Dd no further correction is needed in determining E0 or other subband energy levels due to penetration of electric field in the bulk of the substrate and (13) is good enough in determining NS in the regime of strong inversion.

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

29

Fig. 5. Variation of gate tunneling current density as a function of gate bias for different EOT (1 nm SiO2 + HfO2 of varying thicknesses). The symbol D indicates the same for 1.39 nm SiO2 only. In the solid curves first part corresponds to Direct Tunneling and later part with higher slope corresponds to Fowler–Nordheim Tunneling.

Fig. 6. Variation of gate tunneling current density as a function of EOT for two different values of gate bias.

From the expression it is evident that with increasing VGB the inversion layer charge density, NS will increase in polynomial order and the variation is shown in Fig. 4 for different values of effective oxide thickness. One must be careful of the almost linear trail in the variation of NS before the onset of strong inversion. Besides the above factors tunneling current density is dependent on the quantum tunneling probability through the oxides. Due to variation of potential profile along the width of the linear MOS structure, we are analyzing here, the barrier height encountered by the tunneling electrons will not be rectangular. Tunneling of electrons through the varying potential barrier can be calculated by WKB method with due account of different regimes from direct tunneling to Fowler–Nordheim

30

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

tunneling in the two oxides by turn with increasing gate bias. The effect of interfacial charges on threshold of inversion is incorporated to account for smooth transition to the strong inversion regime at higher gate bias. In Fig. 5 gate tunneling current has been plotted as a function of gate bias with different thicknesses of HfO2, rather with effective oxide thickness as the other parameter. It is seen that if SiO2 of thickness equal to that of effective oxide thickness is solely used gate tunneling current is several orders of magnitude higher than when a combination of HfO2 along with 1 nm SiO2 is used. The result is in good agreement with experimental findings found in [27]. The variation of tunneling current density as a function of effective oxide thickness is shown in Fig. 6. It is worthy to be noticed that tunneling current is reduced by several orders of magnitude as HfO2 thickness is increased by merely 1 nm to 4 nm with no substantial change in the effective oxide thickness so that the threshold condition remains unaltered. It is found that at idle condition, i.e., when MOS is in off state still there is appreciable gate tunneling current when only SiO2 of same thickness as the effective oxide thickness chosen here has been used as the gate oxide. Instead, if HfO2 is used along with 1 nm SiO2 as gate oxide the off-state tunneling current and even the tunneling current near threshold of strong inversion get reduced appreciably. But there is not so much change in on-state current. Still it is much lower than the tunneling current when only SiO2 of same thickness as the effective oxide thickness of the oxide stack is used. Thus it can be concluded that keeping the thickness of SiO2 in the range of 1 nm and varying the thickness of HfO2 merely between 1 nm and 4 nm much reduction in gate tunneling current can be achieved with the effective oxide thickness suitable for maintaining threshold requirement. This is indicative of the fact that use of relatively large HfO2 layer along with ultra thin SiO2 may solve the problem of gate leakage current to an appreciable extent. 4. Conclusion A compact model for gate tunneling current in advanced nano-scale MOSFET is developed here based on the assumption of direct band-to-band tunneling of electrons from the inversion region to the gate metal. The effective charge density at the inversion region is obtained by solving Schrodinger equations corresponding to different regions with their conduction band energy as the potential height which is modulated by the applied gate bias. The tunneling probability is calculated using modified WKB approximation to account for the band bending caused by the applied gate bias. The rectangular barrier height has been tailored to obtain the actual Fowler–Nordheim triangular barrier height because of the difference in work function of different materials and the effect of band bending caused by the gate bias. Effective transmission probability determined from the consideration of trap state distribution in the bulk of oxide and at the interfaces has been duly incorporated in the estimation of tunneling current. Unlike most of the articles where semi-empirical Schrodinger–Poisson equation was used to evaluate the electron probability density, in this article effort has been taken to evaluate an exact analytical expression for the same with no fitting parameters by solving the Schrodinger equations with varying potentials at different regions. The use of high-k dielectric, HfO2 overlayer on SiO2 is found to decrease the tunneling current to an appreciable amount but with almost no change in the threshold condition. Thus the fully analytical formulation for gate tunneling current presented here is good enough for the estimation of the same and can effectively be used for the determination of other material parameters once gate tunneling current can be measured experimentally. References [1] D.A. Buchanan, Scaling the gate dielectric: materials, integration, and reliability, IBM J. Res. Develop. 43 (3) (May 1999) 245–264. [2] H. Wong, Y.C. Cheng, Electronic conduction mechanisms in thin oxynitride films, J. Appl. Phys. 70 (2) (July 1991) 1078– 1080. [3] C. Lee, H.J. Cho, C.S. Kang, S. Rhee, Y.H. Kim, R. Choi, C.Y. Kang, C. Choi, M. Abkar, High-k dielectrics and MOSFET characteristics, in: IEDM Tech. Dig., 2003, pp. 4.4.1–4.4.4. [4] Y. Ma, T. Yasuda, G. Lucovsky, Ultrathin device quality oxide-nitride-oxide heterostructure formed by remote plasma enhanced chemical vapor deposition, Appl. Phys. Lett. 64 (17) (April 1994) 2226–2228.

R. Basak et al. / Superlattices and Microstructures 80 (2015) 20–31

31

[5] T. Ito, T. Nakamura, H. Ishikawa, Advantages of thermal nitride and nitroxide gate films in VLSI process, IEEE Trans. Electron Devices 29 (4) (May 1982) 498–502. [6] K.K. Young, C. Hu, W.G. Oldham, Charge transport and trapping model for scaled nitride-oxide stacked films, Appl. Surf. Sci. 30 (Jan 1987) 171–179. [7] S. Mori, E. Sakagami, H. Araki, Y. Kaneeko, K. Narita, Y. Ohshima, N. Arai, K. Yoshikama, ONO inter-poly dielectric scaling for nonvolatile memory applications, IEEE Trans. Electron Devices 38 (2) (Feb 1991) 386–391. [8] G.W. Yoon, J. Kim, L.K. Han, J. Yan, D.L. Kwong, in: Proc. Symp. VLSI Tech. Dig., 1994, p. 155. [9] Dawei Heh, Chadwin D. Young, George A. Brown, P.Y. Hung, Alain Diebold, Eric M. Vogel, Joseph B. Bernstein, Gennadi Bersuker, Spatial distributions of trapping centres in HfO2/SiO2 gate stack, IEEE Trans. Electron Devices 54 (6) (2007) 338– 1345. [10] J. Coignus, R. Clerc, C. Leroux, G. Reimbold, G. Ghibaudo, F. Boulanger, Analytical modeling of tunneling current through SiO2–HfO2 stacks in metal oxide semiconductor structures, J. Vac. Sci. Technol. B 27 (1) (Jan 2009) 338–345. [11] Yee Chia Yeo, Qiang Lu, Wen Chin Lee, Tsu-Jae King, Chenming Hu, Xiewen Wang, Xin Guo, T.P. Ma, Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric, IEEE Electron Device Lett. 21 (11) (2000) 540– 542. [12] Leland Chang, Kevin J. Yang, Yee-Chia Yeo, Igor Polishchuk, Tsu-Jae King, Hu Chenming, Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs, IEEE Trans. Electron Devices 49 (12) (Dec. 2002) 2288–2295. [13] Andreas. Schenk, Gernot. Heiser, Modeling and simulation of tunneling through ultra-thin gate dielectrics, J. Appl. Phys. 81 (12) (June 1997) 7900–7908. [14] Wu-yun Quan, Dae M. Kim, Myoung Kwan Cho, Unified compact theory of tunneling gate current in metal–oxide– semiconductor structures: quantum and image force barrier lowering, J. Appl. Phys. 92 (7) (Oct. 2002) 3724–3729. [15] F. Jime´nez-Molinos, A. Palma, F. Ga´miz, J. Banqueri, J.A. Lopez-Villanueva, Physical model for trap-assisted inelastic tunneling in metal-oxidesemiconductor structures, J. Appl. Phys. 90 (7) (2001) 3396–3404. [16] M. Houssa, M. Tuominen, M. Naili, V. Afanas’ev, A. Stesmans, S. Haukka, M.M. Heyns, Trap-assisted tunneling in high permittivity gate dielectric stacks, J. Appl. Phys. 87 (12) (June 2000) 8615–8620. [17] F. Jime´nez-Molinos, F. Ga´miz, A. Palma, P. Cartujo, J.A. Lo´pez-Villanueva, Direct and trap-assisted elastic tunneling through ultrathin gate oxides, J. Appl. Phys. 91 (8) (2002) 5116–5124. [18] F. Crupi, C. Ciofi, A. Germano, G. Iannaccone, J.H. Stathis, S. Lombardo, On the role of interface states in low-voltage leakage currents of metal–oxide–semiconductor structures, Appl. Phys. Lett. 80 (24) (2002) 4597–4599. [19] W.C. Lee, C. Hu, Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling, IEEE Trans. Electron Devices 48 (7) (July 2001) 1366–1373. [20] Huixian Wu, Yijie (Sandy) Zhao, Marvin H. White, Quantum mechanical modeling of MOSFET gate leakage for high-k gate dielectrics, Solid-State Electron. 50 (2006) 1164–1169. [21] Imon Mondal, Aloke K. Dutta, An analytical gate tunneling current model for MOSFETs having ultrathin gate oxides, IEEE Trans. Electron Devices 55 (7) (July 2008) 1682–1692. [22] H.Y. Yang, H. Niimi, G. Lucovsky, Tunneling currents through ultrathin oxide/ nitride dual layer gate dielectrics for advanced microelectronic devices, J. Appl. Phys. 83 (4) (1998) 2327–2337. [23] Y. Tsividis, Operation and Modeling of the MOS Transistor, Second ed., McGraw-Hill, 1999. p. 57. [24] F. Stern, Self-consistent results for n-type Si inversion layers, Phys. Rev. B 5 (1972) 4891. [25] Hans Luth, Surfaces and Interfaces of Solids, Springer, Verlag, Berlin, Heidelberg, 1993. pp. 334, ch. 7. [26] Y. Ma, L. Liu, Z. Yu, Z. Li, Simplified method to investigate quantum mechanical effects in MOS structure inversion layer, IEEE Trans. Electron Devices 47 (6) (June 2000) 1303–1305. [27] A. Campera, G. Iannaccone, Modeling of tunneling currents in Hf-based gate stacks as a function of temperature and extraction of material parameters, IEEE Trans. Electron Devices 54 (1) (2007) 83–89. [28] M.L. Roy, E. Lheurette, O. Vanbesien, D. Lippens, Wave mechanical calculations of leakage current through stacked dielectrics for nanotransistor metal-oxide-semiconductor design, J. Appl. Phys. 93 (5) (Mar. 2003) 2966–2971.