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Worn-out oxide MOSFET characteristics: Role of gate current and device parameters on a current mirror
Microelectronics Reliability 47 (2007) 665–668 www.elsevier.com/locate/microrel
Worn-out oxide MOSFET characteristics: Role of gate current and device parameters on a current mirror J. Martı´n-Martı´nez b
a,*
, R. Rodrı´guez a, M. Nafrı´a a, X. Aymerich a, J.H. Stathis
a,b
a Department d’Enginyeria Electro`nica, Edifici Q, Universitat Auto`noma de Barcelona, 08193 Bellaterra, Spain IBM Semiconductor Research and Development Center (SRDC), Research Division, T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA
Available online 2 March 2007
Abstract In this work, the influence of gate oxide wear-out and breakdown (BD) on MOSFET output characteristics has been studied for short and long channel transistors. The experimental curves have been fitted to the BSIM4 model and have been introduced in a circuit simulator to study the effect of the oxide wear-out and BD in an analog circuit such as a current mirror. The results show important variations in the behaviour of the current mirror especially for the long channel transistor. Ó 2007 Elsevier Ltd. All rights reserved.
1. Introduction The continuous scaling of devices has implied the fabrication of MOSFETs whose channel dimensions and gate oxide thickness have decreased drastically in the last years [1]. However, some problems appear as a consequence of this scaling. In the case of the gate oxide, different mechanisms lead to the degradation and breakdown (BD) of the oxide, that is, the loss of its dielectric properties, limiting the oxide reliability. In this sense, it is necessary and of great interest nowadays to determine how the oxide degradation and BD affect the device and the circuit functionality. Previous works seem to indicate that the BD effect is overestimated and the devices and circuits can still work after an important level of oxide degradation [2,3], but the question is still not clear. To advance in this study, it is necessary the development of models for worn-out and broken down devices that can be included in circuit simulators, to predict the influence of the degradation and BD on circuit functionality. The parameters of the device model should include the effect of the oxide degradation to simulate a more realistic effect of this failure mechanism *
Corresponding author. Tel.: +34 93 581 35 24; fax: +34 93 581 26 00. E-mail address: [email protected] (J. Martı´n-Martı´nez).
0026-2714/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2007.01.035
on circuit performance. In this work, the characteristics of long and short channel transistors have been obtained for different levels of oxide degradation. These experimental transistor curves have been fitted to the BSIM4 model. The worn-out device parameters have been included in a circuit simulator, to study the effect of the oxide degradation in the functionality of an analog circuit such as a current mirror. 2. Experimental The samples used in this work were nMOSFETs of a 1.5 V bulk technology and an oxide thickness of 2.2 nm. Two different aspect ratios of W/L = 10 lm/10 lm (long channel transistors) and W/L = 10 lm/0.175 lm (short channel transistors) were analysed. To provoke the degradation of the oxide by means of a high electric field, a constant voltage stress (CVS) of 3.7 V was applied to the gate of the transistors with the other terminals grounded. The stress was stopped periodically to measure the device characteristics: the ID–VDS for several gate voltages, the ID–VGS with VDS = 100 mV and the IG–VG curves. This procedure was repeated from the fresh case until softbreakdown (SBD) took place. The values of IG, ID, IS and IB when a ramp voltage is applied to the gate with
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 665–668
666
the other terminals grounded indicate that for the analysed samples the BD event took place in the overlap region between gate and source (source BD).
14.0m
Δ ID / IDFRESH (%)
Fig. 1 shows the effect of different levels of oxide damage on the ID–VDS characteristics of short channel transistors. A decrease of the saturation current is observed as the degradation of the oxide increases. For these degradation levels, an increase in the threshold voltage and a decrease in the transconductance (Fig. 2) have been observed [4]. The same qualitative results were obtained for the long channel transistors (not shown here) although the variations of the transistor characteristics are more pronounced in this case. Figs. 3 and 4 show the evolution of the variations of the saturation currents and threshold voltages normalized to the fresh values, (IDSAT–IDSATFRESH)/IDSATFRESH and (VT–VTFRESH)/VTFRESH, respectively, as a function of the stress time for the different channel lengths. For the longer channel transistors, larger variations in the saturation current (Fig. 3) and the threshold voltage (Fig. 4) are
-2
SBD
-4
SBD
-6
X HBD -8
W / L = 10μm/0.175μm W / L = 10μm/10μm
-10 0
1000
2000
3000
4000
5000
6000
7000
Stress time (s)
Fig. 3. Relative variation of the saturation current as a function of the stress time for different transistor lengths.
8
SBD
7
X HBD 6 5
Δ VT / VT (%)
3. Results on transistors
0
SBD
4 3 2
Fresh Wear-out beforeSBD After SBD BSIM4
12.0m
Vgs = 1.5V
10.0m
W / L = 10μm/0.175μm W / L = 10μm/10μm
1 0
Vgs = 1.2V
0
1000
2000
3000
4000
5000
6000
7000
I D (A)
Time (s) 8.0m
Fig. 4. Relative variation of the threshold voltage as a function of the stress time for different transistor lengths.
Vgs = 0.9V 6.0m
4.0m
W / L = 10μm / 0.175μm
2.0m
0.0 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VD (V)
Fig. 1. ID–VDS curves measured for a fresh transistor and after different levels of oxide degradation. Symbols correspond to experimental data and continuous lines to the fitting of the data to the BSIM4 model.
3.0m
4.0m Fresh Wear-out before SBD After SBD BSIM4
2.5m
3.5m 3.0m
2.0m
1.5m
2.0m 1.5m
gm (V/A)
ID (A)
2.5m
1.0m 1.0m
observed. A possible explanation for these differences could be based on the geometry dependence of the dielectric degradation. The operation currents of the shorter transistors are larger, so that the effect of the oxide wear-out is not so visible as for the longer transistors. The BSIM4 model parameters have been extracted with Aurora software [5] for the fresh and worn-out transistors of both channel lengths. Good fittings of the experimental curves have been obtained in all the cases (continuous lines in Figs. 1 and 2 for the short channel transistors). It is important to note that the extracted BSIM4 transistor parameters take into account the dielectric degradation. On the other hand, the additional gate current due to oxide SBD has been described with the power law model [6]. 4. Current mirror
500.0µ 500.0µ
W / L = 10μm / 0.175μm 0.0 0.0
0.0 0.2
0.4
0.6
0.8
1.0
1.2
1.4
VG (V)
Fig. 2. ID–VG curves and transconductance measured for VDS = 0.1 V, for a fresh transistor and after different oxide damage. Symbols correspond to experimental data and continuous lines to the fitting of the data to the BSIM4 model.
To analyse the effects of the oxide wear-out in an analog circuit, a current mirror has been simulated using the extracted BSIM4 transistor parameters for several levels of oxide damage, for short and long channel transistors (Fig. 5). The current source in Fig. 5 models the BD current through the gate, when BD occurs in the overlap region between gate and source [3] and it is only included after
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 665–668 IIN
IOUT Wear-out in both transistors
IDSAT1
IOUT = IIN − IG1 − IG2
IDSAT2
1.5 V
T1
T2
.5 V
IG1 Wear-out ar-out in T2 I
OUT
I IN
=
I DSAT2
I DSAT1+ I G2
IG2
Fig. 5. Schematics of the current mirror used to analyse the effect of oxide degradation in the circuit performance. The current source is only included when the oxide breakdown has occurred.
the oxide BD (only one BD location is represented). Note that, in this circuit configuration, source BD corresponds to the worst case, since gate and drain are shortcircuited, so that the flow of BD gate current towards the drain will be negligible. For both geometries three different cases have been taken into account: (i) same wear-out of both transistors with gate current in both of them, (ii) wear-out on T2 transistor, without including the gate current in any of the two transistors and (iii) wear-out of T2, with gate current in both T1 and T2. For all cases, the figure of merit of the circuit performance, Iout/Iin, has been studied as a function of the stress time (Fig. 6). Equivalent conclusions would be drawn if the degradation was considered in T1. Fig. 6 shows that for case (i) the variation of the saturation currents as a consequence of the oxide degradation does not affect the circuit performance (Iout/Iin = 1) because both transistors have the same level of oxide damage and, therefore, the value of the saturation current is the same for both transistors during the whole stress. Only the BD current through the gate influences the circuit functionality. For short channel lengths (open triangles), before the
667
SBD, the symmetry of the drain currents is conserved and even after SBD the influence of the gate tunnel current is low (decrease of 3.3% in Iout/Iin). However, for the longer channel transistors (solid triangles), although before SBD the effect of the tunnel current is also low (but larger than for short channel devices), a strong decrease of 37% in the ratio Iout/Iin is observed after SBD. This result can be explained taking into account that, in this case, ISAT current of T1 and the gate currents for both transistors (see Fig. 6) contributes to the current Iin and that the saturation current is lower for long channel devices. Consequently, the contribution of the gate current to Iin is larger for long channel transistors so that the ratio Iout/Iin is lower. This effect is especially significant after the SBD where IGSBD = 0.01ISAT and Iout/Iin = 0.97 for short channel transistors and IGSBD = 0.35ISAT and Iout/Iin = 0.62 for the longer ones. For cases (ii) and (iii) oxide damage is considered to take place only in T2 (T1 remains fresh). Therefore, the saturation current is different for both transistors. For these cases, a small degradation of Iout/Iin is observed in short channel devices but there is no difference in considering or not the gate current. For longer devices, a small decrease in the figure of merit is observed when the tunnel current is considered before SBD. These observations can be explained taking into account that, before SBD, current through the gate due to oxide degradation is very low compared to the drain current operation values and consequently, the decrease of the Iout/Iin is due mainly to the reduction of the saturation current of the damaged transistor, which is larger for the longer transistors (Fig. 3). Therefore, before SBD, the variation of the model parameters as a consequence of oxide degradation has a more important effect on the functionality of the current mirror than the tunnel through the gate. When SBD takes place, there is a difference between (ii) and (iii), much more remarkable for the longer channel transistor (27% reduction of Iout/Iin) because in this case, the saturation currents are lower, so that BD gate current is relatively more important and has a larger influence in the ratio Iout/Iin. 5. Conclusions
1.00 0.95 0.90
IOUT / IIN
0.85 0.80
Pre SBD
SBD
Pre SBD SBD
0.75 0.70 White symbols - Short channel transistor Black symbols - long channel transistor
0.65 0.60
Wear-out in T2 with gate current Wear-out in T2 without gate current Wear-out in both transistors with gate current
0
1000
2000
3000
4000
5000
6000
7000
Time (s)
Fig. 6. Evolution of the Iout/Iin ratio of the current mirror shown in Fig. 6 for different levels of the degradation and transistor lengths as a function of the stress time. For short channel devices a lower influence of the tunnel current is observed.
The impact of wear-out and BD of the gate oxide of long and short channel nMOSFETS has been analysed. The wear-out of the oxide leads to a strong reduction in IDSAT and an increment of VT takes place. Longer channel transistors are more sensitive to the oxide degradation. BSIM4 model parameters of stressed long and short channel transistors have been extracted for different levels of oxide degradation. In addition to the BSIM4 parameters, a current source must be added to model the gate current when BD takes place. The influence on a current mirror performance of the gate current and the transistor parameter variation due to oxide degradation has been separately analysed. As expected, the wear-out effects are more important in longer devices due to the differences between the
668
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 665–668
operation currents and the gate tunnel current. If both transistors of the circuit are simultaneously degraded the circuit performance is not strongly affected. Only the BD of the devices provokes a decrease of the figure of merit, especially for long channel devices. In this case, the transistor parameters variation has little influence (because the symmetry of the circuit is conserved) and only the gate current influences the circuit performance, increasing its effect for higher levels of degradation and longer devices. However, when only one of the devices is damaged, the degradation of the circuit performance is more important, being again larger for long channel devices. In this case, the BD of the device provokes an important decrease of the figure of merit of the circuit.
Acknowledgements This work has been partially supported by the Spanish MCyT (TEC2004-00798/MIC) and the DURSI of the Generalitat de Catalunya (2005SGR-00061). References [1] International Technology Roadmap for Semiconductors. Semiconductor Industry Association. http://public.itrs.net. [2] Kaczer B et al. IEEE Trans Electron Dev 2002;49(3):500–6. [3] Rodrı´guez R et al. IEEE Electron Dev Lett 2003;24(2):114–6. [4] Cester A et al. In: IRPS proceedings, 2003. p. 189–95. [5] http://www.synopsys.com/products/mixedsignal/aurora_ds.html. [6] Miranda E et al. IEEE Electron Dev Lett 1999;20:265–7.
Worn-out oxide MOSFET characteristics: Role of gate current and device parameters on a current mirror J. Martı´n-Martı´nez b
a,*
, R. Rodrı´guez a, M. Nafrı´a a, X. Aymerich a, J.H. Stathis
a,b
a Department d’Enginyeria Electro`nica, Edifici Q, Universitat Auto`noma de Barcelona, 08193 Bellaterra, Spain IBM Semiconductor Research and Development Center (SRDC), Research Division, T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA
Available online 2 March 2007
Abstract In this work, the influence of gate oxide wear-out and breakdown (BD) on MOSFET output characteristics has been studied for short and long channel transistors. The experimental curves have been fitted to the BSIM4 model and have been introduced in a circuit simulator to study the effect of the oxide wear-out and BD in an analog circuit such as a current mirror. The results show important variations in the behaviour of the current mirror especially for the long channel transistor. Ó 2007 Elsevier Ltd. All rights reserved.
1. Introduction The continuous scaling of devices has implied the fabrication of MOSFETs whose channel dimensions and gate oxide thickness have decreased drastically in the last years [1]. However, some problems appear as a consequence of this scaling. In the case of the gate oxide, different mechanisms lead to the degradation and breakdown (BD) of the oxide, that is, the loss of its dielectric properties, limiting the oxide reliability. In this sense, it is necessary and of great interest nowadays to determine how the oxide degradation and BD affect the device and the circuit functionality. Previous works seem to indicate that the BD effect is overestimated and the devices and circuits can still work after an important level of oxide degradation [2,3], but the question is still not clear. To advance in this study, it is necessary the development of models for worn-out and broken down devices that can be included in circuit simulators, to predict the influence of the degradation and BD on circuit functionality. The parameters of the device model should include the effect of the oxide degradation to simulate a more realistic effect of this failure mechanism *
Corresponding author. Tel.: +34 93 581 35 24; fax: +34 93 581 26 00. E-mail address: [email protected] (J. Martı´n-Martı´nez).
0026-2714/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2007.01.035
on circuit performance. In this work, the characteristics of long and short channel transistors have been obtained for different levels of oxide degradation. These experimental transistor curves have been fitted to the BSIM4 model. The worn-out device parameters have been included in a circuit simulator, to study the effect of the oxide degradation in the functionality of an analog circuit such as a current mirror. 2. Experimental The samples used in this work were nMOSFETs of a 1.5 V bulk technology and an oxide thickness of 2.2 nm. Two different aspect ratios of W/L = 10 lm/10 lm (long channel transistors) and W/L = 10 lm/0.175 lm (short channel transistors) were analysed. To provoke the degradation of the oxide by means of a high electric field, a constant voltage stress (CVS) of 3.7 V was applied to the gate of the transistors with the other terminals grounded. The stress was stopped periodically to measure the device characteristics: the ID–VDS for several gate voltages, the ID–VGS with VDS = 100 mV and the IG–VG curves. This procedure was repeated from the fresh case until softbreakdown (SBD) took place. The values of IG, ID, IS and IB when a ramp voltage is applied to the gate with
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 665–668
666
the other terminals grounded indicate that for the analysed samples the BD event took place in the overlap region between gate and source (source BD).
14.0m
Δ ID / IDFRESH (%)
Fig. 1 shows the effect of different levels of oxide damage on the ID–VDS characteristics of short channel transistors. A decrease of the saturation current is observed as the degradation of the oxide increases. For these degradation levels, an increase in the threshold voltage and a decrease in the transconductance (Fig. 2) have been observed [4]. The same qualitative results were obtained for the long channel transistors (not shown here) although the variations of the transistor characteristics are more pronounced in this case. Figs. 3 and 4 show the evolution of the variations of the saturation currents and threshold voltages normalized to the fresh values, (IDSAT–IDSATFRESH)/IDSATFRESH and (VT–VTFRESH)/VTFRESH, respectively, as a function of the stress time for the different channel lengths. For the longer channel transistors, larger variations in the saturation current (Fig. 3) and the threshold voltage (Fig. 4) are
-2
SBD
-4
SBD
-6
X HBD -8
W / L = 10μm/0.175μm W / L = 10μm/10μm
-10 0
1000
2000
3000
4000
5000
6000
7000
Stress time (s)
Fig. 3. Relative variation of the saturation current as a function of the stress time for different transistor lengths.
8
SBD
7
X HBD 6 5
Δ VT / VT (%)
3. Results on transistors
0
SBD
4 3 2
Fresh Wear-out beforeSBD After SBD BSIM4
12.0m
Vgs = 1.5V
10.0m
W / L = 10μm/0.175μm W / L = 10μm/10μm
1 0
Vgs = 1.2V
0
1000
2000
3000
4000
5000
6000
7000
I D (A)
Time (s) 8.0m
Fig. 4. Relative variation of the threshold voltage as a function of the stress time for different transistor lengths.
Vgs = 0.9V 6.0m
4.0m
W / L = 10μm / 0.175μm
2.0m
0.0 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VD (V)
Fig. 1. ID–VDS curves measured for a fresh transistor and after different levels of oxide degradation. Symbols correspond to experimental data and continuous lines to the fitting of the data to the BSIM4 model.
3.0m
4.0m Fresh Wear-out before SBD After SBD BSIM4
2.5m
3.5m 3.0m
2.0m
1.5m
2.0m 1.5m
gm (V/A)
ID (A)
2.5m
1.0m 1.0m
observed. A possible explanation for these differences could be based on the geometry dependence of the dielectric degradation. The operation currents of the shorter transistors are larger, so that the effect of the oxide wear-out is not so visible as for the longer transistors. The BSIM4 model parameters have been extracted with Aurora software [5] for the fresh and worn-out transistors of both channel lengths. Good fittings of the experimental curves have been obtained in all the cases (continuous lines in Figs. 1 and 2 for the short channel transistors). It is important to note that the extracted BSIM4 transistor parameters take into account the dielectric degradation. On the other hand, the additional gate current due to oxide SBD has been described with the power law model [6]. 4. Current mirror
500.0µ 500.0µ
W / L = 10μm / 0.175μm 0.0 0.0
0.0 0.2
0.4
0.6
0.8
1.0
1.2
1.4
VG (V)
Fig. 2. ID–VG curves and transconductance measured for VDS = 0.1 V, for a fresh transistor and after different oxide damage. Symbols correspond to experimental data and continuous lines to the fitting of the data to the BSIM4 model.
To analyse the effects of the oxide wear-out in an analog circuit, a current mirror has been simulated using the extracted BSIM4 transistor parameters for several levels of oxide damage, for short and long channel transistors (Fig. 5). The current source in Fig. 5 models the BD current through the gate, when BD occurs in the overlap region between gate and source [3] and it is only included after
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 665–668 IIN
IOUT Wear-out in both transistors
IDSAT1
IOUT = IIN − IG1 − IG2
IDSAT2
1.5 V
T1
T2
.5 V
IG1 Wear-out ar-out in T2 I
OUT
I IN
=
I DSAT2
I DSAT1+ I G2
IG2
Fig. 5. Schematics of the current mirror used to analyse the effect of oxide degradation in the circuit performance. The current source is only included when the oxide breakdown has occurred.
the oxide BD (only one BD location is represented). Note that, in this circuit configuration, source BD corresponds to the worst case, since gate and drain are shortcircuited, so that the flow of BD gate current towards the drain will be negligible. For both geometries three different cases have been taken into account: (i) same wear-out of both transistors with gate current in both of them, (ii) wear-out on T2 transistor, without including the gate current in any of the two transistors and (iii) wear-out of T2, with gate current in both T1 and T2. For all cases, the figure of merit of the circuit performance, Iout/Iin, has been studied as a function of the stress time (Fig. 6). Equivalent conclusions would be drawn if the degradation was considered in T1. Fig. 6 shows that for case (i) the variation of the saturation currents as a consequence of the oxide degradation does not affect the circuit performance (Iout/Iin = 1) because both transistors have the same level of oxide damage and, therefore, the value of the saturation current is the same for both transistors during the whole stress. Only the BD current through the gate influences the circuit functionality. For short channel lengths (open triangles), before the
667
SBD, the symmetry of the drain currents is conserved and even after SBD the influence of the gate tunnel current is low (decrease of 3.3% in Iout/Iin). However, for the longer channel transistors (solid triangles), although before SBD the effect of the tunnel current is also low (but larger than for short channel devices), a strong decrease of 37% in the ratio Iout/Iin is observed after SBD. This result can be explained taking into account that, in this case, ISAT current of T1 and the gate currents for both transistors (see Fig. 6) contributes to the current Iin and that the saturation current is lower for long channel devices. Consequently, the contribution of the gate current to Iin is larger for long channel transistors so that the ratio Iout/Iin is lower. This effect is especially significant after the SBD where IGSBD = 0.01ISAT and Iout/Iin = 0.97 for short channel transistors and IGSBD = 0.35ISAT and Iout/Iin = 0.62 for the longer ones. For cases (ii) and (iii) oxide damage is considered to take place only in T2 (T1 remains fresh). Therefore, the saturation current is different for both transistors. For these cases, a small degradation of Iout/Iin is observed in short channel devices but there is no difference in considering or not the gate current. For longer devices, a small decrease in the figure of merit is observed when the tunnel current is considered before SBD. These observations can be explained taking into account that, before SBD, current through the gate due to oxide degradation is very low compared to the drain current operation values and consequently, the decrease of the Iout/Iin is due mainly to the reduction of the saturation current of the damaged transistor, which is larger for the longer transistors (Fig. 3). Therefore, before SBD, the variation of the model parameters as a consequence of oxide degradation has a more important effect on the functionality of the current mirror than the tunnel through the gate. When SBD takes place, there is a difference between (ii) and (iii), much more remarkable for the longer channel transistor (27% reduction of Iout/Iin) because in this case, the saturation currents are lower, so that BD gate current is relatively more important and has a larger influence in the ratio Iout/Iin. 5. Conclusions
1.00 0.95 0.90
IOUT / IIN
0.85 0.80
Pre SBD
SBD
Pre SBD SBD
0.75 0.70 White symbols - Short channel transistor Black symbols - long channel transistor
0.65 0.60
Wear-out in T2 with gate current Wear-out in T2 without gate current Wear-out in both transistors with gate current
0
1000
2000
3000
4000
5000
6000
7000
Time (s)
Fig. 6. Evolution of the Iout/Iin ratio of the current mirror shown in Fig. 6 for different levels of the degradation and transistor lengths as a function of the stress time. For short channel devices a lower influence of the tunnel current is observed.
The impact of wear-out and BD of the gate oxide of long and short channel nMOSFETS has been analysed. The wear-out of the oxide leads to a strong reduction in IDSAT and an increment of VT takes place. Longer channel transistors are more sensitive to the oxide degradation. BSIM4 model parameters of stressed long and short channel transistors have been extracted for different levels of oxide degradation. In addition to the BSIM4 parameters, a current source must be added to model the gate current when BD takes place. The influence on a current mirror performance of the gate current and the transistor parameter variation due to oxide degradation has been separately analysed. As expected, the wear-out effects are more important in longer devices due to the differences between the
668
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 665–668
operation currents and the gate tunnel current. If both transistors of the circuit are simultaneously degraded the circuit performance is not strongly affected. Only the BD of the devices provokes a decrease of the figure of merit, especially for long channel devices. In this case, the transistor parameters variation has little influence (because the symmetry of the circuit is conserved) and only the gate current influences the circuit performance, increasing its effect for higher levels of degradation and longer devices. However, when only one of the devices is damaged, the degradation of the circuit performance is more important, being again larger for long channel devices. In this case, the BD of the device provokes an important decrease of the figure of merit of the circuit.
Acknowledgements This work has been partially supported by the Spanish MCyT (TEC2004-00798/MIC) and the DURSI of the Generalitat de Catalunya (2005SGR-00061). References [1] International Technology Roadmap for Semiconductors. Semiconductor Industry Association. http://public.itrs.net. [2] Kaczer B et al. IEEE Trans Electron Dev 2002;49(3):500–6. [3] Rodrı´guez R et al. IEEE Electron Dev Lett 2003;24(2):114–6. [4] Cester A et al. In: IRPS proceedings, 2003. p. 189–95. [5] http://www.synopsys.com/products/mixedsignal/aurora_ds.html. [6] Miranda E et al. IEEE Electron Dev Lett 1999;20:265–7.