Role of the substrate during pseudo-MOSFET drain current transients

Solid-State Electronics 54 (2010) 316–322

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Role of the substrate during pseudo-MOSFET drain current transients K. Park, P. Nayak, D.K. Schroder * Dept. of Electrical Engineering and Center for Solid State Electronics, Arizona State University, Tempe, AZ 85287-5706, USA

a r t i c l e

i n f o

Article history: Received 21 July 2009 Received in revised form 16 September 2009 Accepted 3 October 2009 Available online 6 November 2009 The review of this paper was arranged by Prof. A. Zaslavsky

a b s t r a c t Drain current transients in floating-body SOI MOSFETs are of considerable interest for possible application for capacitor-less dynamic access random memories. For maximum refresh time of such memories, it is important that the carrier lifetime in the Si film of such devices be high or the leakage current be low. We present here a detailed study, both experimental and by simulation, of the measurements of drain current transients that are commonly used to extract the carrier lifetime, using p-film-p-substrate pseudo-MOSFETs. In contrast to other papers in this field, we include the role of the substrate in such transients and find the substrate to dominate the drain current transient. Previous studies have largely neglected the substrate. Ó 2009 Elsevier Ltd. All rights reserved.

Keywords: Pseudo-MOSFET Silicon Generation lifetime Recombination lifetime Drain current transients

1. Introduction Drain current transients in SOI MOSFETs are commonly related to the floating body. Such floating body effects can be a nuisance or an opportunity. When they are controlled, e.g., through impact ionization at the reverse-biased body/drain junction, they can be used for capacitor-less or zero-capacitor dynamic access random memories (Z-RAM) originally proposed by Okhonin et al. [1] and recently reviewed by Bawedin et al. [2]. Originally these devices operated on the MOSFET principle using the channel current [3– 5], but a more recent version operates on the bipolar junction transistor (BJT) principle using the BJT current [6–8]. An important aspect of such devices is the retention time, that is related to the floating body generation/recombination lifetimes. The refresh time in conventional DRAMs is typically 300–500 ms. Hence the storage time of the DRAM diode should be 3–5 s at 85 °C and the room temperature generation lifetime should be around 1 ms for moderately doped Si films. The generation lifetime is frequently determined from the leakage current of pn junctions or the recovery time of pulsed MOS capacitors [9]. It is, however, also possible to determine it from the drain current of floating-body SOI MOSFETs upon pulsing the gate. This can, of course, be done on completed MOSFETs. However, it is useful to use a simpler test structure without fabricating entire devices.

* Corresponding author. Tel.: +1 480 965 6621; fax: +1 480 965 8118. E-mail address: [email protected] (D.K. Schroder). 0038-1101/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2009.10.002

The pseudo-MOSFET (W-MOSFET) is such a simple test structure to determine a variety of Si film and film/oxide properties. In its simplest form it consists of two probes placed on the Si film forming the source and drain, the substrate being the gate and the buried oxide (BOX) the gate oxide [10]. Other implementations use Hg probes [11], evaporated metal films for source/drain contacts [12], or four probes [13]. In most cases, the source and drain are Schottky diodes, as the Si film is usually lightly to moderately doped. However, it is believed that pressure-adjustable probes are ohmic due to the defects introduced by the high pressure at the probe points. Since the substrate is the gate in W-MOSFETs, one may expect the substrate and the BOX/substrate interface to play a role in the device operation, especially during the transients. For example, for p-type substrates with negative gate bias, the substrate is driven into depletion, inversion, or deep depletion depending on whether the gate voltage is steady-state or suddenly applied. As transient W-MOSFET measurements are used to determine generation and recombination parameters of the Si film [14], it is important to understand the role of the substrate. SOI MOSFET drain current transients were first observed on thin Si film located on top of oxidized poly-Si substrates, silicon-onsapphire MOSFETs, n+nn+ MOSFETs, and n+pn+ MOSFETs [15–17]. Ioannou et al. drive the SOI MOSFET with top and bottom gate from depletion or accumulation to stronger accumulation to create a deep-depletion condition to extract the generation lifetime and surface generation velocity [18]. They mention that a deep-depletion layer can also be created in the substrate following the bias step and suggest its elimination by applying the bias step on the

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2. Experimental We used two types of SOI samples, bonded strained (sSOI) and unstrained SOI. The sSOI has Si film and buried oxide (BOX) thicknesses of tSi  80 nm, tBOX = 145 nm, and NA  1015 cm3 for both Si film and substrate. The Si film is strained to 1.4 GPa stress after SiGe layer removal. The normal, unstrained SOI has about the same

S

ID VD S p D

p

S

Si

BOX VGb Fig. 1. Cross-sectional and top views. The drain is the centered 100 lm  100 lm square, surrounded by bare Si, surrounded by the 100 lm wide source. The gap between drain and source is 100 lm.

sample specification with sSOI, except for the strain. The device structure is shown in Fig. 1. The samples were dry oxidized at 900 °C for oxide thicknesses of 50 nm and 30 nm to form top gate oxides for top-gated devices which are not discussed in this paper. After oxidation, the thicknesses were SiO2/Si/BOX = 54/53/145 nm for sSOI and 29/76/ 145 nm for unstrained SOI. The device area was isolated from the rest of the samples to reduce possible leakage current through BOX pin holes or sample edge by etching the top thermal oxide and Si film with buffered oxide etchant (BOE) and reactive ion etching. The thermal oxide was etched with BOE. 150 nm Ti/ 100 nm Al metal contacts were e-beam evaporated on the bare Si surface and defined by photolithography. The innermost 100 lm  100 lm square is the drain and the outermost contact the source. After metal deposition, samples were forming gas (5% H2 + 95% N2) annealed at 400 °C/20 min. All electrical measurements were made in a dark Micromanipulator probe station at room temperature with an Agilent 4155C parameter analyzer. The integration time for the measurement unit was set to default long and the hold time was typically 100 s for these measurements, unless stated otherwise in the paper. Typical drain current–back-gate voltage (ID–VGb) characteristics of a device with low hole and high electron Schottky barriers are shown in Fig. 2, with the hole current substantially higher than the electron current; the semilog plot shows IDp to be about 3  104 times higher than IDn. Taking the ratio of the Schottky barrier current as

Ap expðq/B p=kTÞ Ip ¼ 3  104 ¼  An expðq/Bn =kTÞ In ) /Bp  /Bn  kT ln 105 ¼ /Bn  0:3 eV shows the hole barrier height to be 0.3 eV lower than the electron barrier height. Next, we discuss the various transients we observe, i.e., positive or negative back-gate voltage (VGb) pulse. 10-4

Drain Current (A)

front gate instead of the back gate. However, by using p-type Si films and n-type substrates and pulse biasing the substrate with negative voltages, the substrate is always in accumulation. Cristoloveanu and Elewa pulse the pseudo-MOSFET substrate without front gate into accumulation and determine the Si film generation lifetime from the drain current transient [19]. Munteanu et al. use a variety of front or back gate pulses of SOI MOSFETs to drive the Si film into the recombination or generation regime [20]. Maintaining one gate at ground and pulsing the other gate to drive the film into inversion, leaves majority carriers in the film which are eliminated through recombination giving a drain current overshoot. Switching the gate from strong to weak inversion, leads to a drain current undershoot and steady state is reached through carrier generation. Detailed experiments and simulations were carried out, but the effect of substrate transients was not considered in the analyses. Shin et al. apply a negative step voltage to the partially depleted SOI MOSFET gate [21,22]. The floating body potential becomes negative during the transient, forcing the threshold voltage to increase. The drain current is suppressed immediately after the negative voltage step and it gradually increases to the steady-state value through carrier generation. The drain current reaches steady state as carriers are generated. Munteanu et al. maintain the SOI MOSFET back gate grounded and pulse the front gate from depletion or accumulation to strong inversion [23]. Minority carriers to form the inversion channel are supplied by the source/drain regions. The positive pulse on the front gate leads to lowering of the threshold voltage and resulting in excess drain current. Steady state is reached through carrier recombination. Yasuda et al. show that the generation lifetime in fully-depleted films can also be determined [24]. Sato et al. step the gate voltage from positive voltage to zero. The resulting drain current decay is attributed to recombination in the SOI film [25]. Martino et al. ground the back gate of the SOI MOSFET and switch the front gate from an ‘‘on” gate bias higher than the threshold voltage, to an ‘‘off” bias in weak inversion. The generation lifetime is then determined as a function of device temperature [26]. Lim and Fossum analyze the recombination and generation transients [27]. When the device is turned on by a step pulse at the front gate, inversion charge is quickly injected into the channel from the source and forces the holes in the film toward the source, forward biasing the source/body junction, injecting electrons into the film to neutralize the holes. Steady state is reached through recombination. When the device is turned off abruptly, the body potential is initially negative and then increases toward zero in time as the space–charge region shrinks due to electron–hole pair generation. Most of these papers use MOSFETs for their measurements. For n+pn+ and n+nn+ devices, the source/drain cannot supply holes. For point-contact pseudo-MOSFETs, the point contacts may be ohmic, supplying electrons or holes. For Schottky-contact W-MOSFETs, the source/drain electron or hole supply depends on the barrier height. Cristoloveanu et al. report that the substrate plays no role during the drain current transient for their point contact W-MOSFET measurements [28]. We believe the substrate to dominate the drain current transients during our negative back-gate bias transient drain current measurements for p-film/p-substrate devices and discuss this effect in more detail here.

10-5

ID3 ID2

ID1

VD = 0.2 V Al contact

10-6 10-7 10-8 10-9 10-10 -20 -15 -10 -5

0

5

10 15 20

Back Gate Voltage (V) Fig. 2. Typical ID–VGb characteristics for low /Bp.

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2.1. 0 to VGb

The fact that gate current flows during the drain current transient clearly shows that substrate generation is important during the transient. If the transient were due to ehp generation in the Si film, the gate and drain currents would be decoupled. To measure the substrate generation directly, we used the Si film islands as a gate of an MOS capacitor (MOS-C) with contact to the source in Fig. 1. The transient capacitance in Fig. 5, measured by applying gate voltage steps to drive the substrate into deep depletion, gives capacitance transient times very similar to the drain/gate current transient times in Fig. 4. In this MOS-C, the recovery is due to ehp generation in the substrate only, since the Si film in this device acts merely as a gate. The effective generation lifetime, determined from the C–t transient, is about 200 ls – a reasonable value for SOI substrates. Occasionally we observe the ID–t behavior in Fig. 6. The ID transient time increases initially with increased negative back-gate voltages, but then appears to decrease beyond 15 V in Fig. 6a. This is very puzzling as it is not at all obvious why the transient time should decrease. The gate current and its transient time, however, continue to increase in Fig. 6b. The ID–t plots in Fig. 6a shows an approximately linear ID increase with time, followed by saturation for VGb P 10 V. Beyond that voltage, however, two slopes begin to emerge. Slope (1) follows that of the lower voltages while slope (2) is steeper, leading to apparent shorter transient times. But a closer examination of the curves shows the transient time to actually increase with more negative VGb. Although the latter portion of the ID–t curves appears constant; it actually rises slightly and the total transient times of the ID–t and IG–t curves are identical. The increase in the ID–t transient time with increasing VGb is due to the creation of a wider substrate space–charge region below the BOX at higher gate bias, requiring longer time to return to stea-

We use the W-MOSFET cross section in Fig. 3 to explain the transient behavior. Consider a negative back-gate voltage step, e.g., VGb = 10 V applied at t = 0. At t = 0+ the drain current changes rapidly from ID1 to ID2 in Fig. 2. Most of the substrate voltage is dropped across the deep-depleted substrate space–charge region (scr) and the buried oxide. The Si film hole charge density is Qp2, and the substrate space–charge region charge density is Qb2. There is very low inversion charge density Qn. Electron–hole pair generation in the substrate scr is shown by the closed circles (electrons) and open circles (holes). Some of the holes neutralize ionized acceptors in the scr while others leave the substrate as gate current, IG. The required holes for the ID1 ) ID2 transition are supplied by the Schottky drain contact, shown by the band diagram in Fig. 3. The substrate inversion layer Qn increases with time as ehp are generated in the substrate. With negative substrate charge density increasing, Qp2 also increases and the drain current changes to ID3 in Figs. 2 and 4a. We note that although the substrate generation plays a dominant role, it is, of course, the drain current we measure in these experiments, but we also measure the gate current, because it is a direct measure of substrate ehp generation. The reason the substrate plays such an important role is that it changes the potential and threshold voltage of the floating Si film. When VGb is applied, a large fraction is dropped across the substrate scr. As this scr collapses due to ehp generation, the scr voltage decreases and the Si film becomes more negatively biased by capacitive coupling of VGb. If the drain current transient is predominantly determined by substrate generation, then the gate current should have a similar time dependence, as is indeed the case, illustrated in Fig. 4b.

ID2 VD

Qb2

+

+

+ + - - - - - - - p

EC VD

φ Bp

EF EV

Qp2

A = 36x10-4 cm2

3 10-11

Vinv = 0 to 20 V

2 10-11

30 V

1 10-11

IG

0

0

VGb

-10 V

0

50

100 150

200

250

Time (s)

t

Fig. 3. Cross sectional diagram and band diagram at t = 0+.

Fig. 5. MOS-C transient capacitance.

(a)

(b)

1 10 -4

VD = 0.2 V Al contact

8 10 -5

-20 V

6 10 -5

ID3 -10 V

4 10 -5

VGb = 0 to -5 V

2 10 -5 0

ID2 0

100

0.0

-30 V

200

Time (s)

300

400

Gate Current (A)

Qn

+

Drain Current (A)

QBOX

Capacitance (F)

Qp2

4 10-11

-5 V

-10 V

-5.0 10-12

-20 V

VGb = 0 to -30 V -1.0

10-11

-1.5 10-11 0

VD = 0.2 V Al contact 100

200

300

Time (s)

Fig. 4. (a) Drain and (b) gate current versus time as a function of back-gate voltage pulse.

400

300

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K. Park et al. / Solid-State Electronics 54 (2010) 316–322

(a)

(b)

10-6

-20 V -15 V

(2)

10-8

Gate Current (A)

Drain Current (A)

10-7

-13 V -10 V

(1)

-7 V -5 V

10-9 10-10

-1 10-11

VGb = -30 V

Experiment 0

50

100

-2 10-11

VGb = -30 V -20 V

-3 10-11 -4 10-11 -5 10-11

150

-7 V -5 V

-10 V

-15 V -13 V

VD = 0.2V 0

50

100

150

200

Time (s)

Time (s)

Fig. 6. (a) Drain current and (b) gate current versus time as a function of back-gate voltage pulse.

(a)

(b)

10-5

ID1

1 10-8

VD = 0.2 V Al contact

Drain Current (A)

Drain Current (A)

10-4

10-6 10-7

ID4

10-8

ID5

10-9 10-10 -20

8

10-9

6

10-9

VD = 0.2 V Al contact 2.2 10 -9

VGb = 0 to 20 V

2.0 10 -9

ID5

4 10-9 2 10-9

30 V

ID4

1.8 10 -9 0

20 V

100 200 300 400

VGb = 0 to 10 V -10

0

10

0 0

20

100

Back Gate Voltage (V)

Gate Current (A)

(c)

200

300

400

Time (s)

5 10-12

VD = 0.2 V

VGb = 0 to 10, 20, 30 V

0

-5 10-12

0

100

200

300

400

Time (s) Fig. 7. (a) ID–VGb, (b) ID–t and (c) IG–t for positive back-gate voltages.

dy-state by ehp generation. The transient drain current time is proportional to IG–t; therefore we observe an increasing ID–t transient time with increasing negative back-gate voltage. A more detailed explanation of the transient time dependence on substrate generation is given in the simulation section. The behavior of Figs. 4 and 6 depends on the S/D Schottky barrier work functions. For a better understanding of this behavior, we did extensive simulations. 2.2. VGb: 0 to +VGb Positive gate voltage steps in Fig. 7 give very different results than negative ones. In this case the electron barrier height is high and the steady-state electron drain current is low, shown in Fig. 7a. At zero back-gate voltage, the hole current is ID = 4  106 A. Positive back-gate voltage step biases the floating Si film positively, reduces the threshold voltage, drives holes very rapidly to the substrate/BOX interface, and drives the Si film/BOX interface into

inversion. The drain current changes rapidly from ID1 to ID4 and then slowly to ID5. Since the Si film/BOX interface is initially accumulated, it takes some time for these holes to recombine, leading to a drain current overshoot and subsequent ehp recombination. The drain current change in this case, Fig. 7b, is much less than for VGb pulses, because the transient is governed by recombination in the Si film. The gate or substrate current in Fig. 7c has very short transient time and it is obvious that this transient is unrelated to the ID–t transient, with the substrate playing essentially no role.

3. Simulations 3.1. VGb: 0 to VGb The pseudo-MOSFET transient effects were simulated with ATLAS/SILVACO. The drain current is shown as current/unit width.

K. Park et al. / Solid-State Electronics 54 (2010) 316–322

Drain Current (A/μm)

5 10-8

VGB = 0 to -10 V VD = 0.2 V

4 10-8

5 1017

τFilm,Sub = 10-4 s

10-8

Nf

=1011

cm-2

nsub

1 10-8 0

0

6 1017

φBp = 0.49 eV 4 1017

ID

3 10-8 2

pch

40

80

3

1017

2 1017 1 1017

0 160

120

(b) Gate Current (A/μm)

(a)

Carrier Concentration (cm-3)

320

0

-2 10-15 0.49 eV -4 10-15

τFilm,Sub = 10-4 s Nf =1011 cm-2

-6

10-15

-8 10-15

VGB = 0 to -10 V VD = 0.2 V

φBp = 0.59 eV 0

40

80

120

160

Time (s)

Time (s) Fig. 8. (a) ID, pch, nsub and (b) IG versus time.

The simulated device dimensions: 6 lm thick substrate, 145 nm thick BOX, 55 nm thick Si film, 100 lm long source, drain and Si film, p-type Si film and p-type substrate with NA = 1015 cm3, and Nf (fixed oxide charge density at BOX/substrate and BOX/film interfaces) = 1011 cm2. The thin substrate was chosen to reduce the simulation time. Concentration- and field-dependent mobility, Shirahata and Klaassen mobility models, Shockley–Read–Hall recombination model, band gap narrowing and impact ionization model are included in the simulations. The substrate voltage in the simulations falls from zero to VGb in 1 ls and remains at VGb for 200 s. After the negative substrate voltage pulse is applied, the substrate below the BOX enters deep depletion and the Si film remains almost neutral (pfilm  1015 cm3). The 6 lm thick substrate contains the deep-depleted scr at all times.

3 10-8

VGb = 0 to -10 V Nf =1011cm-2

τfilm,sub=10-4

150 s

12

Energy (eV)

4

10-8

ID (φBp= 0.49 eV)

s

VD = 0.2 V

2 10-8

8

ID (φBp=0.59 eV)

0 0

40

80

120

BOX Si Film

Drain Current (A/μm)

t = 0.5 s

Ec Ev

Ev

Substrate

1

2

3

4

Distance (μm)

160

Fig. 11. Simulated band diagrams through Si film, BOX and substrate at the source with x = 0 the Si film surface. The inset shows the Si film band diagram. /Bp = 0.49 eV.

Fig. 9. Effect of change in hole barrier height on drain current transients.

(b)

4 10-8

4 10-8

τfilm=10-4,10-5,10-6 s

3 10-8

φBp = 0.49 eV

2 10-8

τsub = 10-4 s Nf = VD = 0.2 V VGb = 0 to -10 V 1011

1 10-8

0

70,150 s

t = 0.5 s

0

0

Time (s)

(a)

Ev

70 s

4

-4

1 10-8

0

50

100

Time (s)

150

cm-2

200

Drain Current (A/μm)

Drain Current (A/μm)

5 10-8

At t = 0+, most of the back-gate voltage drops across the substrate space–charge region and the BOX and only a small fraction appears across the film. The source and the drain Schottky contacts are reverse biased as the p-type film is negatively biased with respect to the source and drain. The film below the drain contact is more reverse biased than the region below the source contact as the drain is held at +0.2 V and the source is grounded. The electrons from ehp generation in the substrate space–charge region move towards the substrate/BOX interface, some of the holes neutralize the scr acceptor ions and some leave the substrate to enter the Si film through the drain contact, leading to a decrease in the substrate scr width and a rise in the hole concentration in the film and the drain current. Fig. 8a shows the ID transient along with the Si film hole concentration, pch, probed 5 nm above the BOX and the substrate electron concentration, nsub, probed 10 nm below the BOX and Fig. 8b

10-6 s

3 10-8 10-5 s

τsub=10-4 s φBp = 0.49 eV

2 10-8

τfilm = 10-4 s Nf = 1011 cm-2 VD = 0.2 V VGb = 0 to -10 V

1 10-8 0

0

50

100

150

200

Time (s)

Fig. 10. Effects of substrate and film carrier lifetimes on drain current transients. (a) ssub = 104 s, sfilm varies and (b) sfilm = 104 s, ssub varies.

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shows the gate current transient. All transients terminate at the same time similar to the experimental data. The ‘‘wiggles” in the gate current plot are an artifact of the simulation. As expected, the gate current is independent of the S/D barrier height. The drain current, however, does depend on the barrier height, as illustrated in Fig. 9. Higher /Bp leads to lower ID, as expected, but also to lower transient times. The drain current saturates with VGb for high /Bp, suggesting that for high /Bp, the drain current transient time is

Concentration (cm-3)

1018 1016 1014

(b)

(a)

(c)

200 s

38 s

Holes

16 s

Holes

1012

t = 0.5 s

1010 108 106

Electrons

Electrons

104 10

2

0 10 20 30 40 50

0 10 20 30 40 50

Distance (nm)

Distance (nm)

0 10 20 30 40 50

Distance (nm)

Fig. 12. Simulated carrier concentrations through the Si film for different times at (a) the middle of the film, (b) the drain and (c) the source. /Bp = 0.59 eV. x = 0 corresponds to the film surface and x = 55 nm to the film/BOX interface.

0.4 0.3

(a)

(c)

(b)

0.1 0

Source

t = 0.5 s

-0,1

Drain

Potential (V)

0.2

-0.2

16 s

-0.3

38 s

-0.4

200 s

-0.5 -0.6

0 10 20 30 40 50

0 10 20 30 40 50

0 10 20 30 40 50

Distance (nm)

Distance (nm)

Distance (nm)

Fig. 13. Simulated potential through the film as a function of time at (a) center of the film, (b) the drain and (c) the source. The vertical dashed line is the metal/ semiconductor interface. /Bp = 0.59 eV.

Energy (eV)

1.6

Channel

EC

1.2 0.8

200 s 38 s

0.4

EV

0 0

16 s t = 0.5 s 100

200

Distance (μm)

Source

1018

Drain

Hole Concentration (cm-3)

Source

governed by barrier height while for lower /Bp it is governed by substrate ehp generation. The effects of film and substrate lifetimes are shown in Fig. 10. If the film lifetime plays a role in the drain current transient, then changing the film carrier lifetimes should affect the drain current transient and if the substrate lifetime contributes to the holes in the film then changing the carrier lifetimes in the substrate should affect the drain current transient. Fig. 10a shows the drain current transient for changes in film carrier lifetimes with a constant substrate carrier lifetime and Fig. 10b shows the drain current transient for changes in substrate carrier lifetimes with a constant film carrier lifetime. We observe that changing the film carrier lifetime has negligible impact on the drain current transient whereas changing the substrate carrier lifetimes changes the ID transient times significantly. To understand the transient mechanism in more detail, we simulated various potentials and carrier distributions. Fig. 11 shows band diagrams from the source to the substrate contact. When the negative gate voltage is applied, the substrate scr is 3 lm deep. The edge of this scr has a potential close to 10 V. As ehp are generated, the scr shrinks, the potential across it drops and the potentials across the BOX and Si film increase. Fig. 12 shows the carrier distributions under source and drain to be quite similar, but quite different from those in the middle of the film between S and D. The middle of the film is never depleted while the regions in the film close to the upper surface under the S and D are depleted, but the hole concentration at the film/BOX interface ranges from about 1011 cm3 immediately after pulse application to 1018 cm3 at the end of the transient time. The hole concentration rate of change at the film/BOX interface and the electron concentration at the substrate/BOX interface (Fig. 8a) indicate that it is indeed the substrate that dominates the drain current transient. The Si film potentials at various locations through the device at source, drain and center are shown in Fig. 13. The potentials at the contact/film interface at S/D are held constant at 0 and 0.2 V, but the surface potential in the region between S/D varies with time. The potentials become more negative with time, attracting more holes to the film/BOX interface and the time dependence is that of substrate ehp generation. The potential along the device at the film/BOX interface is clearly non-uniform, being more negative in the center region. The band diagrams along the film, at 5 nm above the film/BOX interface in Fig. 14, show initially substantial barriers at S/film and D/film interfaces. Toward the end of the transient, these barriers diminish substantially and the hole concentration along the film, very non-uniform initially, becomes reasonably uniform with time in Fig. 14. The hole concentrations under S and D are very low initially due to the reverse-biased S/D junctions and as the bias becomes less reverse biased, the hole concentrations in-

300

Channel

Drain 200 s

1017

38 s

16

10

16 s 1015 1014 1013 12

10

t = 0.5 s 0

100

200

300

Distance (μm)

Fig. 14. Simulated band diagrams and hole concentrations along the film from S to D 5 nm above the film/BOX interface. /Bp = 0.59 eV.

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crease significantly from 5  1012 to 4  1017 cm3. In the channel they are never lower than 1016 cm3. Our device, in the VGb transient mode, operates through the formation of an accumulated channel at the film/BOX interface. The reverse-biased Schottky drain junction supplies majority holes. These holes accumulate in the channel and leave through the source contact. The amount of holes that can be supplied depends on the barrier height of the drain Schottky contact. The lower the barrier height the more holes can be supplied, giving rise to a higher and faster rise of the drain current as seen in Fig. 9. The band diagrams in Fig. 14 show a space–charge region at both ends of the channel with the source end less depleted than the drain end. The channel is at a lower potential than the region below the source and the drain. The depletion at the drain side does not pose any barrier to the holes, but the space–charge region at the source plays a major role in controlling the drain current. The source-side scr is a barrier to holes from the channel as the holes need to cross over this barrier to flow to ground. The two slopes in ID–t are mainly due to the initial non-uniform accumulation followed by the gradual uniform accumulation of the film at the BOX/film interface. During the early part of the transient, the source end remains depleted and holes accumulate in the channel, lowering the channel potential compared to the source and drain junctions and resulting in a higher barrier from the channel to the source. Sufficiently energetic holes overcome this barrier, leading to lower ID. Later, ID rises and a barrier develops along the channel and the drain junction due to a difference in hole concentration (channel becomes p+ and drain end is still depleted or neutral). This barrier slows the flow of holes (0–16 s). After 16 s, the source starts to accumulate and the source end accumulates faster and a larger section below the source is accumulated compared to the drain end, lowering the barrier at the source end. As the source end becomes more accumulated, the barrier decreases further and ID increases at a faster rate (16–150 s). Towards the end of the transient, the potential barrier between the channel and the source becomes minimal, does not reduce further and the drain current saturates after 150 s. 4. Conclusions The role of the substrate in SOI device behavior is frequently neglected. During pseudo-MOSFET measurements, however, the substrate becomes the gate and can influence the SOI MOSFET drain current significantly. Just as the poly-Si gate in conventional MOSFETs influences the drain current through gate depletion, so it happens in pseudo-MOSFETs as well, but more severely since the gate in such devices is lightly doped. We have carried out detailed experiments and simulations with metal-gate W-MOSFETs and show that for negative back-gate voltage pulses, the drain current transient is dominated by substrate electron–hole pair generation. Negative back-gate voltage pulses lead to a substantial voltage drop across the substrate deep-depletion space–charge region, which, in turn, affects the Si film potential and the drain current. For positive back-gate voltages, the substrate plays almost no role and the transient is dominated by the Si film. Acknowledgments The research leading to this paper was partially funded by the Silicon Wafer Engineering and Defect Science Consortium (SiWEDS) (Hynix Semiconductor, Intel Corp., LG Siltron, MEMC Electronic Materials, Samsung Electronics, Siltronic, SOITEC, and SUMCO TECHXIV). We thank G. Celler from Soitec USA and M.

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